From 7dddc1a387f34772cf3dd7a09475fadfbae9ae0d Mon Sep 17 00:00:00 2001
From: Troy Kisky <troy.kisky@boundarydevices.com>
Date: Wed, 16 Oct 2019 14:06:26 -0700
Subject: [PATCH] nitrogen8mm_som: lpddr4_timing: add DDR_PHY_Dq0LnSel_0
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
---
.../boundary/nitrogen8mm_som/lpddr4_timing.c | 33 +++++++++++++++++++
1 file changed, 33 insertions(+)
diff --git a/board/boundary/nitrogen8mm_som/lpddr4_timing.c b/board/boundary/nitrogen8mm_som/lpddr4_timing.c
index a77b266eb69..11348dddf4a 100644
--- a/board/boundary/nitrogen8mm_som/lpddr4_timing.c
+++ b/board/boundary/nitrogen8mm_som/lpddr4_timing.c
@@ -158,6 +158,39 @@ static struct dram_cfg_param lpddr4_ddrc_cfg[] = {
/* PHY Initialize Configuration */
static struct dram_cfg_param lpddr4_ddrphy_cfg[] = {
+ { 0x100a0, 0x0 }, /* DDR_PHY_Dq0LnSel_0 */
+ { 0x100a1, 0x1 },
+ { 0x100a2, 0x2 },
+ { 0x100a3, 0x3 },
+ { 0x100a4, 0x4 },
+ { 0x100a5, 0x5 },
+ { 0x100a6, 0x6 },
+ { 0x100a7, 0x7 },
+ { 0x110a0, 0x0 },
+ { 0x110a1, 0x1 },
+ { 0x110a2, 0x3 },
+ { 0x110a3, 0x4 },
+ { 0x110a4, 0x5 },
+ { 0x110a5, 0x2 },
+ { 0x110a6, 0x7 },
+ { 0x110a7, 0x6 },
+ { 0x120a0, 0x0 },
+ { 0x120a1, 0x1 },
+ { 0x120a2, 0x3 },
+ { 0x120a3, 0x2 },
+ { 0x120a4, 0x5 },
+ { 0x120a5, 0x4 },
+ { 0x120a6, 0x7 },
+ { 0x120a7, 0x6 },
+ { 0x130a0, 0x0 },
+ { 0x130a1, 0x1 },
+ { 0x130a2, 0x2 },
+ { 0x130a3, 0x3 },
+ { 0x130a4, 0x4 },
+ { 0x130a5, 0x5 },
+ { 0x130a6, 0x6 },
+ { 0x130a7, 0x7 },
+
{ 0x1005f, 0x1ff },
{ 0x1015f, 0x1ff },
{ 0x1105f, 0x1ff },
--
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