From 79ef7eefe426c4efcf21843cf06df12c7ae8e660 Mon Sep 17 00:00:00 2001
From: mntmn <lukas@mntmn.com>
Date: Thu, 21 May 2020 16:34:04 +0200
Subject: [PATCH] reform2: dump clocks and test some DDR bytes in SPL
---
arch/arm/mach-imx/imx8m/clock_imx8mq.c | 52 ++++++++++++++++++++++++
board/boundary/nitrogen8m_som/spl.c | 55 ++++++++++++++++++++++++--
2 files changed, 104 insertions(+), 3 deletions(-)
diff --git a/arch/arm/mach-imx/imx8m/clock_imx8mq.c b/arch/arm/mach-imx/imx8m/clock_imx8mq.c
index 3f37af8545f..4b73dcc760c 100644
--- a/arch/arm/mach-imx/imx8m/clock_imx8mq.c
+++ b/arch/arm/mach-imx/imx8m/clock_imx8mq.c
@@ -924,3 +924,55 @@ U_BOOT_CMD(
""
);
#endif
+
+int mx8mq_showclocks() {
+ u32 freq;
+
+ freq = decode_frac_pll(ARM_PLL_CLK);
+ printf("ARM_PLL %8d MHz\n", freq / 1000000);
+ freq = decode_sscg_pll(SYSTEM_PLL1_800M_CLK);
+ printf("SYS_PLL1_800 %8d MHz\n", freq / 1000000);
+ freq = decode_sscg_pll(SYSTEM_PLL1_400M_CLK);
+ printf("SYS_PLL1_400 %8d MHz\n", freq / 1000000);
+ freq = decode_sscg_pll(SYSTEM_PLL1_266M_CLK);
+ printf("SYS_PLL1_266 %8d MHz\n", freq / 1000000);
+ freq = decode_sscg_pll(SYSTEM_PLL1_200M_CLK);
+ printf("SYS_PLL1_200 %8d MHz\n", freq / 1000000);
+ freq = decode_sscg_pll(SYSTEM_PLL1_160M_CLK);
+ printf("SYS_PLL1_160 %8d MHz\n", freq / 1000000);
+ freq = decode_sscg_pll(SYSTEM_PLL1_133M_CLK);
+ printf("SYS_PLL1_133 %8d MHz\n", freq / 1000000);
+ freq = decode_sscg_pll(SYSTEM_PLL1_100M_CLK);
+ printf("SYS_PLL1_100 %8d MHz\n", freq / 1000000);
+ freq = decode_sscg_pll(SYSTEM_PLL1_80M_CLK);
+ printf("SYS_PLL1_80 %8d MHz\n", freq / 1000000);
+ freq = decode_sscg_pll(SYSTEM_PLL1_40M_CLK);
+ printf("SYS_PLL1_40 %8d MHz\n", freq / 1000000);
+ freq = decode_sscg_pll(SYSTEM_PLL2_1000M_CLK);
+ printf("SYS_PLL2_1000 %8d MHz\n", freq / 1000000);
+ freq = decode_sscg_pll(SYSTEM_PLL2_500M_CLK);
+ printf("SYS_PLL2_500 %8d MHz\n", freq / 1000000);
+ freq = decode_sscg_pll(SYSTEM_PLL2_333M_CLK);
+ printf("SYS_PLL2_333 %8d MHz\n", freq / 1000000);
+ freq = decode_sscg_pll(SYSTEM_PLL2_250M_CLK);
+ printf("SYS_PLL2_250 %8d MHz\n", freq / 1000000);
+ freq = decode_sscg_pll(SYSTEM_PLL2_200M_CLK);
+ printf("SYS_PLL2_200 %8d MHz\n", freq / 1000000);
+ freq = decode_sscg_pll(SYSTEM_PLL2_166M_CLK);
+ printf("SYS_PLL2_166 %8d MHz\n", freq / 1000000);
+ freq = decode_sscg_pll(SYSTEM_PLL2_125M_CLK);
+ printf("SYS_PLL2_125 %8d MHz\n", freq / 1000000);
+ freq = decode_sscg_pll(SYSTEM_PLL2_100M_CLK);
+ printf("SYS_PLL2_100 %8d MHz\n", freq / 1000000);
+ freq = decode_sscg_pll(SYSTEM_PLL2_50M_CLK);
+ printf("SYS_PLL2_50 %8d MHz\n", freq / 1000000);
+ freq = decode_sscg_pll(SYSTEM_PLL3_CLK);
+ printf("SYS_PLL3 %8d MHz\n", freq / 1000000);
+ freq = mxc_get_clock(UART1_CLK_ROOT);
+ printf("UART1 %8d MHz\n", freq / 1000000);
+ freq = mxc_get_clock(USDHC1_CLK_ROOT);
+ printf("USDHC1 %8d MHz\n", freq / 1000000);
+ freq = mxc_get_clock(QSPI_CLK_ROOT);
+ printf("QSPI %8d MHz\n", freq / 1000000);
+ return 0;
+}
diff --git a/board/boundary/nitrogen8m_som/spl.c b/board/boundary/nitrogen8m_som/spl.c
index 4b72cb236a0..484e95b43cd 100644
--- a/board/boundary/nitrogen8m_som/spl.c
+++ b/board/boundary/nitrogen8m_som/spl.c
@@ -54,6 +54,8 @@ int board_mmc_getcd(struct mmc *mmc)
switch (cfg->esdhc_base) {
case USDHC1_BASE_ADDR:
return 1;
+ case USDHC2_BASE_ADDR:
+ return 1;
}
return 0;
}
@@ -62,6 +64,10 @@ int board_mmc_getcd(struct mmc *mmc)
PAD_CTL_FSEL2)
#define USDHC_GPIO_PAD_CTRL (PAD_CTL_PUE | PAD_CTL_DSE1)
+#define USDHC2_CD_GPIO IMX_GPIO_NR(2, 12)
+#define USDHC1_PWR_GPIO IMX_GPIO_NR(2, 10)
+#define USDHC2_PWR_GPIO IMX_GPIO_NR(2, 19)
+
static iomux_v3_cfg_t const init_pads[] = {
#define GP_I2C1_PCA9546_RESET IMX_GPIO_NR(1, 4)
IMX8MQ_PAD_GPIO1_IO04__GPIO1_IO4 | MUX_PAD_CTRL(0x46),
@@ -78,11 +84,22 @@ static iomux_v3_cfg_t const init_pads[] = {
IMX8MQ_PAD_SD1_DATA7__USDHC1_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
#define GP_EMMC_RESET IMX_GPIO_NR(2, 10)
IMX8MQ_PAD_SD1_RESET_B__GPIO2_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
+
+ IMX8MQ_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
+ IMX8MQ_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
+ IMX8MQ_PAD_SD2_DATA0__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
+ IMX8MQ_PAD_SD2_DATA1__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
+ IMX8MQ_PAD_SD2_DATA2__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0x16 */
+ IMX8MQ_PAD_SD2_DATA3__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
+ IMX8MQ_PAD_SD2_CD_B__GPIO2_IO12 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL),
+ IMX8MQ_PAD_SD2_RESET_B__GPIO2_IO19 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL),
};
static struct fsl_esdhc_cfg usdhc_cfg[] = {
{.esdhc_base = USDHC1_BASE_ADDR, .bus_width = 8,
.gp_reset = GP_EMMC_RESET},
+ {.esdhc_base = USDHC2_BASE_ADDR, .bus_width = 1,
+ .gp_reset = USDHC2_PWR_GPIO},
};
int board_mmc_init(bd_t *bis)
@@ -103,12 +120,20 @@ int board_mmc_init(bd_t *bis)
udelay(500);
gpio_direction_output(GP_EMMC_RESET, 1);
break;
+ case 1:
+ usdhc_cfg[1].sdhc_clk = mxc_get_clock(USDHC2_CLK_ROOT);
+ gpio_request(GP_EMMC_RESET, "usdhc2_reset");
+ gpio_direction_output(USDHC2_PWR_GPIO, 0);
+ udelay(500);
+ gpio_direction_output(USDHC2_PWR_GPIO, 1);
+ break;
default:
printf("Warning: you configured more USDHC controllers"
"(%d) than supported by the board\n", i + 1);
return -EINVAL;
}
+ printf("board_mmc_init: %d\n",i);
ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
if (ret)
return ret;
@@ -192,11 +217,25 @@ int board_fit_config_name_match(const char *name)
{
/* Just empty function now - can't decide what to choose */
debug("%s: %s\n", __func__, name);
-
- return 0;
+ return 0;
}
#endif
+static void hexdump(unsigned char *buf, int len)
+{
+ int i;
+
+ for (i = 0; i < len; i++) {
+ if ((i % 16) == 0)
+ printf("%s%08x: ", i ? "\n" : "",
+ (unsigned int)&buf[i]);
+ printf("%02x ", buf[i]);
+ }
+ printf("\n");
+}
+
+int mx8mq_showclocks();
+
void board_init_f(ulong dummy)
{
int ret;
@@ -206,6 +245,7 @@ void board_init_f(ulong dummy)
arch_cpu_init();
+ // without this, no uart output
board_early_init_f();
init_uart_clk(0);
timer_init();
@@ -215,13 +255,14 @@ void board_init_f(ulong dummy)
/* Clear the BSS. */
memset(__bss_start, 0, __bss_end - __bss_start);
- ret = spl_init();
+ //ret = spl_init();
if (ret) {
printf("spl_init() failed: %d\n", ret);
hang();
}
enable_tzc380();
+ // without this, no uart output
imx_iomux_v3_setup_multiple_pads(init_pads, ARRAY_SIZE(init_pads));
/* Adjust pmic voltage to 1.0V for 800M */
@@ -232,5 +273,13 @@ void board_init_f(ulong dummy)
/* DDR initialization */
spl_dram_init();
+ mx8mq_showclocks();
+
+ // FIXME: quick DDR test
+ for (int i=0; i<256; i++) {
+ *((uint8_t*)0x42000000+i) = i;
+ }
+ hexdump(0x42000000, 512);
+
board_init_r(NULL, 0);
}
--
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