diff --git a/board/isee/igep0033/board.c b/board/isee/igep0033/board.c
index 87c6736696c25d5513faa6ab48994849aa6304c2..a24c22b1ad44fe737e222e745036ced8ff8bf3bb 100644
--- a/board/isee/igep0033/board.c
+++ b/board/isee/igep0033/board.c
@@ -96,7 +96,7 @@ void sdram_init(void)
  */
 int board_init(void)
 {
-	gd->bd->bi_boot_params = PHYS_DRAM_1 + 0x100;
+	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
 
 	gpmc_init();
 
diff --git a/board/phytec/pcm051/board.c b/board/phytec/pcm051/board.c
index f3bad76c9a3408f5a88362032695f5cadc949b44..f53c5bbd4b50f4e42781fabb13ac74f62e9902e4 100644
--- a/board/phytec/pcm051/board.c
+++ b/board/phytec/pcm051/board.c
@@ -112,7 +112,7 @@ int board_init(void)
 {
 	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
 
-	gd->bd->bi_boot_params = PHYS_DRAM_1 + 0x100;
+	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
 
 	return 0;
 }
diff --git a/board/ti/am335x/board.c b/board/ti/am335x/board.c
index eac9cc9265ba9396c94ee4079a7b049d7a03c06c..04c37e2db6b3ad177fd43a082c772e33e298ac28 100644
--- a/board/ti/am335x/board.c
+++ b/board/ti/am335x/board.c
@@ -343,7 +343,7 @@ int board_init(void)
 		STNOR_GPMC_CONFIG5, STNOR_GPMC_CONFIG6, STNOR_GPMC_CONFIG7 };
 #endif
 
-	gd->bd->bi_boot_params = PHYS_DRAM_1 + 0x100;
+	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
 
 	gpmc_init();
 
diff --git a/board/ti/ti814x/evm.c b/board/ti/ti814x/evm.c
index 31ddc68e860b3c2c527596d9d9fb502bb3310158..e406326a11eeca4de1208c9df1f0a39e149122c3 100644
--- a/board/ti/ti814x/evm.c
+++ b/board/ti/ti814x/evm.c
@@ -112,7 +112,7 @@ void sdram_init(void)
  */
 int board_init(void)
 {
-	gd->bd->bi_boot_params = PHYS_DRAM_1 + 0x100;
+	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
 	return 0;
 }
 
diff --git a/include/configs/igep0033.h b/include/configs/igep0033.h
index 2ee13671d93a26d5e6272ba66e315eadcfae5296..e08fc14b3ad58f6bdcbfce213d40a9f41cab732c 100644
--- a/include/configs/igep0033.h
+++ b/include/configs/igep0033.h
@@ -136,10 +136,9 @@
 
 /* Physical Memory Map */
 #define CONFIG_NR_DRAM_BANKS		1		/*  1 bank of DRAM */
-#define PHYS_DRAM_1			0x80000000	/* DRAM Bank #1 */
 #define CONFIG_MAX_RAM_BANK_SIZE	(1024 << 20)	/* 1GB */
 
-#define CONFIG_SYS_SDRAM_BASE		PHYS_DRAM_1
+#define CONFIG_SYS_SDRAM_BASE		0x80000000
 #define CONFIG_SYS_INIT_SP_ADDR         (NON_SECURE_SRAM_END - \
 						GENERATED_GBL_DATA_SIZE)
 /* Platform/Board specific defs */
diff --git a/include/configs/pcm051.h b/include/configs/pcm051.h
index a3f8ead784340982b606c1760ff88fdffc32ae00..d4d4d791cf9ec1d94504c8474fb12c4d82ce8503 100644
--- a/include/configs/pcm051.h
+++ b/include/configs/pcm051.h
@@ -123,7 +123,7 @@
  * memtest works on 8 MB in DRAM after skipping 32MB from
  * start addr of ram disk
  */
-#define CONFIG_SYS_MEMTEST_START	(PHYS_DRAM_1 + (64 * 1024 * 1024))
+#define CONFIG_SYS_MEMTEST_START	(CONFIG_SYS_SDRAM_BASE + (64 << 20))
 #define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START \
 					+ (8 * 1024 * 1024))
 
@@ -147,10 +147,9 @@
 
  /* Physical Memory Map */
 #define CONFIG_NR_DRAM_BANKS		1		/*  1 bank of DRAM */
-#define PHYS_DRAM_1			0x80000000	/* DRAM Bank #1 */
 #define CONFIG_MAX_RAM_BANK_SIZE	(1024 << 19)	/* 512MiB */
 
-#define CONFIG_SYS_SDRAM_BASE		PHYS_DRAM_1
+#define CONFIG_SYS_SDRAM_BASE		0x80000000
 #define CONFIG_SYS_INIT_SP_ADDR         (NON_SECURE_SRAM_END - \
 						GENERATED_GBL_DATA_SIZE)
  /* Platform/Board specific defs */
diff --git a/include/configs/ti814x_evm.h b/include/configs/ti814x_evm.h
index 42d113df538bdffafbd87074f14dff91ab1a0f0d..dfc4c756db8c9e2f1647639f49e718785bf2acf5 100644
--- a/include/configs/ti814x_evm.h
+++ b/include/configs/ti814x_evm.h
@@ -117,7 +117,7 @@
 /* Boot Argument Buffer Size */
 #define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
 
-#define CONFIG_SYS_MEMTEST_START	PHYS_DRAM_1
+#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE
 #define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START \
 					+ PHYS_DRAM_1_SIZE - (8 << 12))
 
@@ -137,11 +137,10 @@
  * Physical Memory Map
  */
 #define CONFIG_NR_DRAM_BANKS		1		/* 1 banks of DRAM */
-#define PHYS_DRAM_1			0x80000000	/* DRAM Bank #1 */
 #define PHYS_DRAM_1_SIZE		0x20000000	/* 512MB */
 #define CONFIG_MAX_RAM_BANK_SIZE	(1024 << 20)	/* 1024MB */
 
-#define CONFIG_SYS_SDRAM_BASE		PHYS_DRAM_1
+#define CONFIG_SYS_SDRAM_BASE		0x80000000
 #define CONFIG_SYS_INIT_SP_ADDR		(NON_SECURE_SRAM_END - \
 					 GENERATED_GBL_DATA_SIZE)