diff --git a/board/boundary/nitrogen8m/Kconfig b/board/boundary/nitrogen8m/Kconfig
index f0c9f378674d82f7ebd561ee0f12bb8dd912cd00..5d45e54356bac806560c8b06e10fce6c79d9be98 100644
--- a/board/boundary/nitrogen8m/Kconfig
+++ b/board/boundary/nitrogen8m/Kconfig
@@ -9,6 +9,10 @@ config SYS_VENDOR
config SYS_CONFIG_NAME
default "nitrogen8m"
+config DDR_RANK_BITS
+ int "ddr rank bits"
+ default 1
+
source "board/boundary/common/Kconfig"
endif
diff --git a/board/boundary/nitrogen8m/lpddr4_timing.c b/board/boundary/nitrogen8m/lpddr4_timing.c
index de2ca55437f92dc40704c3715b12d5db6df4d5a9..559b8e1cd4edae4f94cd64a54d25b7f46bde3dda 100644
--- a/board/boundary/nitrogen8m/lpddr4_timing.c
+++ b/board/boundary/nitrogen8m/lpddr4_timing.c
@@ -10,7 +10,6 @@
#include <asm/arch/lpddr4_define.h>
#include <asm/arch/imx8m_ddr.h>
-#define LPDDR4_CS 0x3 /* 2 ranks */
#define DDR_BOOT_P1 /* default DDR boot frequency point */
#define WR_POST_EXT_3200
@@ -20,6 +19,17 @@
#define VAL_INIT4 ((LPDDR4_MR3 << 16) | 0x00000008)
#endif
+#if CONFIG_DDR_RANK_BITS == 0
+#define LPDDR4_CS 0x1 /* 0 rank bits, 1 chip select */
+#if CONFIG_DDR_MB == 2048
+ /* Address map is from MSB 28: r15, r14, r13-r0, b2-b0, c9-c0 */
+#define VAL_DDRC_ADDRMAP0 0x0000001F
+#define VAL_DDRC_ADDRMAP6 0x07070707
+#else
+#error unsupported memory size
+#endif
+#elif CONFIG_DDR_RANK_BITS == 1
+#define LPDDR4_CS 0x3 /* 1 rank bit, 2 chip selects */
#if CONFIG_DDR_MB == 2048
/* Address map is from MSB 28: cs, r14, r13-r0, b2-b0, c9-c0 */
#define VAL_DDRC_ADDRMAP0 0x00000016
@@ -35,6 +45,9 @@
#else
#error unsupported memory size
#endif
+#else
+#error unsupported rank bits
+#endif
static struct dram_cfg_param lpddr4_ddrc_cfg[] = {
/* Start to config, default 3200mbps */
@@ -42,7 +55,7 @@ static struct dram_cfg_param lpddr4_ddrc_cfg[] = {
{ DDRC_DBG1(0), 0x00000001 },
/* selfref_en=1, SDRAM enter self-refresh state */
{ DDRC_PWRCTL(0), 0x00000001 },
- { DDRC_MSTR(0), 0xa3080020 },
+ { DDRC_MSTR(0), 0xa0080020 | (LPDDR4_CS << 24) },
{ DDRC_MSTR2(0), 0x00000000 },
{ DDRC_DERATEEN(0), 0x00000203 },
{ DDRC_DERATEINT(0), 0x0186A000 },
@@ -397,7 +410,7 @@ static struct dram_cfg_param lpddr4_fsp0_cfg[] = {
{ 0x5400f, 0x0 },
{ 0x54010, 0x0 },
{ 0x54011, 0x0 },
- { 0x54012, (LPDDR4_CS << 8) | 0x10 },
+ { 0x54012, 0x10 | (LPDDR4_CS << 8) },
{ 0x54013, 0x0 },
{ 0x54014, 0x0 },
{ 0x54015, 0x0 },
@@ -423,7 +436,7 @@ static struct dram_cfg_param lpddr4_fsp0_cfg[] = {
{ 0x54029, 0x0 },
{ 0x5402a, 0x0 },
{ 0x5402b, 0x1000 },
- { 0x5402c, 0x3 },
+ { 0x5402c, LPDDR4_CS },
{ 0x5402d, 0x0 },
{ 0x5402e, 0x0 },
{ 0x5402f, 0x0 },
@@ -472,7 +485,7 @@ static struct dram_cfg_param lpddr4_fsp0_2d_cfg[] = {
{ 0x5400f, (LPDDR4_2D_SHARE << 8) | 0x00 },
{ 0x54010, LPDDR4_2D_WEIGHT },
{ 0x54011, 0x0 },
- { 0x54012, (LPDDR4_CS << 8) | 0x10 },
+ { 0x54012, 0x10 | (LPDDR4_CS << 8) },
{ 0x54013, 0x0 },
{ 0x54014, 0x0 },
{ 0x54015, 0x0 },
@@ -499,7 +512,7 @@ static struct dram_cfg_param lpddr4_fsp0_2d_cfg[] = {
{ 0x54029, 0x0 },
{ 0x5402a, 0x0 },
{ 0x5402b, 0x1000 },
- { 0x5402c, 0x3 },
+ { 0x5402c, LPDDR4_CS },
{ 0x5402d, 0x0 },
{ 0x5402e, 0x0 },
{ 0x5402f, 0x0 },
@@ -548,7 +561,7 @@ static struct dram_cfg_param lpddr4_fsp1_cfg[] = {
{ 0x5400f, 0x0 },
{ 0x54010, 0x0 },
{ 0x54011, 0x0 },
- { 0x54012, (LPDDR4_CS << 8) | 0x10 },
+ { 0x54012, 0x10 | (LPDDR4_CS << 8) },
{ 0x54013, 0x0 },
{ 0x54014, 0x0 },
{ 0x54015, 0x0 },
@@ -573,7 +586,7 @@ static struct dram_cfg_param lpddr4_fsp1_cfg[] = {
{ 0x54029, 0x0 },
{ 0x5402a, 0x0 },
{ 0x5402b, 0x1000 },
- { 0x5402c, 0x3 },
+ { 0x5402c, LPDDR4_CS },
{ 0x5402d, 0x0 },
{ 0x5402e, 0x0 },
{ 0x5402f, 0x0 },
diff --git a/configs/nitrogen8m_2gr0_defconfig b/configs/nitrogen8m_2gr0_defconfig
new file mode 100644
index 0000000000000000000000000000000000000000..a1fe46005d13afa3c97c88396d2a01d0b473f1ad
--- /dev/null
+++ b/configs/nitrogen8m_2gr0_defconfig
@@ -0,0 +1,105 @@
+CONFIG_ARM=y
+CONFIG_ARCH_IMX8M=y
+CONFIG_SYS_TEXT_BASE=0x40200000
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_TARGET_NITROGEN8M=y
+CONFIG_DDR_RANK_BITS=0
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_SPL=y
+CONFIG_DEBUG_UART_BASE=0x30860000
+CONFIG_DEBUG_UART_CLOCK=25000000
+CONFIG_DEFAULT_DEVICE_TREE="imx8mq-nitrogen8m"
+CONFIG_DEBUG_UART=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_FIT=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh"
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/imx8m/imximage.cfg,DDR_MB=2048,DEFCONFIG=\"nitrogen8m_2gr0\""
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_POWER_SUPPORT=y
+CONFIG_SPL_USB_HOST_SUPPORT=y
+CONFIG_SPL_USB_GADGET_SUPPORT=y
+CONFIG_SPL_USB_SDP_SUPPORT=y
+CONFIG_SPL_WATCHDOG_SUPPORT=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_SYS_ALT_MEMTEST=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_BMP=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_EXT4_WRITE=y
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_ISO_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
+CONFIG_PARTITION_TYPE_GUID=y
+CONFIG_OF_CONTROL=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_IMX8M_LPDDR4=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x40480000
+CONFIG_FASTBOOT_BUF_SIZE=0x20000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=0
+CONFIG_DM_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_SYS_I2C_MXC_I2C4=y
+CONFIG_DM_MMC=y
+CONFIG_FSL_ESDHC=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_NETDEVICES=y
+CONFIG_FEC_MXC=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX8M=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DEBUG_UART_MXC=y
+CONFIG_MXC_UART=y
+CONFIG_DM_THERMAL=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GADGET=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_KEYBOARD=y
+CONFIG_SYS_USB_EVENT_POLL_VIA_CONTROL_EP=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="Boundary"
+CONFIG_USB_GADGET_VENDOR_NUM=0x3016
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0001
+CONFIG_USB_GADGET_SPL_SPD_PRODUCT_NUM=0x1001
+CONFIG_USB_ETHER=y
+CONFIG_USB_ETH_CDC=y
+CONFIG_USBNET_DEVADDR="00:19:b8:00:00:02"
+CONFIG_USBNET_HOST_ADDR="00:19:b8:00:00:01"
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_USB_ETHER_MCS7830=y
+CONFIG_USB_ETHER_SMSC95XX=y
+CONFIG_VIDEO=y
+CONFIG_VIDEO_IMXDCSS=y
+CONFIG_VIDEO_IMX8_HDMI=y