From 654ea1f3184235694306ddc5874baa27ad3018fe Mon Sep 17 00:00:00 2001
From: Dave Liu <daveliu@freescale.com>
Date: Thu, 22 Oct 2009 00:10:23 -0500
Subject: [PATCH] ppc/85xx: Make L2 support more robust
According the user manual, we need loop-check the L2 enable bit set.
Signed-off-by: Dave Liu <daveliu@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
---
cpu/mpc85xx/cpu_init.c | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/cpu/mpc85xx/cpu_init.c b/cpu/mpc85xx/cpu_init.c
index 53369349d13..0041a60df96 100644
--- a/cpu/mpc85xx/cpu_init.c
+++ b/cpu/mpc85xx/cpu_init.c
@@ -360,8 +360,11 @@ int cpu_init_r(void)
/* enable the cache */
mtspr(SPRN_L2CSR0, CONFIG_SYS_INIT_L2CSR0);
- if (CONFIG_SYS_INIT_L2CSR0 & L2CSR0_L2E)
+ if (CONFIG_SYS_INIT_L2CSR0 & L2CSR0_L2E) {
+ while (!(mfspr(SPRN_L2CSR0) & L2CSR0_L2E))
+ ;
printf("%d KB enabled\n", (l2cfg0 & 0x3fff) * 64);
+ }
#else
puts("disabled\n");
#endif
--
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