From 62f739fe465c41a2c5be0a46b3330c12b213dc07 Mon Sep 17 00:00:00 2001
From: York Sun <yorksun@freescale.com>
Date: Fri, 17 Aug 2012 08:22:42 +0000
Subject: [PATCH] powerpc/mpc8xxx DDR: Fall back to raw timing for first
controller only
Only the first DIMM of first controller should fall back to raw timing
parameters if SPD is missing or corrupted.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
---
arch/powerpc/cpu/mpc8xxx/ddr/main.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/main.c b/arch/powerpc/cpu/mpc8xxx/ddr/main.c
index 4fd4f8fc330..b47268c20ea 100644
--- a/arch/powerpc/cpu/mpc8xxx/ddr/main.c
+++ b/arch/powerpc/cpu/mpc8xxx/ddr/main.c
@@ -383,7 +383,7 @@ fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step,
retval = compute_dimm_parameters(spd, pdimm, i);
#ifdef CONFIG_SYS_DDR_RAW_TIMING
- if (retval != 0) {
+ if (!i && !j && retval) {
printf("SPD error on controller %d! "
"Trying fallback to raw timing "
"calculation\n", i);
--
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