diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig
index ee7491761947c5c346b66324cc12fd377c78c64b..b0077cde5c28d77ce2287f457bb54baf7a0dbd36 100644
--- a/arch/arm/mach-imx/mx6/Kconfig
+++ b/arch/arm/mach-imx/mx6/Kconfig
@@ -370,6 +370,10 @@ config TARGET_OPOS6ULDEV
 	bool "Armadeus OPOS6ULDev board"
 	select MX6UL_OPOS6UL
 
+config TARGET_YS
+	bool "ys"
+	select MX6SX
+
 config TARGET_OT1200
 	bool "Bachmann OT1200"
 	select SUPPORT_SPL
@@ -498,6 +502,7 @@ source "board/barco/platinum/Kconfig"
 source "board/barco/titanium/Kconfig"
 source "board/boundary/a/Kconfig"
 source "board/boundary/nitrogen6x/Kconfig"
+source "board/boundary/ys/Kconfig"
 source "board/bticino/mamoj/Kconfig"
 source "board/ccv/xpress/Kconfig"
 source "board/compulab/cm_fx6/Kconfig"
diff --git a/board/boundary/ys/Kconfig b/board/boundary/ys/Kconfig
new file mode 100644
index 0000000000000000000000000000000000000000..66aff1f801349bb21556016d032f3a788155c8f8
--- /dev/null
+++ b/board/boundary/ys/Kconfig
@@ -0,0 +1,20 @@
+if TARGET_YS
+
+config SYS_CPU
+	default "armv7"
+
+config SYS_BOARD
+	default "ys"
+
+config SYS_VENDOR
+	default "boundary"
+
+config SYS_SOC
+	default "mx6"
+
+config SYS_CONFIG_NAME
+	default "ys"
+
+source "board/boundary/common/Kconfig"
+
+endif
diff --git a/board/boundary/ys/MAINTAINERS b/board/boundary/ys/MAINTAINERS
new file mode 100644
index 0000000000000000000000000000000000000000..5980fda7ece2706b6f2630fcef0450d467ec690a
--- /dev/null
+++ b/board/boundary/ys/MAINTAINERS
@@ -0,0 +1,6 @@
+YS BOARD
+M:	Troy Kisky <troy.kisky@boundarydevices.com>
+S:	Maintained
+F:	board/boundary/ys/
+F:	include/configs/ys.h
+F:	configs/ys_defconfig
diff --git a/board/boundary/ys/Makefile b/board/boundary/ys/Makefile
new file mode 100644
index 0000000000000000000000000000000000000000..50d44b89f2ebd6e924466ab88da662b230d06abf
--- /dev/null
+++ b/board/boundary/ys/Makefile
@@ -0,0 +1,6 @@
+# (C) Copyright 2017 Boundary Devices, Inc.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y  := ys.o
diff --git a/board/boundary/ys/ys.c b/board/boundary/ys/ys.c
new file mode 100644
index 0000000000000000000000000000000000000000..37e76a0153a0519495ed1e94eaeb14adaf189f7f
--- /dev/null
+++ b/board/boundary/ys/ys.c
@@ -0,0 +1,351 @@
+/*
+ * Copyright (C) 2017 Boundary Devices, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <asm/arch/clock.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/gpio.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#include <asm/io.h>
+#include <common.h>
+#include <fsl_esdhc.h>
+#include <i2c.h>
+#include <linux/sizes.h>
+#include <malloc.h>
+#include <mmc.h>
+#include <usb.h>
+#include <usb/ehci-ci.h>
+#include "../common/bd_common.h"
+#include "../common/padctrl.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define AUD_PAD_CTRL  (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_LOW | \
+	PAD_CTL_DSE_40ohm | PAD_CTL_HYS | PAD_CTL_SRE_FAST)
+
+#define CSI_PAD_CTL	PAD_CTL_DSE_120ohm
+
+#define I2C_PAD_CTRL    (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
+	PAD_CTL_DSE_40ohm | PAD_CTL_HYS | PAD_CTL_ODE)
+
+#define LCDIF_PAD_CTL	PAD_CTL_DSE_120ohm
+
+#define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED |		\
+	PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
+
+#define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
+	PAD_CTL_DSE_40ohm | PAD_CTL_HYS | PAD_CTL_SRE_FAST)
+
+#define USDHC2_PAD_CTRL (PAD_CTL_PUS_22K_UP  | PAD_CTL_SPEED_LOW | \
+	PAD_CTL_DSE_40ohm | PAD_CTL_HYS | PAD_CTL_SRE_FAST)
+
+#define USDHC2_CLK_PAD_CTRL (PAD_CTL_SPEED_LOW | \
+	PAD_CTL_DSE_40ohm | PAD_CTL_HYS | PAD_CTL_SRE_FAST)
+
+#define USDHC3_PAD_CTRL (PAD_CTL_PUS_22K_UP  | PAD_CTL_SPEED_LOW | \
+	PAD_CTL_DSE_80ohm | PAD_CTL_HYS | PAD_CTL_SRE_FAST | PAD_CTL_LVE)
+
+/* External pullup to 1.8V, input (release), out low(asserted) */
+#define USDHC3_PAD_CTRL_RST (PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
+		PAD_CTL_SRE_SLOW)
+
+#define USDHC_CLK_PAD_CTRL (PAD_CTL_SPEED_LOW | \
+	PAD_CTL_DSE_80ohm | PAD_CTL_HYS | PAD_CTL_SRE_FAST)
+
+static const iomux_v3_cfg_t init_pads[] = {
+	/* ECSPI1 (serial nor eeprom) */
+	IOMUX_PAD_CTRL(KEY_COL1__ECSPI1_MISO, SPI_PAD_CTRL),
+	IOMUX_PAD_CTRL(KEY_ROW0__ECSPI1_MOSI, SPI_PAD_CTRL),
+	IOMUX_PAD_CTRL(KEY_COL0__ECSPI1_SCLK, SPI_PAD_CTRL),
+#define GP_ECSPI1_NOR_CS	IMX_GPIO_NR(2, 16)
+	IOMUX_PAD_CTRL(KEY_ROW1__GPIO2_IO_16, WEAK_PULLUP),
+
+	/* ECSPI2 */
+	IOMUX_PAD_CTRL(SD4_CLK__ECSPI2_MISO, SPI_PAD_CTRL),
+	IOMUX_PAD_CTRL(SD4_CMD__ECSPI2_MOSI, SPI_PAD_CTRL),
+	IOMUX_PAD_CTRL(SD4_DATA1__ECSPI2_SCLK, SPI_PAD_CTRL),
+	IOMUX_PAD_CTRL(SD4_DATA3__ECSPI2_RDY, SPI_PAD_CTRL),
+#define GP_ECSPI2_CS	IMX_GPIO_NR(6, 14)
+	IOMUX_PAD_CTRL(SD4_DATA0__GPIO6_IO_14, WEAK_PULLUP),
+
+	/* ECSPI3 */
+	IOMUX_PAD_CTRL(SD4_DATA6__ECSPI3_MISO, SPI_PAD_CTRL),
+	IOMUX_PAD_CTRL(SD4_DATA5__ECSPI3_MOSI, SPI_PAD_CTRL),
+	IOMUX_PAD_CTRL(SD4_DATA4__ECSPI3_SCLK, SPI_PAD_CTRL),
+#define GP_ECSPI3_CS	IMX_GPIO_NR(6, 21)
+	IOMUX_PAD_CTRL(SD4_DATA7__GPIO6_IO_21, WEAK_PULLUP),
+
+	/* ECSPI5 */
+	IOMUX_PAD_CTRL(QSPI1A_SS1_B__ECSPI5_MISO, SPI_PAD_CTRL),
+	IOMUX_PAD_CTRL(QSPI1A_DQS__ECSPI5_MOSI, SPI_PAD_CTRL),
+	IOMUX_PAD_CTRL(QSPI1B_SS1_B__ECSPI5_SCLK, SPI_PAD_CTRL),
+#define GP_ECSPI5_CS	IMX_GPIO_NR(4, 28)
+	IOMUX_PAD_CTRL(QSPI1B_DQS__GPIO4_IO_28, SPI_PAD_CTRL),
+
+	/* enet phy */
+	IOMUX_PAD_CTRL(ENET1_MDC__ENET1_MDC, PAD_CTRL_ENET_MDC),
+	IOMUX_PAD_CTRL(ENET1_MDIO__ENET1_MDIO, PAD_CTRL_ENET_MDIO),
+
+	/* fec1 */
+	IOMUX_PAD_CTRL(RGMII1_TD0__ENET1_TX_DATA_0, PAD_CTRL_ENET_TX),
+	IOMUX_PAD_CTRL(RGMII1_TD1__ENET1_TX_DATA_1, PAD_CTRL_ENET_TX),
+	IOMUX_PAD_CTRL(RGMII1_TD2__ENET1_TX_DATA_2, PAD_CTRL_ENET_TX),
+	IOMUX_PAD_CTRL(RGMII1_TD3__ENET1_TX_DATA_3, PAD_CTRL_ENET_TX),
+	IOMUX_PAD_CTRL(RGMII1_TXC__ENET1_RGMII_TXC, PAD_CTRL_ENET_TX),
+	IOMUX_PAD_CTRL(RGMII1_TX_CTL__ENET1_TX_EN, PAD_CTRL_ENET_TX),
+	/* AR8035 PHY Reset */
+#define GP_RGMII_PHY_RESET	IMX_GPIO_NR(2, 7)
+	IOMUX_PAD_CTRL(ENET2_CRS__GPIO2_IO_7, WEAK_PULLUP),
+#define GP_RGMII_PHY_INT	IMX_GPIO_NR(2, 4)
+	IOMUX_PAD_CTRL(ENET1_RX_CLK__GPIO2_IO_4, WEAK_PULLUP),
+	IOMUX_PAD_CTRL(ENET1_TX_CLK__GPIO2_IO_5, WEAK_PULLUP),
+
+	/* fec2 */
+	IOMUX_PAD_CTRL(RGMII2_TD0__ENET2_TX_DATA_0, PAD_CTRL_ENET_TX),
+	IOMUX_PAD_CTRL(RGMII2_TD1__ENET2_TX_DATA_1, PAD_CTRL_ENET_TX),
+	IOMUX_PAD_CTRL(RGMII2_TD2__ENET2_TX_DATA_2, PAD_CTRL_ENET_TX),
+	IOMUX_PAD_CTRL(RGMII2_TD3__ENET2_TX_DATA_3, PAD_CTRL_ENET_TX),
+	IOMUX_PAD_CTRL(RGMII2_TXC__ENET2_RGMII_TXC, PAD_CTRL_ENET_TX),
+	IOMUX_PAD_CTRL(RGMII2_TX_CTL__ENET2_TX_EN, PAD_CTRL_ENET_TX),
+	/* AR8035 PHY Reset */
+#define GP_RGMII2_PHY_RESET	IMX_GPIO_NR(2, 6)
+	IOMUX_PAD_CTRL(ENET2_COL__GPIO2_IO_6, WEAK_PULLUP),
+#define GP_RGMII2_PHY_INT	IMX_GPIO_NR(2, 8)
+	IOMUX_PAD_CTRL(ENET2_RX_CLK__GPIO2_IO_8, WEAK_PULLUP),
+	IOMUX_PAD_CTRL(ENET2_TX_CLK__GPIO2_IO_9, WEAK_PULLUP),
+
+	/* hogs - GPIO */
+#define GP_TERM_ON_OFF		IMX_GPIO_NR(1, 13)
+	IOMUX_PAD_CTRL(GPIO1_IO13__GPIO1_IO_13, WEAK_PULLDN_OUTPUT),
+#define GP_485_TERM_CTRL	IMX_GPIO_NR(3, 1)
+	IOMUX_PAD_CTRL(LCD1_DATA00__GPIO3_IO_1, WEAK_PULLDN_OUTPUT),
+#define GP_RESET_DSP_N		IMX_GPIO_NR(3, 3)
+	IOMUX_PAD_CTRL(LCD1_DATA02__GPIO3_IO_3, WEAK_PULLUP_OUTPUT),
+#define GP_485_DIR		IMX_GPIO_NR(3, 4)
+	IOMUX_PAD_CTRL(LCD1_DATA03__GPIO3_IO_4, WEAK_PULLDN_OUTPUT),
+#define GP_PWR_SYNC		IMX_GPIO_NR(3, 6)
+	IOMUX_PAD_CTRL(LCD1_DATA05__GPIO3_IO_6, WEAK_PULLDN_OUTPUT),
+#define GP_SERVICE_LED		IMX_GPIO_NR(3, 7)
+	IOMUX_PAD_CTRL(LCD1_DATA06__GPIO3_IO_7, WEAK_PULLDN_OUTPUT),
+#define GP_NETWORK_LED		IMX_GPIO_NR(3, 9)
+	IOMUX_PAD_CTRL(LCD1_DATA08__GPIO3_IO_9, WEAK_PULLDN_OUTPUT),
+#define GP_POWER_OK_VDSP	IMX_GPIO_NR(3, 10)
+	IOMUX_PAD_CTRL(LCD1_DATA09__GPIO3_IO_10, WEAK_PULLDN_OUTPUT),
+#define GP_SYSTEM_LED		IMX_GPIO_NR(3, 11)
+	IOMUX_PAD_CTRL(LCD1_DATA10__GPIO3_IO_11, WEAK_PULLDN_OUTPUT),
+#define GP_CUST_START		IMX_GPIO_NR(3, 12)
+	IOMUX_PAD_CTRL(LCD1_DATA11__GPIO3_IO_12, WEAK_PULLDN_OUTPUT),
+
+	/* hogs - Test points */
+#define GP_TP51			IMX_GPIO_NR(4, 24)
+	IOMUX_PAD_CTRL(QSPI1B_DATA0__GPIO4_IO_24, WEAK_PULLUP),
+#define GP_TP83			IMX_GPIO_NR(4, 29)
+	IOMUX_PAD_CTRL(QSPI1B_SCLK__GPIO4_IO_29, WEAK_PULLUP),
+#define GP_TP92			IMX_GPIO_NR(4, 22)
+	IOMUX_PAD_CTRL(QSPI1A_SS0_B__GPIO4_IO_22, WEAK_PULLUP),
+
+	/* i2c1 - rtc RV4162 irq */
+#define GPIRQ_RTC_RV4162	IMX_GPIO_NR(4, 30)
+	IOMUX_PAD_CTRL(QSPI1B_SS0_B__GPIO4_IO_30, WEAK_PULLUP),
+
+	/* PCIe */
+#define GP_PCIE_RESET	IMX_GPIO_NR(4, 7)
+	IOMUX_PAD_CTRL(NAND_DATA03__GPIO4_IO_7, WEAK_PULLUP),
+#define GP_PCIE_DISABLE	IMX_GPIO_NR(4, 8)
+	IOMUX_PAD_CTRL(NAND_DATA04__GPIO4_IO_8, WEAK_PULLUP),
+#define GP_PCIE_WAKE	IMX_GPIO_NR(4, 9)
+	IOMUX_PAD_CTRL(NAND_DATA05__GPIO4_IO_9, WEAK_PULLUP),
+
+	/* uart1 */
+	IOMUX_PAD_CTRL(GPIO1_IO04__UART1_TX, UART_PAD_CTRL),
+	IOMUX_PAD_CTRL(GPIO1_IO05__UART1_RX, UART_PAD_CTRL),
+
+	/* uart2 */
+	IOMUX_PAD_CTRL(GPIO1_IO06__UART2_TX, UART_PAD_CTRL),
+	IOMUX_PAD_CTRL(GPIO1_IO07__UART2_RX, UART_PAD_CTRL),
+
+	/* uart3 */
+	IOMUX_PAD_CTRL(NAND_DATA07__UART3_TX, UART_PAD_CTRL),
+	IOMUX_PAD_CTRL(NAND_DATA06__UART3_RX, UART_PAD_CTRL),
+
+	/* uart5 */
+	IOMUX_PAD_CTRL(KEY_COL3__UART5_TX, UART_PAD_CTRL),
+	IOMUX_PAD_CTRL(KEY_ROW3__UART5_RX, UART_PAD_CTRL),
+#define GP_RS485_RXEN		IMX_GPIO_NR(4, 22)
+	IOMUX_PAD_CTRL(GPIO1_IO12__GPIO1_IO_12, WEAK_PULLUP),
+
+	/* USB OTG1 */
+	IOMUX_PAD_CTRL(GPIO1_IO08__USB_OTG1_OC, WEAK_PULLUP),
+	IOMUX_PAD_CTRL(GPIO1_IO10__ANATOP_OTG1_ID, WEAK_PULLUP),
+#define GP_USB_OTG1_PWR		IMX_GPIO_NR(1, 9)
+	IOMUX_PAD_CTRL(GPIO1_IO09__GPIO1_IO_9, WEAK_PULLDN_OUTPUT),
+
+	/* USB OTG2 */
+#define GP_USB_HUB_RESET	IMX_GPIO_NR(4, 26)
+	IOMUX_PAD_CTRL(QSPI1B_DATA2__GPIO4_IO_26, OUTPUT_40OHM),
+#define GP_USB_HOST_PWR_EN	IMX_GPIO_NR(1, 11)
+	IOMUX_PAD_CTRL(GPIO1_IO11__GPIO1_IO_11, OUTPUT_40OHM),
+
+	/* usdhc2 - micro SD */
+	IOMUX_PAD_CTRL(SD2_CLK__USDHC2_CLK, USDHC2_CLK_PAD_CTRL),
+	IOMUX_PAD_CTRL(SD2_CMD__USDHC2_CMD, USDHC2_PAD_CTRL),
+	IOMUX_PAD_CTRL(SD2_DATA0__USDHC2_DATA0, USDHC2_PAD_CTRL),
+	IOMUX_PAD_CTRL(SD2_DATA1__USDHC2_DATA1, USDHC2_PAD_CTRL),
+	IOMUX_PAD_CTRL(SD2_DATA2__USDHC2_DATA2, USDHC2_PAD_CTRL),
+	IOMUX_PAD_CTRL(SD2_DATA3__USDHC2_DATA3, USDHC2_PAD_CTRL),
+#define GP_USDHC2_CD	IMX_GPIO_NR(2, 12)
+	IOMUX_PAD_CTRL(KEY_COL2__GPIO2_IO_12, WEAK_PULLUP),
+
+	/* usdhc3 - eMMC */
+	IOMUX_PAD_CTRL(SD3_CLK__USDHC3_CLK, USDHC3_PAD_CTRL),
+	IOMUX_PAD_CTRL(SD3_CMD__USDHC3_CMD, USDHC3_PAD_CTRL),
+	IOMUX_PAD_CTRL(SD3_DATA0__USDHC3_DATA0, USDHC3_PAD_CTRL),
+	IOMUX_PAD_CTRL(SD3_DATA1__USDHC3_DATA1, USDHC3_PAD_CTRL),
+	IOMUX_PAD_CTRL(SD3_DATA2__USDHC3_DATA2, USDHC3_PAD_CTRL),
+	IOMUX_PAD_CTRL(SD3_DATA3__USDHC3_DATA3, USDHC3_PAD_CTRL),
+	IOMUX_PAD_CTRL(SD3_DATA4__USDHC3_DATA4, USDHC3_PAD_CTRL),
+	IOMUX_PAD_CTRL(SD3_DATA5__USDHC3_DATA5, USDHC3_PAD_CTRL),
+	IOMUX_PAD_CTRL(SD3_DATA6__USDHC3_DATA6, USDHC3_PAD_CTRL),
+	IOMUX_PAD_CTRL(SD3_DATA7__USDHC3_DATA7, USDHC3_PAD_CTRL),
+	/* External pullup to 1.8V, input (release), out low(asserted) */
+#define GP_EMMC_RESET	IMX_GPIO_NR(2, 17)
+	IOMUX_PAD_CTRL(KEY_ROW2__GPIO2_IO_17, USDHC3_PAD_CTRL_RST),
+};
+
+static const struct i2c_pads_info i2c_pads[] = {
+	I2C_PADS_INFO_ENTRY(I2C1, GPIO1_IO00, 1, 0, GPIO1_IO01, 1, 1, I2C_PAD_CTRL),
+	I2C_PADS_INFO_ENTRY(I2C2, GPIO1_IO02, 1, 2, GPIO1_IO03, 1, 3, I2C_PAD_CTRL),
+	I2C_PADS_INFO_ENTRY(I2C3, KEY_COL4, 2, 14, KEY_ROW4, 2, 19, I2C_PAD_CTRL),
+};
+#define I2C_BUS_CNT	3
+
+#ifdef CONFIG_MXC_SPI
+int board_spi_cs_gpio(unsigned bus, unsigned cs)
+{
+	return (bus == 0 && cs == 0) ? GP_ECSPI1_NOR_CS : (cs >> 8) ? (cs >> 8) : -1;
+}
+#endif
+
+#ifdef CONFIG_USB_EHCI_MX6
+#define USB_OTHERREGS_OFFSET	0x800
+#define UCTRL_PWR_POL		(1 << 9)
+
+int board_usb_phy_mode(int port)
+{
+	if (port == 1)
+		return USB_INIT_HOST;
+	else
+		return usb_phy_mode(port);
+}
+
+int board_ehci_hcd_init(int port)
+{
+	u32 *usbnc_usb_ctrl;
+
+	if (port > 1)
+		return -EINVAL;
+	usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET +
+			port * 4);
+	setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL);
+
+	/* Reset USB hub */
+	gpio_direction_output(GP_USB_HUB_RESET, 0);
+	mdelay(2);
+	gpio_set_value(GP_USB_HUB_RESET, 1);
+	return 0;
+}
+
+int board_ehci_power(int port, int on)
+{
+	if (port)
+		gpio_set_value(GP_USB_HOST_PWR_EN, on);
+	else
+		gpio_set_value(GP_USB_OTG1_PWR, on);
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_FSL_ESDHC
+struct fsl_esdhc_cfg board_usdhc_cfg[] = {
+	{.esdhc_base = USDHC2_BASE_ADDR, .bus_width = 4,
+			.gp_cd = GP_USDHC2_CD},
+	{.esdhc_base = USDHC3_BASE_ADDR, .bus_width = 8,
+			.vs18_enable = 1},
+};
+#endif
+
+static const unsigned short gpios_out_low[] = {
+	GP_485_DIR,
+	GP_485_TERM_CTRL,
+	GP_CUST_START,
+	GP_NETWORK_LED,
+	GP_PCIE_RESET,
+	GP_POWER_OK_VDSP,
+	GP_PWR_SYNC,
+	GP_RGMII_PHY_RESET,
+	GP_RGMII2_PHY_RESET,
+	GP_SERVICE_LED,
+	GP_SYSTEM_LED,
+	GP_TERM_ON_OFF,
+	GP_USB_HUB_RESET,
+	GP_USB_OTG1_PWR,
+	GP_USB_HOST_PWR_EN,
+};
+
+static const unsigned short gpios_out_high[] = {
+	GP_ECSPI1_NOR_CS,
+	GP_ECSPI2_CS,
+	GP_ECSPI3_CS,
+	GP_ECSPI5_CS,
+	GP_RESET_DSP_N,
+	GP_RS485_RXEN,
+};
+
+static const unsigned short gpios_in[] = {
+	GP_RGMII_PHY_INT,
+	GP_RGMII2_PHY_INT,
+	GP_USDHC2_CD,
+	GP_TP51,
+	GP_TP83,
+	GP_TP92,
+	GPIRQ_RTC_RV4162,
+	GP_PCIE_WAKE,
+	GP_PCIE_DISABLE,
+	GP_EMMC_RESET,
+};
+
+int board_early_init_f(void)
+{
+	set_gpios_in(gpios_in, ARRAY_SIZE(gpios_in));
+	set_gpios(gpios_out_high, ARRAY_SIZE(gpios_out_high), 1);
+	set_gpios(gpios_out_low, ARRAY_SIZE(gpios_out_low), 0);
+	SETUP_IOMUX_PADS(init_pads);
+	return 0;
+}
+
+int board_init(void)
+{
+	common_board_init(i2c_pads, I2C_BUS_CNT, 0, NULL, 0, 0);
+	return 0;
+}
+
+const struct button_key board_buttons[] = {
+	{"tp51",	GP_TP51,	't', 1},
+	{NULL, 0, 0, 0},
+};
+
+#ifdef CONFIG_CMD_BMODE
+const struct boot_mode board_boot_modes[] = {
+	{"mmc0", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
+	{"mmc1", MAKE_CFGVAL(0x60, 0x58, 0x00, 0x00)},
+	{NULL, 0},
+};
+#endif
diff --git a/board/boundary/ys/ys_1g.cfg b/board/boundary/ys/ys_1g.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..0a5b3614292bb91da4bad54ad8a7a2f226cdf1b2
--- /dev/null
+++ b/board/boundary/ys/ys_1g.cfg
@@ -0,0 +1,138 @@
+/*
+ * Copyright (C) 2017 Boundary Devices, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#define __ASSEMBLY__
+#include <config.h>
+#include "asm/arch/mx6-ddr.h"
+#include "asm/arch/crm_regs.h"
+
+
+/* image version */
+
+IMAGE_VERSION 2
+
+/*
+ * Boot Device : one of
+ * spi/sd/nand/onenand, qspi/nor
+ */
+
+BOOT_FROM	spi
+
+#ifdef CONFIG_SECURE_BOOT
+CSF CONFIG_CSF_SIZE
+#endif
+
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type           Address        Value
+ *
+ * where:
+ *	Addr-type register length (1,2 or 4 bytes)
+ *	Address	  absolute address of the register
+ *	value	  value to be stored in the register
+ */
+
+/* enable cko1 as 32k for slow clock */
+DATA 4, CCM_CCOSR, 0x0000008e
+
+/* Enable all clocks */
+DATA 4, CCM_CCGR0, 0xffffffff
+DATA 4, CCM_CCGR1, 0xffffffff
+DATA 4, CCM_CCGR2, 0xffffffff
+DATA 4, CCM_CCGR3, 0xffffffff
+DATA 4, CCM_CCGR4, 0xffffffff
+DATA 4, CCM_CCGR5, 0xffffffff
+DATA 4, CCM_CCGR6, 0xffffffff
+DATA 4, CCM_CCGR7, 0xffffffff
+
+/* IOMUX - DDR IO Type */
+DATA 4, MX6_IOM_GRP_DDR_TYPE, 0x000c0000
+DATA 4, MX6_IOM_GRP_DDRPKE, 0x00000000
+
+/* Clock */
+DATA 4, MX6_IOM_DRAM_SDCLK_0, 0x00000030
+
+/* Address */
+DATA 4, MX6_IOM_DRAM_CAS, 0x00000020
+DATA 4, MX6_IOM_DRAM_RAS, 0x00000020
+DATA 4, MX6_IOM_GRP_ADDDS, 0x00000020
+
+/* Control */
+DATA 4, MX6_IOM_DRAM_RESET, 0x00000020
+
+DATA 4, MX6_IOM_DRAM_SDBA2, 0x00000000
+DATA 4, MX6_IOM_DRAM_SDODT0, 0x00000020
+DATA 4, MX6_IOM_DRAM_SDODT1, 0x00000020
+DATA 4, MX6_IOM_GRP_CTLDS, 0x00000020
+
+/* Data Strobe */
+DATA 4, MX6_IOM_DDRMODE_CTL, 0x00020000
+DATA 4, MX6_IOM_DRAM_SDQS0, 0x00000028
+DATA 4, MX6_IOM_DRAM_SDQS1, 0x00000028
+DATA 4, MX6_IOM_DRAM_SDQS2, 0x00000028
+DATA 4, MX6_IOM_DRAM_SDQS3, 0x00000028
+
+/* Data */
+DATA 4, MX6_IOM_GRP_DDRMODE, 0x00020000
+DATA 4, MX6_IOM_GRP_B0DS, 0x00000028
+DATA 4, MX6_IOM_GRP_B1DS, 0x00000028
+DATA 4, MX6_IOM_GRP_B2DS, 0x00000028
+DATA 4, MX6_IOM_GRP_B3DS, 0x00000028
+DATA 4, MX6_IOM_DRAM_DQM0, 0x00000028
+DATA 4, MX6_IOM_DRAM_DQM1, 0x00000028
+DATA 4, MX6_IOM_DRAM_DQM2, 0x00000028
+DATA 4, MX6_IOM_DRAM_DQM3, 0x00000028
+
+/* Calibrations - ZQ */
+DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xa1390003
+
+/* Calibration settings */
+DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x41380128
+DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x0124011C
+DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x3E3E4246
+DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x34363838
+DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x001D001E
+DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x001A0013
+
+/* Read data bit delay */
+DATA 4, MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333
+DATA 4, MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333
+DATA 4, MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333
+DATA 4, MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333
+
+/* Complete calibration by forced measurement */
+DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800
+
+/* MMDC init - DDR3, 64-bit mode, only MMDC0 is initiated */
+DATA 4, MX6_MMDC_P0_MDPDC, 0x0002002d
+DATA 4, MX6_MMDC_P0_MDCFG0, 0x676b52f3
+DATA 4, MX6_MMDC_P0_MDCFG1, 0xb66d8b63
+DATA 4, MX6_MMDC_P0_MDCFG2, 0x01ff00db
+DATA 4, MX6_MMDC_P0_MDMISC, 0x00011740
+DATA 4, MX6_MMDC_P0_MDSCR, 0x00008000
+DATA 4, MX6_MMDC_P0_MDRWD, 0x000026d2
+DATA 4, MX6_MMDC_P0_MDOR, 0x006b1023
+DATA 4, MX6_MMDC_P0_MDOTC, 0x00333030
+
+DATA 4, MX6_MMDC_P0_MDPDC, 0x0002556d
+
+DATA 4, MX6_MMDC_P0_MDASP, 0x0000005f
+DATA 4, MX6_MMDC_P0_MDCTL, 0x84190000
+
+/* Initialize MT41K256M16HA-125 */
+DATA 4, MX6_MMDC_P0_MDSCR, 0x04008032	/* MR2 */
+DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033	/* MR3 */
+DATA 4, MX6_MMDC_P0_MDSCR, 0x00048031	/* MR1 */
+DATA 4, MX6_MMDC_P0_MDSCR, 0x05208030	/* MR0 */
+/* DDR device ZQ calibration */
+DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040
+
+/* Final DDR setup, before operation start */
+DATA 4, MX6_MMDC_P0_MDREF, 0x00000800
+DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00011117
+DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000
diff --git a/board/boundary/ys/ys_512m.cfg b/board/boundary/ys/ys_512m.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..cc1df1107c00b7e4a1c56fdd423ffcda32621b7d
--- /dev/null
+++ b/board/boundary/ys/ys_512m.cfg
@@ -0,0 +1,211 @@
+/*
+ * Copyright (C) 2017 Boundary Devices, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+/* MT41K128M16JT-125 IT:K */
+
+#define __ASSEMBLY__
+#include <config.h>
+#include "asm/arch/mx6-ddr.h"
+#include "asm/arch/crm_regs.h"
+
+
+/* image version */
+
+IMAGE_VERSION 2
+
+/*
+ * Boot Device : one of
+ * spi/sd/nand/onenand, qspi/nor
+ */
+
+BOOT_FROM	spi
+
+#ifdef CONFIG_SECURE_BOOT
+CSF CONFIG_CSF_SIZE
+#endif
+
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type           Address        Value
+ *
+ * where:
+ *	Addr-type register length (1,2 or 4 bytes)
+ *	Address	  absolute address of the register
+ *	value	  value to be stored in the register
+ */
+
+/* enable cko1 as 32k for slow clock */
+DATA 4, CCM_CCOSR, 0x0000008e
+
+/* Enable all clocks */
+DATA 4, CCM_CCGR0, 0xffffffff
+DATA 4, CCM_CCGR1, 0xffffffff
+DATA 4, CCM_CCGR2, 0xffffffff
+DATA 4, CCM_CCGR3, 0xffffffff
+DATA 4, CCM_CCGR4, 0xffffffff
+DATA 4, CCM_CCGR5, 0xffffffff
+DATA 4, CCM_CCGR6, 0xffffffff
+DATA 4, CCM_CCGR7, 0xffffffff
+
+/* IOMUX - DDR IO Type */
+DATA 4, MX6_IOM_GRP_DDR_TYPE, 0x000c0000
+DATA 4, MX6_IOM_GRP_DDRPKE, 0x00000000
+
+/* Clock */
+DATA 4, MX6_IOM_DRAM_SDCLK_0, 0x00000030
+
+/* Address */
+DATA 4, MX6_IOM_DRAM_CAS, 0x00000020
+DATA 4, MX6_IOM_DRAM_RAS, 0x00000020
+DATA 4, MX6_IOM_GRP_ADDDS, 0x00000020
+
+/* Control */
+DATA 4, MX6_IOM_DRAM_RESET, 0x00000020
+
+DATA 4, MX6_IOM_DRAM_SDBA2, 0x00000000
+DATA 4, MX6_IOM_DRAM_SDODT0, 0x00000020
+DATA 4, MX6_IOM_DRAM_SDODT1, 0x00000020
+DATA 4, MX6_IOM_GRP_CTLDS, 0x00000020
+
+/* Data Strobe */
+DATA 4, MX6_IOM_DDRMODE_CTL, 0x00020000
+DATA 4, MX6_IOM_DRAM_SDQS0, 0x00000028
+DATA 4, MX6_IOM_DRAM_SDQS1, 0x00000028
+DATA 4, MX6_IOM_DRAM_SDQS2, 0x00000028
+DATA 4, MX6_IOM_DRAM_SDQS3, 0x00000028
+
+/* Data */
+DATA 4, MX6_IOM_GRP_DDRMODE, 0x00020000
+DATA 4, MX6_IOM_GRP_B0DS, 0x00000028
+DATA 4, MX6_IOM_GRP_B1DS, 0x00000028
+DATA 4, MX6_IOM_GRP_B2DS, 0x00000028
+DATA 4, MX6_IOM_GRP_B3DS, 0x00000028
+DATA 4, MX6_IOM_DRAM_DQM0, 0x00000028
+DATA 4, MX6_IOM_DRAM_DQM1, 0x00000028
+DATA 4, MX6_IOM_DRAM_DQM2, 0x00000028
+DATA 4, MX6_IOM_DRAM_DQM3, 0x00000028
+
+/* Calibrations - ZQ */
+DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xa1390003
+
+/*
+ * Calibration settings - 4 board sample
+ * 00:19:b8:03:11:24
+ * 00:19:b8:03:17:2a
+ * 00:19:b8:03:17:2c
+ * 00:19:b8:03:17:2e
+ */
+DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x41400133
+DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x01310126
+DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x42434547
+DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x38383b36
+DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x001c0019
+DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x0016000f
+
+/* Read data bit delay */
+DATA 4, MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333
+DATA 4, MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333
+DATA 4, MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333
+DATA 4, MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333
+
+/* Complete calibration by forced measurement */
+DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800
+
+/*
+ * Initialize MT41K128M16HA-125
+ * 14 row + 3 bank + 10 col + 0 rank + 2 width = 29 = 512 MB
+ * tRCD 13125 ps
+ * tRP 13125 ps
+ * tCL 13125 ps
+ * 396M DDR clock = .396G = 2525.2ps/clocks
+ * 13125ps / 2525.2ps/clocks = 5.198 clocks
+ */
+
+/* MMDC init - DDR3, 64-bit mode, only MMDC0 is initiated */
+DATA 4, MX6_MMDC_P0_MDPDC, 0x0002002d
+
+/*
+ * tRFC:0x3f: 64(0x40) clocks		(160000/2525.2)
+ * tXS:0x43: 68(0x44) clocks		(170000/2525.2)
+ * tXP:b'010': 3 clocks			(7500/2525.2)
+ * tXPDLL:b'1001': 10(0xa) clocks	(24000/2525.2)
+ * tFAW:b'01010': 11(0x0b) clocks	(27000/2525.2)
+ * tCL:b'0011': 6 clocks		(13125/2525.2)
+ */
+DATA 4, MX6_MMDC_P0_MDCFG0, 0x3f4352a3
+/*
+ * tRCD:b'101': 6 clocks		(13125/2525.2)
+ * tRP:b'101': 6 clocks			(13125/2525.2)
+ * tRC:b'10100': 21(0x15) clocks	(50625/2525.2)
+ * tRAS:b'01110': 15(0x0f) clocks	(37500/2525.2)
+ * tRPA:b'1': 7 clocks			(tRP[+1]) 6
+ * b'000'
+ * tWR:b'101': 6 clocks			(15000/2525.2)
+ * tMRD:b'1011': 12(0xc) clocks		(min 4 clocks)4
+ * b'00'
+ * tCWL:b'011': 5 clocks		(tCL-1)
+ */
+DATA 4, MX6_MMDC_P0_MDCFG1, 0xb68e8b63
+/*
+ * b'0000000'
+ * tDLLK:0x1ff(9 bits), 512(0x200) clocks (Jedec for DDR3)
+ * b'0000000'
+ * tRTP:b'011': 4 clocks		(7500/2525.2), min 4
+ * tWTR:same bank b'011': 4 clocks	(7500/2525.2), min 4
+ * tRRD:b'011': 4 clocks		(5000/2525.2), min 4
+ */
+DATA 4, MX6_MMDC_P0_MDCFG2, 0x01ff00db
+DATA 4, MX6_MMDC_P0_MDMISC, 0x00011740
+DATA 4, MX6_MMDC_P0_MDSCR, 0x00008000
+/*
+ * RTW_SAME: 2 cycles,
+ * WTR_DIFF: 3 cycles,
+ * WTW_DIFF: 3 cycles,
+ * RTW_DIFF: 2 cycles,
+ * RTR_DIFF: 2 cycles
+ */
+DATA 4, MX6_MMDC_P0_MDRWD, 0x000026d2
+/*
+ * tXPR:0x43: 68(0x44) cycles,	(170000/2525.2), min 5
+ * SDE_to_RST:0x10: 14 cycles, (Jedec)
+ * RST_to_CKE:0x23: 33 cycles	(Jedec)
+ */
+DATA 4, MX6_MMDC_P0_MDOR, 0x00431023
+DATA 4, MX6_MMDC_P0_MDOTC, 0x00333030
+
+DATA 4, MX6_MMDC_P0_MDPDC, 0x0002556d
+
+/* end of CS0 US 0xa0000000-1  */
+DATA 4, MX6_MMDC_P0_MDASP, 0x0000004f
+/* row:14 bits */
+DATA 4, MX6_MMDC_P0_MDCTL, 0x83190000
+
+DATA 4, MX6_MMDC_P0_MDSCR, 0x04008032	/* MR2 */
+DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033	/* MR3 */
+DATA 4, MX6_MMDC_P0_MDSCR, 0x00048031	/* MR1 */
+/*
+ * b'1' - dll on
+ * b'010' - tWR 6 clocks
+ * b'1' - dll reset
+ * b'0'
+ * b'01000' - CAS 6
+ * b'00' Fixed BC4
+ */
+DATA 4, MX6_MMDC_P0_MDSCR, 0x15208030	/* MR0 */
+
+/* DDR device ZQ calibration */
+DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040
+
+/* Final DDR setup, before operation start */
+/*
+ * Need 8192 cycles in 64ms, or 128K/sec, 4/ sec/32k
+ * b'01' - 32 Khz
+ * b'011' - 4 refreshes
+ */
+DATA 4, MX6_MMDC_P0_MDREF, 0x00005800
+DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00022227
+DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000
diff --git a/configs/ys_1g_defconfig b/configs/ys_1g_defconfig
new file mode 100644
index 0000000000000000000000000000000000000000..4370b8f94723dd6825d3c06f163fc0a1d32feb63
--- /dev/null
+++ b/configs/ys_1g_defconfig
@@ -0,0 +1,71 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_SYS_TEXT_BASE=0x87800000
+CONFIG_TARGET_YS=y
+CONFIG_IMX_BOOTAUX=y
+CONFIG_ENV_VARS_UBOOT_CONFIG=y
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/ys/ys_1g.cfg,MX6SX,DEFCONFIG=\"ys_1g\""
+CONFIG_BOOTDELAY=3
+CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
+CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_SYS_ALT_MEMTEST=y
+CONFIG_CMD_DFU=y
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+# CONFIG_RANDOM_UUID is not set
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PART=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_PARTITION_TYPE_GUID=y
+# CONFIG_ENV_IS_IN_MMC is not set
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_SIZE=0x26000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=1
+CONFIG_FSL_ESDHC=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_SST=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_NETDEVICES=y
+CONFIG_FEC_MXC=y
+CONFIG_SPI=y
+CONFIG_MXC_SPI=y
+CONFIG_USB=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_KEYBOARD=y
+CONFIG_SYS_USB_EVENT_POLL_VIA_CONTROL_EP=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="Boundary"
+CONFIG_USB_GADGET_VENDOR_NUM=0x0525
+CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
+CONFIG_CI_UDC=y
+CONFIG_USB_ETHER=y
+CONFIG_USB_ETH_CDC=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_USB_ETHER_MCS7830=y
+CONFIG_USB_ETHER_SMSC95XX=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/ys_512m_defconfig b/configs/ys_512m_defconfig
new file mode 100644
index 0000000000000000000000000000000000000000..48a1d5050415286b2a68206dc5dbb99a282d03ac
--- /dev/null
+++ b/configs/ys_512m_defconfig
@@ -0,0 +1,71 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_SYS_TEXT_BASE=0x87800000
+CONFIG_TARGET_YS=y
+CONFIG_IMX_BOOTAUX=y
+CONFIG_ENV_VARS_UBOOT_CONFIG=y
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/ys/ys_512m.cfg,MX6SX,DEFCONFIG=\"ys_512m\""
+CONFIG_BOOTDELAY=3
+CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
+CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_SYS_ALT_MEMTEST=y
+CONFIG_CMD_DFU=y
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+# CONFIG_RANDOM_UUID is not set
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PART=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_PARTITION_TYPE_GUID=y
+# CONFIG_ENV_IS_IN_MMC is not set
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_SIZE=0x26000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=1
+CONFIG_FSL_ESDHC=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_SST=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_NETDEVICES=y
+CONFIG_FEC_MXC=y
+CONFIG_SPI=y
+CONFIG_MXC_SPI=y
+CONFIG_USB=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_KEYBOARD=y
+CONFIG_SYS_USB_EVENT_POLL_VIA_CONTROL_EP=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="Boundary"
+CONFIG_USB_GADGET_VENDOR_NUM=0x0525
+CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
+CONFIG_CI_UDC=y
+CONFIG_USB_ETHER=y
+CONFIG_USB_ETH_CDC=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_USB_ETHER_MCS7830=y
+CONFIG_USB_ETHER_SMSC95XX=y
+CONFIG_OF_LIBFDT=y
diff --git a/include/configs/ys.h b/include/configs/ys.h
new file mode 100644
index 0000000000000000000000000000000000000000..1251e60fe1fced4949f1e1e3819461c55860207a
--- /dev/null
+++ b/include/configs/ys.h
@@ -0,0 +1,64 @@
+/*
+ * Copyright (C) 2017 Boundary Devices, Inc.
+ *
+ * Configuration settings for the Boundary Devices YS
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include "mx6_common.h"
+
+#define CONFIG_MACH_TYPE	3769
+
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+
+/* M4 specific */
+#define SYS_AUXCORE_BOOTDATA_DDR		0x9ff00000
+#define SYS_AUXCORE_BOOTDATA_OCRAM	0x00910000
+#define SYS_AUXCORE_BOOTDATA_TCM		0x007F8000
+#define EXTRA_ENV_M4 \
+	"m4image=m4_fw.bin\0" \
+	"m4offset=0x1e0000\0" \
+	"m4size=0x8000\0" \
+	"loadm4image=load ${dtype} ${disk}:1 ${loadaddr} ${m4image}\0" \
+	"m4update=for dtype in ${bootdevs}; do " \
+		"for disk in 0 1 ; do ${dtype} dev ${disk} ;" \
+			"if run loadm4image; then " \
+				"sf probe; " \
+				"sf erase ${m4offset} ${m4size}; " \
+				"sf write ${loadaddr} ${m4offset} ${filesize}; " \
+				"exit; " \
+			"fi; " \
+		"done; " \
+		"done\0" \
+	"m4loadaddr="__stringify(CONFIG_SYS_AUXCORE_BOOTDATA_TCM)"\0" \
+	"m4boot=run m4boot_nor\0" \
+	"m4boot_ext=load ${dtype} ${disk}:1 ${m4loadaddr} ${m4image}; " \
+		"dcache flush; bootaux ${m4loadaddr}\0" \
+	"m4boot_nor=sf probe; sf read ${m4loadaddr} ${m4offset} ${m4size}; " \
+		"dcache flush; bootaux ${m4loadaddr}\0"
+
+#define CONFIG_PCIE_IMX_PERST_GPIO	IMX_GPIO_NR(4, 10)
+#define CONFIG_RGMII1
+#define CONFIG_RGMII2
+#define CONFIG_SYS_FSL_ESDHC_GPIO_WP
+#define ENET_MDIO_BASE			ENET_BASE_ADDR
+
+#define CONFIG_MXC_UART_BASE		UART1_BASE
+#define CONFIG_FEC_MXC_PHYADDR		4
+#define CONFIG_SYS_FSL_USDHC_NUM	2
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
+#define BD_CONSOLE	"ttymxc0"
+#define BD_I2C_MASK	7
+#define BD_LOG_LEVEL	"7"
+#define BD_CMA		"2M"
+
+#include "boundary.h"
+#define CONFIG_EXTRA_ENV_SETTINGS BD_BOUNDARY_ENV_SETTINGS \
+	"cmd_custom= \0" \
+	EXTRA_ENV_M4
+
+#endif	       /* __CONFIG_H */