From 5d9692693a6fc7550ffab39cf8ae1e522f974edc Mon Sep 17 00:00:00 2001
From: Troy Kisky <troy.kisky@boundarydevices.com>
Date: Tue, 20 Aug 2019 13:01:32 -0700
Subject: [PATCH] nitrogen8m: lpddr4_timing: replace some 2G values with values
from 3g/4g as should be the same
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
---
board/boundary/nitrogen8m/lpddr4_timing.c | 30 +++++------------------
1 file changed, 6 insertions(+), 24 deletions(-)
diff --git a/board/boundary/nitrogen8m/lpddr4_timing.c b/board/boundary/nitrogen8m/lpddr4_timing.c
index b784740f3d9..de2ca55437f 100644
--- a/board/boundary/nitrogen8m/lpddr4_timing.c
+++ b/board/boundary/nitrogen8m/lpddr4_timing.c
@@ -21,32 +21,14 @@
#endif
#if CONFIG_DDR_MB == 2048
-#define VAL_DDRC_RFSHTMG 0x00610090
-#define VAL_DDRC_DRAMTMG14 0x00000096
-#define VAL_DDRC_FREQ1_RFSHTMG 0x0014001F
-#define VAL_DDRC_FREQ1_DRAMTMG14 0x00000020
-#define VAL_DDRC_FREQ2_RFSHTMG 0x00030005
-#define VAL_DDRC_FREQ2_DRAMTMG14 0x00000005
/* Address map is from MSB 28: cs, r14, r13-r0, b2-b0, c9-c0 */
#define VAL_DDRC_ADDRMAP0 0x00000016
#define VAL_DDRC_ADDRMAP6 0x0f070707
#elif CONFIG_DDR_MB == 3072
-#define VAL_DDRC_RFSHTMG 0x006100E0
-#define VAL_DDRC_DRAMTMG14 0x000000E6
-#define VAL_DDRC_FREQ1_RFSHTMG 0x0014002F
-#define VAL_DDRC_FREQ1_DRAMTMG14 0x00000031
-#define VAL_DDRC_FREQ2_RFSHTMG 0x00030007
-#define VAL_DDRC_FREQ2_DRAMTMG14 0x00000008
/* Address map is from MSB 29: r15, r14, cs, r13-r0, b2-b0, c9-c0 */
#define VAL_DDRC_ADDRMAP0 0x00000015
#define VAL_DDRC_ADDRMAP6 0x48080707
#elif CONFIG_DDR_MB == 4096
-#define VAL_DDRC_RFSHTMG 0x006100E0
-#define VAL_DDRC_DRAMTMG14 0x000000E6
-#define VAL_DDRC_FREQ1_RFSHTMG 0x0014002F
-#define VAL_DDRC_FREQ1_DRAMTMG14 0x00000031
-#define VAL_DDRC_FREQ2_RFSHTMG 0x00030007
-#define VAL_DDRC_FREQ2_DRAMTMG14 0x00000008
/* Address map is from MSB 29: cs, r15, r14, r13-r0, b2-b0, c9-c0 */
#define VAL_DDRC_ADDRMAP0 0x00000017
#define VAL_DDRC_ADDRMAP6 0x07070707
@@ -64,7 +46,7 @@ static struct dram_cfg_param lpddr4_ddrc_cfg[] = {
{ DDRC_MSTR2(0), 0x00000000 },
{ DDRC_DERATEEN(0), 0x00000203 },
{ DDRC_DERATEINT(0), 0x0186A000 },
- { DDRC_RFSHTMG(0), VAL_DDRC_RFSHTMG },
+ { DDRC_RFSHTMG(0), 0x006100E0 },
{ DDRC_INIT0(0), 0xC003061C },
{ DDRC_INIT1(0), 0x009E0000 },
{ DDRC_INIT3(0), 0x00D4002D },
@@ -81,7 +63,7 @@ static struct dram_cfg_param lpddr4_ddrc_cfg[] = {
{ DDRC_DRAMTMG7(0), 0x00000401 },
{ DDRC_DRAMTMG12(0), 0x00020600 },
{ DDRC_DRAMTMG13(0), 0x0C100002 },
- { DDRC_DRAMTMG14(0), VAL_DDRC_DRAMTMG14 },
+ { DDRC_DRAMTMG14(0), 0x000000E6 },
{ DDRC_DRAMTMG17(0), 0x00A00050 },
{ DDRC_ZQCTL0(0), 0xC3200018 },
@@ -121,7 +103,7 @@ static struct dram_cfg_param lpddr4_ddrc_cfg[] = {
{ DDRC_FREQ1_DERATEEN(0), 0x0000001 },
{ DDRC_FREQ1_DERATEINT(0), 0x00518B00 },
{ DDRC_FREQ1_RFSHCTL0(0), 0x0020D040 },
- { DDRC_FREQ1_RFSHTMG(0), VAL_DDRC_FREQ1_RFSHTMG },
+ { DDRC_FREQ1_RFSHTMG(0), 0x0014002F },
{ DDRC_FREQ1_INIT3(0), 0x00940009 },
{ DDRC_FREQ1_INIT4(0), VAL_INIT4 },
{ DDRC_FREQ1_INIT6(0), 0x0066004A },
@@ -136,7 +118,7 @@ static struct dram_cfg_param lpddr4_ddrc_cfg[] = {
{ DDRC_FREQ1_DRAMTMG7(0), 0x00000301 },
{ DDRC_FREQ1_DRAMTMG12(0), 0x00020300 },
{ DDRC_FREQ1_DRAMTMG13(0), 0x0A100002 },
- { DDRC_FREQ1_DRAMTMG14(0), VAL_DDRC_FREQ1_DRAMTMG14 },
+ { DDRC_FREQ1_DRAMTMG14(0), 0x00000031 },
{ DDRC_FREQ1_DRAMTMG17(0), 0x00220011 },
{ DDRC_FREQ1_ZQCTL0(0), 0xC0A70006 },
{ DDRC_FREQ1_DFITMG0(0), 0x03858202 },
@@ -147,7 +129,7 @@ static struct dram_cfg_param lpddr4_ddrc_cfg[] = {
{ DDRC_FREQ2_DERATEEN(0), 0x0000001 },
{ DDRC_FREQ2_DERATEINT(0), 0x000C3500 },
{ DDRC_FREQ2_RFSHCTL0(0), 0x0020D040 },
- { DDRC_FREQ2_RFSHTMG(0), VAL_DDRC_FREQ2_RFSHTMG },
+ { DDRC_FREQ2_RFSHTMG(0), 0x00030007 },
{ DDRC_FREQ2_INIT3(0), 0x00840000 },
{ DDRC_FREQ2_INIT4(0), VAL_INIT4 },
{ DDRC_FREQ2_INIT6(0), 0x0066004A },
@@ -162,7 +144,7 @@ static struct dram_cfg_param lpddr4_ddrc_cfg[] = {
{ DDRC_FREQ2_DRAMTMG7(0), 0x00000301 },
{ DDRC_FREQ2_DRAMTMG12(0), 0x00020300 },
{ DDRC_FREQ2_DRAMTMG13(0), 0x0A100002 },
- { DDRC_FREQ2_DRAMTMG14(0), VAL_DDRC_FREQ2_DRAMTMG14 },
+ { DDRC_FREQ2_DRAMTMG14(0), 0x00000008 },
{ DDRC_FREQ2_DRAMTMG17(0), 0x00050003 },
{ DDRC_FREQ2_ZQCTL0(0), 0xC0190004 },
{ DDRC_FREQ2_DFITMG0(0), 0x03818200 },
--
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