diff --git a/Makefile b/Makefile
index d4c35ba09d71468b9b78e9e0da26d7e37efaa2dc..3c21f8ddf9e902dc20bf893995b1a38f295afe35 100644
--- a/Makefile
+++ b/Makefile
@@ -1130,7 +1130,11 @@ spl/u-boot-spl.pbl: spl/u-boot-spl.bin FORCE
$(call if_changed,mkimage)
ifeq ($(ARCH),arm)
+ifdef CONFIG_DM
+UBOOT_BINLOAD := u-boot-dtb.img
+else
UBOOT_BINLOAD := u-boot.img
+endif
else
UBOOT_BINLOAD := u-boot.bin
endif
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 2632099874b1d75d9b4db71126cc93a2dd72310f..3992f69b12f2b9a4089fb57529d1a9d58b232351 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -627,6 +627,14 @@ config TARGET_LS1021ATWR
select CPU_V7
select SUPPORT_SPL
+config TARGET_LS1043ARDB
+ bool "Support ls1043ardb"
+ select ARM64
+ select ARMV8_MULTIENTRY
+ select SUPPORT_SPL
+ help
+ Support for Freescale LS1043ARDB platform.
+
config TARGET_H2200
bool "Support h2200"
select CPU_PXA
@@ -743,6 +751,7 @@ source "board/freescale/ls2085aqds/Kconfig"
source "board/freescale/ls2085ardb/Kconfig"
source "board/freescale/ls1021aqds/Kconfig"
source "board/freescale/ls1021atwr/Kconfig"
+source "board/freescale/ls1043ardb/Kconfig"
source "board/freescale/mx23evk/Kconfig"
source "board/freescale/mx25pdk/Kconfig"
source "board/freescale/mx28evk/Kconfig"
diff --git a/arch/arm/cpu/armv7/ls102xa/Makefile b/arch/arm/cpu/armv7/ls102xa/Makefile
index 2d557827495303955390213be15350de6acd80e1..2311468ac98ee6a4577a46e1d166a44f06d45585 100644
--- a/arch/arm/cpu/armv7/ls102xa/Makefile
+++ b/arch/arm/cpu/armv7/ls102xa/Makefile
@@ -9,6 +9,7 @@ obj-y += clock.o
obj-y += timer.o
obj-y += fsl_epu.o
+obj-$(CONFIG_SCSI_AHCI_PLAT) += ls102xa_sata.o
obj-$(CONFIG_OF_LIBFDT) += fdt.o
obj-$(CONFIG_SYS_HAS_SERDES) += fsl_ls1_serdes.o ls102xa_serdes.o
obj-$(CONFIG_SPL) += spl.o
diff --git a/arch/arm/cpu/armv7/ls102xa/cpu.c b/arch/arm/cpu/armv7/ls102xa/cpu.c
index e2eb5f383a4a34b6de8bc665f98f676a107ca0da..df2e1b76f168eb4c67e28d591730787277a66ca9 100644
--- a/arch/arm/cpu/armv7/ls102xa/cpu.c
+++ b/arch/arm/cpu/armv7/ls102xa/cpu.c
@@ -301,6 +301,7 @@ int arch_cpu_init(void)
void *epu_base = (void *)(CONFIG_SYS_DCSRBAR + EPU_BLOCK_OFFSET);
void *rcpm2_base =
(void *)(CONFIG_SYS_DCSRBAR + DCSR_RCPM2_BLOCK_OFFSET);
+ struct ccsr_scfg *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR;
u32 state;
/*
@@ -328,6 +329,8 @@ int arch_cpu_init(void)
*/
fsl_epu_clean(epu_base);
+ setbits_be32(&scfg->snpcnfgcr, SCFG_SNPCNFGCR_SEC_RD_WR);
+
return 0;
}
diff --git a/arch/arm/cpu/armv7/ls102xa/fdt.c b/arch/arm/cpu/armv7/ls102xa/fdt.c
index e01d91178054e7920219d3117ea95e1b8ce98976..856abed94182ce741643a40bbe286bf613f97977 100644
--- a/arch/arm/cpu/armv7/ls102xa/fdt.c
+++ b/arch/arm/cpu/armv7/ls102xa/fdt.c
@@ -171,7 +171,7 @@ void ft_cpu_setup(void *blob, bd_t *bd)
do_fixup_by_compat_u32(blob, "fsl, ls1021a-flexcan",
"clock-frequency", busclk / 2, 1);
-#ifdef CONFIG_QSPI_BOOT
+#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
off = fdt_node_offset_by_compat_reg(blob, FSL_IFC_COMPAT,
CONFIG_SYS_IFC_ADDR);
fdt_set_node_status(blob, off, FDT_STATUS_DISABLED, 0);
diff --git a/arch/arm/cpu/armv7/ls102xa/ls102xa_sata.c b/arch/arm/cpu/armv7/ls102xa/ls102xa_sata.c
new file mode 100644
index 0000000000000000000000000000000000000000..deeb674c692a2408dd9464cb9304b952c0cd1a6c
--- /dev/null
+++ b/arch/arm/cpu/armv7/ls102xa/ls102xa_sata.c
@@ -0,0 +1,42 @@
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/immap_ls102xa.h>
+#include <ahci.h>
+#include <scsi.h>
+
+/* port register default value */
+#define AHCI_PORT_PHY_1_CFG 0xa003fffe
+#define AHCI_PORT_PHY_2_CFG 0x28183411
+#define AHCI_PORT_PHY_3_CFG 0x0e081004
+#define AHCI_PORT_PHY_4_CFG 0x00480811
+#define AHCI_PORT_PHY_5_CFG 0x192c96a4
+#define AHCI_PORT_TRANS_CFG 0x08000025
+
+#define SATA_ECC_REG_ADDR 0x20220520
+#define SATA_ECC_DISABLE 0x00020000
+
+int ls1021a_sata_init(void)
+{
+ struct ccsr_ahci __iomem *ccsr_ahci = (void *)AHCI_BASE_ADDR;
+
+#ifdef CONFIG_SYS_FSL_ERRATUM_A008407
+ out_le32((void *)SATA_ECC_REG_ADDR, SATA_ECC_DISABLE);
+#endif
+
+ out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG);
+ out_le32(&ccsr_ahci->pp2c, AHCI_PORT_PHY_2_CFG);
+ out_le32(&ccsr_ahci->pp3c, AHCI_PORT_PHY_3_CFG);
+ out_le32(&ccsr_ahci->pp4c, AHCI_PORT_PHY_4_CFG);
+ out_le32(&ccsr_ahci->pp5c, AHCI_PORT_PHY_5_CFG);
+ out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG);
+
+ ahci_init((void __iomem *)AHCI_BASE_ADDR);
+ scsi_scan(0);
+
+ return 0;
+}
diff --git a/arch/arm/cpu/armv8/Makefile b/arch/arm/cpu/armv8/Makefile
index adb11b3bda1a68f7851580d0863341d2fa04e96c..48c041bb9b30d556cda7d766e9e0e841a65c5017 100644
--- a/arch/arm/cpu/armv8/Makefile
+++ b/arch/arm/cpu/armv8/Makefile
@@ -15,6 +15,6 @@ obj-y += cache.o
obj-y += tlb.o
obj-y += transition.o
-obj-$(CONFIG_FSL_LSCH3) += fsl-lsch3/
+obj-$(CONFIG_FSL_LAYERSCAPE) += fsl-layerscape/
obj-$(CONFIG_ARCH_ZYNQMP) += zynqmp/
obj-$(CONFIG_TARGET_HIKEY) += hisilicon/
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Makefile b/arch/arm/cpu/armv8/fsl-layerscape/Makefile
new file mode 100644
index 0000000000000000000000000000000000000000..6fa08c8f3c17ea1f0d74a28b00cb05ae8cd3757e
--- /dev/null
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Makefile
@@ -0,0 +1,30 @@
+#
+# Copyright 2014-2015, Freescale Semiconductor
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += cpu.o
+obj-y += lowlevel.o
+obj-y += soc.o
+obj-$(CONFIG_MP) += mp.o
+obj-$(CONFIG_OF_LIBFDT) += fdt.o
+obj-$(CONFIG_SPL) += spl.o
+
+ifneq ($(CONFIG_FSL_LSCH3),)
+obj-y += fsl_lsch3_speed.o
+obj-$(CONFIG_SYS_HAS_SERDES) += fsl_lsch3_serdes.o
+else
+ifneq ($(CONFIG_FSL_LSCH2),)
+obj-y += fsl_lsch2_speed.o
+obj-$(CONFIG_SYS_HAS_SERDES) += fsl_lsch2_serdes.o
+endif
+endif
+
+ifneq ($(CONFIG_LS2085A),)
+obj-$(CONFIG_SYS_HAS_SERDES) += ls2085a_serdes.o
+else
+ifneq ($(CONFIG_LS1043A),)
+obj-$(CONFIG_SYS_HAS_SERDES) += ls1043a_serdes.o
+endif
+endif
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/README.lsch2 b/arch/arm/cpu/armv8/fsl-layerscape/README.lsch2
new file mode 100644
index 0000000000000000000000000000000000000000..a6ef830069e4ec881778c9b2abd06663ef63c783
--- /dev/null
+++ b/arch/arm/cpu/armv8/fsl-layerscape/README.lsch2
@@ -0,0 +1,10 @@
+#
+# Copyright 2015 Freescale Semiconductor
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+Freescale LayerScape with Chassis Generation 2
+
+This architecture supports Freescale ARMv8 SoCs with Chassis generation 2,
+for example LS1043A.
diff --git a/arch/arm/cpu/armv8/fsl-lsch3/README b/arch/arm/cpu/armv8/fsl-layerscape/README.lsch3
similarity index 99%
rename from arch/arm/cpu/armv8/fsl-lsch3/README
rename to arch/arm/cpu/armv8/fsl-layerscape/README.lsch3
index 08da7e4d1d2d9dd1f4b87136c5f4c987937b97e1..03e18f6573734fcc6461a1713297b2dd33100e7e 100644
--- a/arch/arm/cpu/armv8/fsl-lsch3/README
+++ b/arch/arm/cpu/armv8/fsl-layerscape/README.lsch3
@@ -1,5 +1,5 @@
#
-# Copyright 2014 Freescale Semiconductor
+# Copyright 2014-2015 Freescale Semiconductor
#
# SPDX-License-Identifier: GPL-2.0+
#
diff --git a/arch/arm/cpu/armv8/fsl-lsch3/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
similarity index 59%
rename from arch/arm/cpu/armv8/fsl-lsch3/cpu.c
rename to arch/arm/cpu/armv8/fsl-layerscape/cpu.c
index eb1213e9f0a90292dc7fcbde15e6219375ceb7f6..0cb0afa0b395be57af3f6d0a48394ad30be05da5 100644
--- a/arch/arm/cpu/armv8/fsl-lsch3/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
@@ -1,5 +1,5 @@
/*
- * Copyright 2014 Freescale Semiconductor, Inc.
+ * Copyright 2014-2015 Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
@@ -10,34 +10,28 @@
#include <asm/system.h>
#include <asm/armv8/mmu.h>
#include <asm/io.h>
-#include <asm/arch-fsl-lsch3/soc.h>
-#include <asm/arch-fsl-lsch3/immap_lsch3.h>
+#include <asm/arch/fsl_serdes.h>
+#include <asm/arch/soc.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/speed.h>
+#ifdef CONFIG_MP
+#include <asm/arch/mp.h>
+#endif
+#include <fm_eth.h>
#include <fsl_debug_server.h>
#include <fsl-mc/fsl_mc.h>
-#include <asm/arch/fsl_serdes.h>
#ifdef CONFIG_FSL_ESDHC
#include <fsl_esdhc.h>
#endif
-#include "cpu.h"
-#include "mp.h"
-#include "speed.h"
DECLARE_GLOBAL_DATA_PTR;
-static struct cpu_type cpu_type_list[] = {
-#ifdef CONFIG_LS2085A
- CPU_TYPE_ENTRY(LS2085, LS2085, 8),
- CPU_TYPE_ENTRY(LS2080, LS2080, 8),
- CPU_TYPE_ENTRY(LS2045, LS2045, 4),
-#endif
-};
-
void cpu_name(char *name)
{
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
unsigned int i, svr, ver;
- svr = in_le32(&gur->svr);
+ svr = gur_in32(&gur->svr);
ver = SVR_SOC_VER(svr);
for (i = 0; i < ARRAY_SIZE(cpu_type_list); i++)
@@ -54,146 +48,6 @@ void cpu_name(char *name)
}
#ifndef CONFIG_SYS_DCACHE_OFF
-
-#define SECTION_SHIFT_L0 39UL
-#define SECTION_SHIFT_L1 30UL
-#define SECTION_SHIFT_L2 21UL
-#define BLOCK_SIZE_L0 0x8000000000
-#define BLOCK_SIZE_L1 0x40000000
-#define BLOCK_SIZE_L2 0x200000
-
-#define NUM_OF_ENTRY 512
-
-#define TCR_EL2_PS_40BIT (2 << 16)
-#define LSCH3_VA_BITS (40)
-#define LSCH3_TCR (TCR_TG0_4K | \
- TCR_EL2_PS_40BIT | \
- TCR_SHARED_NON | \
- TCR_ORGN_NC | \
- TCR_IRGN_NC | \
- TCR_T0SZ(LSCH3_VA_BITS))
-#define LSCH3_TCR_FINAL (TCR_TG0_4K | \
- TCR_EL2_PS_40BIT | \
- TCR_SHARED_OUTER | \
- TCR_ORGN_WBWA | \
- TCR_IRGN_WBWA | \
- TCR_T0SZ(LSCH3_VA_BITS))
-
-#define CONFIG_SYS_FSL_CCSR_BASE 0x00000000
-#define CONFIG_SYS_FSL_CCSR_SIZE 0x10000000
-#define CONFIG_SYS_FSL_QSPI_BASE1 0x20000000
-#define CONFIG_SYS_FSL_QSPI_SIZE1 0x10000000
-#define CONFIG_SYS_FSL_IFC_BASE1 0x30000000
-#define CONFIG_SYS_FSL_IFC_SIZE1 0x10000000
-#define CONFIG_SYS_FSL_IFC_SIZE1_1 0x400000
-#define CONFIG_SYS_FSL_DRAM_BASE1 0x80000000
-#define CONFIG_SYS_FSL_DRAM_SIZE1 0x80000000
-#define CONFIG_SYS_FSL_QSPI_BASE2 0x400000000
-#define CONFIG_SYS_FSL_QSPI_SIZE2 0x100000000
-#define CONFIG_SYS_FSL_IFC_BASE2 0x500000000
-#define CONFIG_SYS_FSL_IFC_SIZE2 0x100000000
-#define CONFIG_SYS_FSL_DCSR_BASE 0x700000000
-#define CONFIG_SYS_FSL_DCSR_SIZE 0x40000000
-#define CONFIG_SYS_FSL_MC_BASE 0x80c000000
-#define CONFIG_SYS_FSL_MC_SIZE 0x4000000
-#define CONFIG_SYS_FSL_NI_BASE 0x810000000
-#define CONFIG_SYS_FSL_NI_SIZE 0x8000000
-#define CONFIG_SYS_FSL_QBMAN_BASE 0x818000000
-#define CONFIG_SYS_FSL_QBMAN_SIZE 0x8000000
-#define CONFIG_SYS_FSL_QBMAN_SIZE_1 0x4000000
-#define CONFIG_SYS_PCIE1_PHYS_SIZE 0x200000000
-#define CONFIG_SYS_PCIE2_PHYS_SIZE 0x200000000
-#define CONFIG_SYS_PCIE3_PHYS_SIZE 0x200000000
-#define CONFIG_SYS_PCIE4_PHYS_SIZE 0x200000000
-#define CONFIG_SYS_FSL_WRIOP1_BASE 0x4300000000
-#define CONFIG_SYS_FSL_WRIOP1_SIZE 0x100000000
-#define CONFIG_SYS_FSL_AIOP1_BASE 0x4b00000000
-#define CONFIG_SYS_FSL_AIOP1_SIZE 0x100000000
-#define CONFIG_SYS_FSL_PEBUF_BASE 0x4c00000000
-#define CONFIG_SYS_FSL_PEBUF_SIZE 0x400000000
-#define CONFIG_SYS_FSL_DRAM_BASE2 0x8080000000
-#define CONFIG_SYS_FSL_DRAM_SIZE2 0x7F80000000
-
-struct sys_mmu_table {
- u64 virt_addr;
- u64 phys_addr;
- u64 size;
- u64 memory_type;
- u64 share;
-};
-
-static const struct sys_mmu_table lsch3_early_mmu_table[] = {
- { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
- CONFIG_SYS_FSL_CCSR_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
- { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
- CONFIG_SYS_FSL_OCRAM_SIZE, MT_NORMAL, PMD_SECT_NON_SHARE },
- /* For IFC Region #1, only the first 4MB is cache-enabled */
- { CONFIG_SYS_FSL_IFC_BASE1, CONFIG_SYS_FSL_IFC_BASE1,
- CONFIG_SYS_FSL_IFC_SIZE1_1, MT_NORMAL, PMD_SECT_NON_SHARE },
- { CONFIG_SYS_FSL_IFC_BASE1 + CONFIG_SYS_FSL_IFC_SIZE1_1,
- CONFIG_SYS_FSL_IFC_BASE1 + CONFIG_SYS_FSL_IFC_SIZE1_1,
- CONFIG_SYS_FSL_IFC_SIZE1 - CONFIG_SYS_FSL_IFC_SIZE1_1,
- MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
- { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FSL_IFC_BASE1,
- CONFIG_SYS_FSL_IFC_SIZE1, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
- { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
- CONFIG_SYS_FSL_DRAM_SIZE1, MT_NORMAL, PMD_SECT_OUTER_SHARE },
- { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
- CONFIG_SYS_FSL_DCSR_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
- { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
- CONFIG_SYS_FSL_DRAM_SIZE2, MT_NORMAL, PMD_SECT_OUTER_SHARE },
-};
-
-static const struct sys_mmu_table lsch3_final_mmu_table[] = {
- { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
- CONFIG_SYS_FSL_CCSR_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
- { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
- CONFIG_SYS_FSL_OCRAM_SIZE, MT_NORMAL, PMD_SECT_NON_SHARE },
- { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
- CONFIG_SYS_FSL_DRAM_SIZE1, MT_NORMAL, PMD_SECT_OUTER_SHARE },
- { CONFIG_SYS_FSL_QSPI_BASE2, CONFIG_SYS_FSL_QSPI_BASE2,
- CONFIG_SYS_FSL_QSPI_SIZE2, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
- { CONFIG_SYS_FSL_IFC_BASE2, CONFIG_SYS_FSL_IFC_BASE2,
- CONFIG_SYS_FSL_IFC_SIZE2, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
- { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
- CONFIG_SYS_FSL_DCSR_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
- { CONFIG_SYS_FSL_MC_BASE, CONFIG_SYS_FSL_MC_BASE,
- CONFIG_SYS_FSL_MC_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
- { CONFIG_SYS_FSL_NI_BASE, CONFIG_SYS_FSL_NI_BASE,
- CONFIG_SYS_FSL_NI_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
- /* For QBMAN portal, only the first 64MB is cache-enabled */
- { CONFIG_SYS_FSL_QBMAN_BASE, CONFIG_SYS_FSL_QBMAN_BASE,
- CONFIG_SYS_FSL_QBMAN_SIZE_1, MT_NORMAL, PMD_SECT_NON_SHARE },
- { CONFIG_SYS_FSL_QBMAN_BASE + CONFIG_SYS_FSL_QBMAN_SIZE_1,
- CONFIG_SYS_FSL_QBMAN_BASE + CONFIG_SYS_FSL_QBMAN_SIZE_1,
- CONFIG_SYS_FSL_QBMAN_SIZE - CONFIG_SYS_FSL_QBMAN_SIZE_1,
- MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
- { CONFIG_SYS_PCIE1_PHYS_ADDR, CONFIG_SYS_PCIE1_PHYS_ADDR,
- CONFIG_SYS_PCIE1_PHYS_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
- { CONFIG_SYS_PCIE2_PHYS_ADDR, CONFIG_SYS_PCIE2_PHYS_ADDR,
- CONFIG_SYS_PCIE2_PHYS_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
- { CONFIG_SYS_PCIE3_PHYS_ADDR, CONFIG_SYS_PCIE3_PHYS_ADDR,
- CONFIG_SYS_PCIE3_PHYS_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
-#ifdef CONFIG_LS2085A
- { CONFIG_SYS_PCIE4_PHYS_ADDR, CONFIG_SYS_PCIE4_PHYS_ADDR,
- CONFIG_SYS_PCIE4_PHYS_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
-#endif
- { CONFIG_SYS_FSL_WRIOP1_BASE, CONFIG_SYS_FSL_WRIOP1_BASE,
- CONFIG_SYS_FSL_WRIOP1_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
- { CONFIG_SYS_FSL_AIOP1_BASE, CONFIG_SYS_FSL_AIOP1_BASE,
- CONFIG_SYS_FSL_AIOP1_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
- { CONFIG_SYS_FSL_PEBUF_BASE, CONFIG_SYS_FSL_PEBUF_BASE,
- CONFIG_SYS_FSL_PEBUF_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
- { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
- CONFIG_SYS_FSL_DRAM_SIZE2, MT_NORMAL, PMD_SECT_OUTER_SHARE },
-};
-
-struct table_info {
- u64 *ptr;
- u64 table_base;
- u64 entry_size;
-};
-
/*
* Set the block entries according to the information of the table.
*/
@@ -311,6 +165,7 @@ static inline void early_mmu_setup(void)
u64 *level1_table1 = (u64 *)(CONFIG_SYS_FSL_OCRAM_BASE + 0x2000);
u64 *level2_table0 = (u64 *)(CONFIG_SYS_FSL_OCRAM_BASE + 0x3000);
u64 *level2_table1 = (u64 *)(CONFIG_SYS_FSL_OCRAM_BASE + 0x4000);
+
struct table_info table = {level0_table, 0, BLOCK_SIZE_L0};
/* Invalidate all table entries */
@@ -320,19 +175,23 @@ static inline void early_mmu_setup(void)
set_pgtable_table(level0_table, 0, level1_table0);
set_pgtable_table(level0_table, 1, level1_table1);
set_pgtable_table(level1_table0, 0, level2_table0);
+
+#ifdef CONFIG_FSL_LSCH3
set_pgtable_table(level1_table0,
CONFIG_SYS_FLASH_BASE >> SECTION_SHIFT_L1,
level2_table1);
-
+#elif defined(CONFIG_FSL_LSCH2)
+ set_pgtable_table(level1_table0, 1, level2_table1);
+#endif
/* Find the table and fill in the block entries */
- for (i = 0; i < ARRAY_SIZE(lsch3_early_mmu_table); i++) {
- if (find_table(&lsch3_early_mmu_table[i],
+ for (i = 0; i < ARRAY_SIZE(early_mmu_table); i++) {
+ if (find_table(&early_mmu_table[i],
&table, level0_table) == 0) {
/*
* If find_table() returns error, it cannot be dealt
* with here. Breakpoint can be added for debugging.
*/
- set_block_entry(&lsch3_early_mmu_table[i], &table);
+ set_block_entry(&early_mmu_table[i], &table);
/*
* If set_block_entry() returns error, it cannot be
* dealt with here too.
@@ -341,7 +200,9 @@ static inline void early_mmu_setup(void)
}
el = current_el();
- set_ttbr_tcr_mair(el, (u64)level0_table, LSCH3_TCR, MEMORY_ATTRIBUTES);
+
+ set_ttbr_tcr_mair(el, (u64)level0_table, LAYERSCAPE_TCR,
+ MEMORY_ATTRIBUTES);
set_sctlr(get_sctlr() | CR_M);
}
@@ -353,7 +214,12 @@ static inline void early_mmu_setup(void)
* Level 1 table 0 contains 512 entries for each 1GB from 0 to 512GB.
* Level 1 table 1 contains 512 entries for each 1GB from 512GB to 1TB.
* Level 2 table 0 contains 512 entries for each 2MB from 0 to 1GB.
+ *
+ * For LSCH3:
* Level 2 table 1 contains 512 entries for each 2MB from 32GB to 33GB.
+ * For LSCH2:
+ * Level 2 table 1 contains 512 entries for each 2MB from 1GB to 2GB.
+ * Level 2 table 2 contains 512 entries for each 2MB from 20GB to 21GB.
*/
static inline void final_mmu_setup(void)
{
@@ -362,7 +228,12 @@ static inline void final_mmu_setup(void)
u64 *level1_table0 = (u64 *)(gd->arch.tlb_addr + 0x1000);
u64 *level1_table1 = (u64 *)(gd->arch.tlb_addr + 0x2000);
u64 *level2_table0 = (u64 *)(gd->arch.tlb_addr + 0x3000);
+#ifdef CONFIG_FSL_LSCH3
+ u64 *level2_table1 = (u64 *)(gd->arch.tlb_addr + 0x4000);
+#elif defined(CONFIG_FSL_LSCH2)
u64 *level2_table1 = (u64 *)(gd->arch.tlb_addr + 0x4000);
+ u64 *level2_table2 = (u64 *)(gd->arch.tlb_addr + 0x5000);
+#endif
struct table_info table = {level0_table, 0, BLOCK_SIZE_L0};
/* Invalidate all table entries */
@@ -372,23 +243,30 @@ static inline void final_mmu_setup(void)
set_pgtable_table(level0_table, 0, level1_table0);
set_pgtable_table(level0_table, 1, level1_table1);
set_pgtable_table(level1_table0, 0, level2_table0);
+#ifdef CONFIG_FSL_LSCH3
set_pgtable_table(level1_table0,
CONFIG_SYS_FSL_QBMAN_BASE >> SECTION_SHIFT_L1,
level2_table1);
+#elif defined(CONFIG_FSL_LSCH2)
+ set_pgtable_table(level1_table0, 1, level2_table1);
+ set_pgtable_table(level1_table0,
+ CONFIG_SYS_FSL_QBMAN_BASE >> SECTION_SHIFT_L1,
+ level2_table2);
+#endif
/* Find the table and fill in the block entries */
- for (i = 0; i < ARRAY_SIZE(lsch3_final_mmu_table); i++) {
- if (find_table(&lsch3_final_mmu_table[i],
+ for (i = 0; i < ARRAY_SIZE(final_mmu_table); i++) {
+ if (find_table(&final_mmu_table[i],
&table, level0_table) == 0) {
- if (set_block_entry(&lsch3_final_mmu_table[i],
+ if (set_block_entry(&final_mmu_table[i],
&table) != 0) {
printf("MMU error: could not set block entry for %p\n",
- &lsch3_final_mmu_table[i]);
+ &final_mmu_table[i]);
}
} else {
printf("MMU error: could not find the table for %p\n",
- &lsch3_final_mmu_table[i]);
+ &final_mmu_table[i]);
}
}
@@ -396,9 +274,13 @@ static inline void final_mmu_setup(void)
flush_dcache_range(gd->arch.tlb_addr,
gd->arch.tlb_addr + gd->arch.tlb_size);
+#ifdef CONFIG_SYS_DPAA_FMAN
+ flush_dcache_all();
+#endif
/* point TTBR to the new table */
el = current_el();
- set_ttbr_tcr_mair(el, (u64)level0_table, LSCH3_TCR_FINAL,
+
+ set_ttbr_tcr_mair(el, (u64)level0_table, LAYERSCAPE_TCR_FINAL,
MEMORY_ATTRIBUTES);
/*
* MMU is already enabled, just need to invalidate TLB to load the
@@ -434,8 +316,9 @@ static inline u32 initiator_type(u32 cluster, int init_id)
{
struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
u32 idx = (cluster >> (init_id * 8)) & TP_CLUSTER_INIT_MASK;
- u32 type = in_le32(&gur->tp_ityp[idx]);
+ u32 type = 0;
+ type = gur_in32(&gur->tp_ityp[idx]);
if (type & TP_ITYP_AV)
return type;
@@ -450,7 +333,8 @@ u32 cpu_mask(void)
do {
int j;
- cluster = in_le32(&gur->tp_cluster[i].lower);
+
+ cluster = gur_in32(&gur->tp_cluster[i].lower);
for (j = 0; j < TP_INIT_PER_CLUSTER; j++) {
type = initiator_type(cluster, j);
if (type) {
@@ -460,7 +344,7 @@ u32 cpu_mask(void)
}
}
i++;
- } while ((cluster & TP_CLUSTER_EOC) != TP_CLUSTER_EOC);
+ } while ((cluster & TP_CLUSTER_EOC) == 0x0);
return mask;
}
@@ -482,7 +366,8 @@ int fsl_qoriq_core_to_cluster(unsigned int core)
do {
int j;
- cluster = in_le32(&gur->tp_cluster[i].lower);
+
+ cluster = gur_in32(&gur->tp_cluster[i].lower);
for (j = 0; j < TP_INIT_PER_CLUSTER; j++) {
if (initiator_type(cluster, j)) {
if (count == core)
@@ -491,7 +376,7 @@ int fsl_qoriq_core_to_cluster(unsigned int core)
}
}
i++;
- } while ((cluster & TP_CLUSTER_EOC) != TP_CLUSTER_EOC);
+ } while ((cluster & TP_CLUSTER_EOC) == 0x0);
return -1; /* cannot identify the cluster */
}
@@ -505,7 +390,8 @@ u32 fsl_qoriq_core_to_type(unsigned int core)
do {
int j;
- cluster = in_le32(&gur->tp_cluster[i].lower);
+
+ cluster = gur_in32(&gur->tp_cluster[i].lower);
for (j = 0; j < TP_INIT_PER_CLUSTER; j++) {
type = initiator_type(cluster, j);
if (type) {
@@ -515,7 +401,7 @@ u32 fsl_qoriq_core_to_type(unsigned int core)
}
}
i++;
- } while ((cluster & TP_CLUSTER_EOC) != TP_CLUSTER_EOC);
+ } while ((cluster & TP_CLUSTER_EOC) == 0x0);
return -1; /* cannot identify the cluster */
}
@@ -527,15 +413,13 @@ int print_cpuinfo(void)
struct sys_info sysinfo;
char buf[32];
unsigned int i, core;
- u32 type;
+ u32 type, rcw;
puts("SoC: ");
cpu_name(buf);
- printf(" %s (0x%x)\n", buf, in_le32(&gur->svr));
-
+ printf(" %s (0x%x)\n", buf, gur_in32(&gur->svr));
memset((u8 *)buf, 0x00, ARRAY_SIZE(buf));
-
get_sys_info(&sysinfo);
puts("Clock Configuration:");
for_each_cpu(i, core, cpu_numcores(), cpu_mask()) {
@@ -551,18 +435,23 @@ int print_cpuinfo(void)
printf("\n Bus: %-4s MHz ",
strmhz(buf, sysinfo.freq_systembus));
printf("DDR: %-4s MT/s", strmhz(buf, sysinfo.freq_ddrbus));
+#ifdef CONFIG_SYS_DPAA_FMAN
+ printf(" FMAN: %-4s MHz", strmhz(buf, sysinfo.freq_fman[0]));
+#endif
+#ifdef CONFIG_FSL_LSCH3
printf(" DP-DDR: %-4s MT/s", strmhz(buf, sysinfo.freq_ddrbus2));
+#endif
puts("\n");
- /* Display the RCW, so that no one gets confused as to what RCW
+ /*
+ * Display the RCW, so that no one gets confused as to what RCW
* we're actually using for this boot.
*/
puts("Reset Configuration Word (RCW):");
for (i = 0; i < ARRAY_SIZE(gur->rcwsr); i++) {
- u32 rcw = in_le32(&gur->rcwsr[i]);
-
+ rcw = gur_in32(&gur->rcwsr[i]);
if ((i % 4) == 0)
- printf("\n %02x:", i * 4);
+ printf("\n %08x:", i * 4);
printf(" %08x", rcw);
}
puts("\n");
@@ -584,20 +473,28 @@ int cpu_eth_init(bd_t *bis)
#ifdef CONFIG_FSL_MC_ENET
error = fsl_mc_ldpaa_init(bis);
+#endif
+#ifdef CONFIG_FMAN_ENET
+ fm_standard_init(bis);
#endif
return error;
}
int arch_early_init_r(void)
{
- int rv;
- rv = fsl_lsch3_wake_seconday_cores();
+#ifdef CONFIG_MP
+ int rv = 1;
+ rv = fsl_layerscape_wake_seconday_cores();
if (rv)
printf("Did not wake secondary cores\n");
+#endif
#ifdef CONFIG_SYS_HAS_SERDES
fsl_serdes_init();
+#endif
+#ifdef CONFIG_FMAN_ENET
+ fman_enet_init();
#endif
return 0;
}
@@ -605,7 +502,9 @@ int arch_early_init_r(void)
int timer_init(void)
{
u32 __iomem *cntcr = (u32 *)CONFIG_SYS_FSL_TIMER_ADDR;
+#ifdef CONFIG_FSL_LSCH3
u32 __iomem *cltbenr = (u32 *)CONFIG_SYS_FSL_PMU_CLTBENR;
+#endif
#ifdef COUNTER_FREQUENCY_REAL
unsigned long cntfrq = COUNTER_FREQUENCY_REAL;
@@ -613,10 +512,12 @@ int timer_init(void)
asm volatile("msr cntfrq_el0, %0" : : "r" (cntfrq) : "memory");
#endif
+#ifdef CONFIG_FSL_LSCH3
/* Enable timebase for all clusters.
* It is safe to do so even some clusters are not enabled.
*/
out_le32(cltbenr, 0xf);
+#endif
/* Enable clock for timer
* This is a global setting.
@@ -632,7 +533,7 @@ void reset_cpu(ulong addr)
u32 val;
/* Raise RESET_REQ_B */
- val = in_le32(rstcr);
+ val = scfg_in32(rstcr);
val |= 0x02;
- out_le32(rstcr, val);
+ scfg_out32(rstcr, val);
}
diff --git a/arch/arm/cpu/armv8/fsl-lsch3/cpu.h b/arch/arm/cpu/armv8/fsl-layerscape/cpu.h
similarity index 71%
rename from arch/arm/cpu/armv8/fsl-lsch3/cpu.h
rename to arch/arm/cpu/armv8/fsl-layerscape/cpu.h
index 2e3312b99beec55f38d76b895c199750f3a67fac..8072f3ca6a09917e023df9cc5e93845125e45372 100644
--- a/arch/arm/cpu/armv8/fsl-lsch3/cpu.h
+++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.h
@@ -1,5 +1,5 @@
/*
- * Copyright 2014, Freescale Semiconductor
+ * Copyright 2014-2015, Freescale Semiconductor
*
* SPDX-License-Identifier: GPL-2.0+
*/
diff --git a/arch/arm/cpu/armv8/fsl-lsch3/fdt.c b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
similarity index 90%
rename from arch/arm/cpu/armv8/fsl-lsch3/fdt.c
rename to arch/arm/cpu/armv8/fsl-layerscape/fdt.c
index 567c41927ad7d354374752d43b72bdb9ab6b8f4b..47599c121764419c7a356d1b628e92cbf5d53a1a 100644
--- a/arch/arm/cpu/armv8/fsl-lsch3/fdt.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
@@ -1,5 +1,5 @@
/*
- * Copyright 2014 Freescale Semiconductor, Inc.
+ * Copyright 2014-2015 Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
@@ -7,11 +7,22 @@
#include <common.h>
#include <libfdt.h>
#include <fdt_support.h>
-#include <asm/arch-fsl-lsch3/fdt.h>
+#include <phy.h>
+#ifdef CONFIG_FSL_LSCH3
+#include <asm/arch/fdt.h>
+#endif
#ifdef CONFIG_FSL_ESDHC
#include <fsl_esdhc.h>
#endif
-#include "mp.h"
+#ifdef CONFIG_MP
+#include <asm/arch/mp.h>
+#endif
+
+int fdt_fixup_phy_connection(void *blob, int offset, phy_interface_t phyc)
+{
+ return fdt_setprop_string(blob, offset, "phy-connection-type",
+ phy_string_for_interface(phyc));
+}
#ifdef CONFIG_MP
void ft_fixup_cpu(void *blob)
@@ -33,8 +44,8 @@ void ft_fixup_cpu(void *blob)
off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4);
while (off != -FDT_ERR_NOTFOUND) {
reg = (fdt32_t *)fdt_getprop(blob, off, "reg", 0);
- core_id = of_read_number(reg, addr_cells);
if (reg) {
+ core_id = of_read_number(reg, addr_cells);
if (core_id == 0 || (is_core_online(core_id))) {
val = spin_tbl_addr;
val += id_to_core(core_id) *
@@ -150,6 +161,7 @@ void append_mmu_masters(void *blob, const char *smmu_path,
* for all DPAA2 devices.
*
*/
+#ifdef CONFIG_FSL_LSCH3
static void fdt_fixup_smmu(void *blob)
{
int nodeoffset;
@@ -165,6 +177,7 @@ static void fdt_fixup_smmu(void *blob)
fdt_fixup_smmu_pcie(blob);
#endif
}
+#endif
void ft_cpu_setup(void *blob, bd_t *bd)
{
@@ -181,9 +194,11 @@ void ft_cpu_setup(void *blob, bd_t *bd)
ft_pci_setup(blob, bd);
#endif
-#if defined(CONFIG_FSL_ESDHC)
+#ifdef CONFIG_FSL_ESDHC
fdt_fixup_esdhc(blob, bd);
#endif
+#ifdef CONFIG_FSL_LSCH3
fdt_fixup_smmu(blob);
+#endif
}
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_serdes.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_serdes.c
new file mode 100644
index 0000000000000000000000000000000000000000..f7178d14705e03f074aa0433e296910848b0266a
--- /dev/null
+++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_serdes.c
@@ -0,0 +1,117 @@
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/errno.h>
+#include <asm/arch/fsl_serdes.h>
+#include <asm/arch/soc.h>
+
+#ifdef CONFIG_SYS_FSL_SRDS_1
+static u8 serdes1_prtcl_map[SERDES_PRCTL_COUNT];
+#endif
+
+int is_serdes_configured(enum srds_prtcl device)
+{
+ int ret = 0;
+
+#ifdef CONFIG_SYS_FSL_SRDS_1
+ ret |= serdes1_prtcl_map[device];
+#endif
+
+ return !!ret;
+}
+
+int serdes_get_first_lane(u32 sd, enum srds_prtcl device)
+{
+ struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ u32 cfg = gur_in32(&gur->rcwsr[4]);
+ int i;
+
+ switch (sd) {
+#ifdef CONFIG_SYS_FSL_SRDS_1
+ case FSL_SRDS_1:
+ cfg &= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK;
+ cfg >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT;
+ break;
+#endif
+ default:
+ printf("invalid SerDes%d\n", sd);
+ break;
+ }
+
+ /* Is serdes enabled at all? */
+ if (unlikely(cfg == 0))
+ return -ENODEV;
+
+ for (i = 0; i < SRDS_MAX_LANES; i++) {
+ if (serdes_get_prtcl(sd, cfg, i) == device)
+ return i;
+ }
+
+ return -ENODEV;
+}
+
+int get_serdes_protocol(void)
+{
+ struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ u32 cfg = gur_in32(&gur->rcwsr[4]) &
+ FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK;
+ cfg >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT;
+
+ return cfg;
+}
+
+const char *serdes_clock_to_string(u32 clock)
+{
+ switch (clock) {
+ case SRDS_PLLCR0_RFCK_SEL_100:
+ return "100";
+ case SRDS_PLLCR0_RFCK_SEL_125:
+ return "125";
+ case SRDS_PLLCR0_RFCK_SEL_156_25:
+ return "156.25";
+ default:
+ return "100";
+ }
+}
+
+void serdes_init(u32 sd, u32 sd_addr, u32 sd_prctl_mask, u32 sd_prctl_shift,
+ u8 serdes_prtcl_map[SERDES_PRCTL_COUNT])
+{
+ struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ u32 cfg;
+ int lane;
+
+ memset(serdes_prtcl_map, 0, sizeof(serdes_prtcl_map));
+
+ cfg = gur_in32(&gur->rcwsr[4]) & sd_prctl_mask;
+ cfg >>= sd_prctl_shift;
+ printf("Using SERDES%d Protocol: %d (0x%x)\n", sd + 1, cfg, cfg);
+
+ if (!is_serdes_prtcl_valid(sd, cfg))
+ printf("SERDES%d[PRTCL] = 0x%x is not valid\n", sd + 1, cfg);
+
+ for (lane = 0; lane < SRDS_MAX_LANES; lane++) {
+ enum srds_prtcl lane_prtcl = serdes_get_prtcl(sd, cfg, lane);
+
+ if (unlikely(lane_prtcl >= SERDES_PRCTL_COUNT))
+ debug("Unknown SerDes lane protocol %d\n", lane_prtcl);
+ else
+ serdes_prtcl_map[lane_prtcl] = 1;
+ }
+}
+
+void fsl_serdes_init(void)
+{
+#ifdef CONFIG_SYS_FSL_SRDS_1
+ serdes_init(FSL_SRDS_1,
+ CONFIG_SYS_FSL_SERDES_ADDR,
+ FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK,
+ FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT,
+ serdes1_prtcl_map);
+#endif
+}
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
new file mode 100644
index 0000000000000000000000000000000000000000..6f6a588292b1083b42d52a3a98aeaa2933574cfe
--- /dev/null
+++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
@@ -0,0 +1,180 @@
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <linux/compiler.h>
+#include <asm/io.h>
+#include <asm/processor.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/soc.h>
+#include <fsl_ifc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifndef CONFIG_SYS_FSL_NUM_CC_PLLS
+#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
+#endif
+
+void get_sys_info(struct sys_info *sys_info)
+{
+ struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+#ifdef CONFIG_FSL_IFC
+ struct fsl_ifc ifc_regs = {(void *)CONFIG_SYS_IFC_ADDR, (void *)NULL};
+ u32 ccr;
+#endif
+#if defined(CONFIG_FSL_ESDHC) || defined(CONFIG_SYS_DPAA_FMAN)
+ u32 rcw_tmp;
+#endif
+ struct ccsr_clk *clk = (void *)(CONFIG_SYS_FSL_CLK_ADDR);
+ unsigned int cpu;
+ const u8 core_cplx_pll[8] = {
+ [0] = 0, /* CC1 PPL / 1 */
+ [1] = 0, /* CC1 PPL / 2 */
+ [4] = 1, /* CC2 PPL / 1 */
+ [5] = 1, /* CC2 PPL / 2 */
+ };
+
+ const u8 core_cplx_pll_div[8] = {
+ [0] = 1, /* CC1 PPL / 1 */
+ [1] = 2, /* CC1 PPL / 2 */
+ [4] = 1, /* CC2 PPL / 1 */
+ [5] = 2, /* CC2 PPL / 2 */
+ };
+
+ uint i;
+ uint freq_c_pll[CONFIG_SYS_FSL_NUM_CC_PLLS];
+ uint ratio[CONFIG_SYS_FSL_NUM_CC_PLLS];
+ unsigned long sysclk = CONFIG_SYS_CLK_FREQ;
+
+ sys_info->freq_systembus = sysclk;
+#ifdef CONFIG_DDR_CLK_FREQ
+ sys_info->freq_ddrbus = CONFIG_DDR_CLK_FREQ;
+#else
+ sys_info->freq_ddrbus = sysclk;
+#endif
+
+ sys_info->freq_systembus *= (gur_in32(&gur->rcwsr[0]) >>
+ FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_SHIFT) &
+ FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_MASK;
+ sys_info->freq_ddrbus *= (gur_in32(&gur->rcwsr[0]) >>
+ FSL_CHASSIS2_RCWSR0_MEM_PLL_RAT_SHIFT) &
+ FSL_CHASSIS2_RCWSR0_MEM_PLL_RAT_MASK;
+
+ for (i = 0; i < CONFIG_SYS_FSL_NUM_CC_PLLS; i++) {
+ ratio[i] = (in_be32(&clk->pllcgsr[i].pllcngsr) >> 1) & 0xff;
+ if (ratio[i] > 4)
+ freq_c_pll[i] = sysclk * ratio[i];
+ else
+ freq_c_pll[i] = sys_info->freq_systembus * ratio[i];
+ }
+
+ for (cpu = 0; cpu < CONFIG_MAX_CPUS; cpu++) {
+ u32 c_pll_sel = (in_be32(&clk->clkcsr[cpu].clkcncsr) >> 27)
+ & 0xf;
+ u32 cplx_pll = core_cplx_pll[c_pll_sel];
+
+ sys_info->freq_processor[cpu] =
+ freq_c_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel];
+ }
+
+#define HWA_CGA_M1_CLK_SEL 0xe0000000
+#define HWA_CGA_M1_CLK_SHIFT 29
+#ifdef CONFIG_SYS_DPAA_FMAN
+ rcw_tmp = in_be32(&gur->rcwsr[7]);
+ switch ((rcw_tmp & HWA_CGA_M1_CLK_SEL) >> HWA_CGA_M1_CLK_SHIFT) {
+ case 2:
+ sys_info->freq_fman[0] = freq_c_pll[0] / 2;
+ break;
+ case 3:
+ sys_info->freq_fman[0] = freq_c_pll[0] / 3;
+ break;
+ case 6:
+ sys_info->freq_fman[0] = freq_c_pll[1] / 2;
+ break;
+ case 7:
+ sys_info->freq_fman[0] = freq_c_pll[1] / 3;
+ break;
+ default:
+ printf("Error: Unknown FMan1 clock select!\n");
+ break;
+ }
+#endif
+
+#define HWA_CGA_M2_CLK_SEL 0x00000007
+#define HWA_CGA_M2_CLK_SHIFT 0
+#ifdef CONFIG_FSL_ESDHC
+ rcw_tmp = in_be32(&gur->rcwsr[15]);
+ rcw_tmp = (rcw_tmp & HWA_CGA_M2_CLK_SEL) >> HWA_CGA_M2_CLK_SHIFT;
+ sys_info->freq_sdhc = freq_c_pll[1] / rcw_tmp;
+#endif
+
+#if defined(CONFIG_FSL_IFC)
+ ccr = ifc_in32(&ifc_regs.gregs->ifc_ccr);
+ ccr = ((ccr & IFC_CCR_CLK_DIV_MASK) >> IFC_CCR_CLK_DIV_SHIFT) + 1;
+
+ sys_info->freq_localbus = sys_info->freq_systembus / ccr;
+#endif
+}
+
+int get_clocks(void)
+{
+ struct sys_info sys_info;
+
+ get_sys_info(&sys_info);
+ gd->cpu_clk = sys_info.freq_processor[0];
+ gd->bus_clk = sys_info.freq_systembus;
+ gd->mem_clk = sys_info.freq_ddrbus;
+
+#ifdef CONFIG_FSL_ESDHC
+ gd->arch.sdhc_clk = sys_info.freq_sdhc;
+#endif
+
+ if (gd->cpu_clk != 0)
+ return 0;
+ else
+ return 1;
+}
+
+ulong get_bus_freq(ulong dummy)
+{
+ return gd->bus_clk;
+}
+
+ulong get_ddr_freq(ulong dummy)
+{
+ return gd->mem_clk;
+}
+
+#ifdef CONFIG_FSL_ESDHC
+int get_sdhc_freq(ulong dummy)
+{
+ return gd->arch.sdhc_clk;
+}
+#endif
+
+int get_serial_clock(void)
+{
+ return gd->bus_clk;
+}
+
+unsigned int mxc_get_clock(enum mxc_clock clk)
+{
+ switch (clk) {
+ case MXC_I2C_CLK:
+ return get_bus_freq(0);
+#if defined(CONFIG_FSL_ESDHC)
+ case MXC_ESDHC_CLK:
+ return get_sdhc_freq(0);
+#endif
+ case MXC_DSPI_CLK:
+ return get_bus_freq(0);
+ case MXC_UART_CLK:
+ return get_bus_freq(0);
+ default:
+ printf("Unsupported clock\n");
+ }
+ return 0;
+}
diff --git a/arch/arm/cpu/armv8/fsl-lsch3/fsl_lsch3_serdes.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c
similarity index 95%
rename from arch/arm/cpu/armv8/fsl-lsch3/fsl_lsch3_serdes.c
rename to arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c
index ae0834365e4487ca01860a0bfbde7180367cecb9..2ab8da64030763fd87055b1c5f5f5f0fdab52959 100644
--- a/arch/arm/cpu/armv8/fsl-lsch3/fsl_lsch3_serdes.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c
@@ -1,5 +1,5 @@
/*
- * Copyright 2015 Freescale Semiconductor, Inc.
+ * Copyright 2014-2015 Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
@@ -8,7 +8,7 @@
#include <asm/io.h>
#include <asm/errno.h>
#include <asm/arch/fsl_serdes.h>
-#include <asm/arch-fsl-lsch3/immap_lsch3.h>
+#include <asm/arch/soc.h>
#include <fsl-mc/ldpaa_wriop.h>
#ifdef CONFIG_SYS_FSL_SRDS_1
@@ -35,7 +35,7 @@ int is_serdes_configured(enum srds_prtcl device)
int serdes_get_first_lane(u32 sd, enum srds_prtcl device)
{
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
- u32 cfg = in_le32(&gur->rcwsr[28]);
+ u32 cfg = gur_in32(&gur->rcwsr[28]);
int i;
switch (sd) {
@@ -76,7 +76,7 @@ void serdes_init(u32 sd, u32 sd_addr, u32 sd_prctl_mask, u32 sd_prctl_shift,
memset(serdes_prtcl_map, 0, sizeof(serdes_prtcl_map));
- cfg = in_le32(&gur->rcwsr[28]) & sd_prctl_mask;
+ cfg = gur_in32(&gur->rcwsr[28]) & sd_prctl_mask;
cfg >>= sd_prctl_shift;
printf("Using SERDES%d Protocol: %d (0x%x)\n", sd + 1, cfg, cfg);
diff --git a/arch/arm/cpu/armv8/fsl-lsch3/speed.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c
similarity index 93%
rename from arch/arm/cpu/armv8/fsl-lsch3/speed.c
rename to arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c
index d9f137cc2df2e1695a747134292563acfd78ffbb..4054c3c7d292a2681fe98654a3a475d7c78d7065 100644
--- a/arch/arm/cpu/armv8/fsl-lsch3/speed.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c
@@ -1,5 +1,5 @@
/*
- * Copyright 2014, Freescale Semiconductor, Inc.
+ * Copyright 2014-2015, Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*
@@ -11,8 +11,8 @@
#include <fsl_ifc.h>
#include <asm/processor.h>
#include <asm/io.h>
-#include <asm/arch-fsl-lsch3/immap_lsch3.h>
#include <asm/arch/clock.h>
+#include <asm/arch/soc.h>
#include "cpu.h"
DECLARE_GLOBAL_DATA_PTR;
@@ -83,15 +83,15 @@ void get_sys_info(struct sys_info *sys_info)
sys_info->freq_ddrbus2 = sysclk;
#endif
- sys_info->freq_systembus *= (in_le32(&gur->rcwsr[0]) >>
+ sys_info->freq_systembus *= (gur_in32(&gur->rcwsr[0]) >>
FSL_CHASSIS3_RCWSR0_SYS_PLL_RAT_SHIFT) &
FSL_CHASSIS3_RCWSR0_SYS_PLL_RAT_MASK;
/* Platform clock is half of platform PLL */
sys_info->freq_systembus /= 2;
- sys_info->freq_ddrbus *= (in_le32(&gur->rcwsr[0]) >>
+ sys_info->freq_ddrbus *= (gur_in32(&gur->rcwsr[0]) >>
FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_SHIFT) &
FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_MASK;
- sys_info->freq_ddrbus2 *= (in_le32(&gur->rcwsr[0]) >>
+ sys_info->freq_ddrbus2 *= (gur_in32(&gur->rcwsr[0]) >>
FSL_CHASSIS3_RCWSR0_MEM2_PLL_RAT_SHIFT) &
FSL_CHASSIS3_RCWSR0_MEM2_PLL_RAT_MASK;
@@ -118,7 +118,7 @@ void get_sys_info(struct sys_info *sys_info)
}
#if defined(CONFIG_FSL_IFC)
- ccr = in_le32(&ifc_regs.gregs->ifc_ccr);
+ ccr = ifc_in32(&ifc_regs.gregs->ifc_ccr);
ccr = ((ccr & IFC_CCR_CLK_DIV_MASK) >> IFC_CCR_CLK_DIV_SHIFT) + 1;
sys_info->freq_localbus = sys_info->freq_systembus / ccr;
diff --git a/arch/arm/cpu/armv8/fsl-lsch3/lowlevel.S b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
similarity index 97%
rename from arch/arm/cpu/armv8/fsl-lsch3/lowlevel.S
rename to arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
index 6b19d36f115fce5d5647ff3edd9db98a6781e608..41e17049865d0688c4a20e3a72cf5e667bda8092 100644
--- a/arch/arm/cpu/armv8/fsl-lsch3/lowlevel.S
+++ b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
@@ -1,5 +1,5 @@
/*
- * (C) Copyright 2014 Freescale Semiconductor
+ * (C) Copyright 2014-2015 Freescale Semiconductor
*
* SPDX-License-Identifier: GPL-2.0+
*
@@ -10,11 +10,14 @@
#include <linux/linkage.h>
#include <asm/gic.h>
#include <asm/macro.h>
-#include "mp.h"
+#ifdef CONFIG_MP
+#include <asm/arch/mp.h>
+#endif
ENTRY(lowlevel_init)
mov x29, lr /* Save LR */
+#ifdef CONFIG_FSL_LSCH3
/* Add fully-coherent masters to DVM domain */
ldr x0, =CCI_MN_BASE
ldr x1, =CCI_MN_RNF_NODEID_LIST
@@ -81,6 +84,7 @@ ENTRY(lowlevel_init)
ldr x0, =CCI_S2_QOS_CONTROL_BASE(20)
ldr x1, =0x00FF000C
bl ccn504_set_qos
+#endif
/* Set the SMMU page size in the sACR register */
ldr x1, =SMMU_BASE
@@ -106,10 +110,12 @@ ENTRY(lowlevel_init)
branch_if_master x0, x1, 2f
+#if defined(CONFIG_MP) && defined(CONFIG_ARMV8_MULTIENTRY)
ldr x0, =secondary_boot_func
blr x0
-2:
+#endif
+2:
#ifdef CONFIG_FSL_TZPC_BP147
/* Set Non Secure access for all devices protected via TZPC */
ldr x1, =TZPCDECPROT_0_SET_BASE /* Decode Protection-0 Set Reg */
@@ -245,6 +251,7 @@ ENTRY(__asm_flush_l3_cache)
ret
ENDPROC(__asm_flush_l3_cache)
+#ifdef CONFIG_MP
/* Keep literals not used by the secondary boot code outside it */
.ltorg
@@ -353,3 +360,4 @@ __real_cntfrq:
/* Secondary Boot Code ends here */
__secondary_boot_code_size:
.quad .-secondary_boot_code
+#endif
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls1043a_serdes.c b/arch/arm/cpu/armv8/fsl-layerscape/ls1043a_serdes.c
new file mode 100644
index 0000000000000000000000000000000000000000..e54d3899bb9962096aaefaab641c1fd1787f14cd
--- /dev/null
+++ b/arch/arm/cpu/armv8/fsl-layerscape/ls1043a_serdes.c
@@ -0,0 +1,86 @@
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/fsl_serdes.h>
+#include <asm/arch/immap_lsch2.h>
+
+struct serdes_config {
+ u32 protocol;
+ u8 lanes[SRDS_MAX_LANES];
+};
+
+static struct serdes_config serdes1_cfg_tbl[] = {
+ /* SerDes 1 */
+ {0x1555, {XFI_FM1_MAC9, PCIE1, PCIE2, PCIE3} },
+ {0x2555, {SGMII_2500_FM1_DTSEC9, PCIE1, PCIE2, PCIE3} },
+ {0x4555, {QSGMII_FM1_A, PCIE1, PCIE2, PCIE3} },
+ {0x4558, {QSGMII_FM1_A, PCIE1, PCIE2, SATA1} },
+ {0x1355, {XFI_FM1_MAC9, SGMII_FM1_DTSEC2, PCIE2, PCIE3} },
+ {0x2355, {SGMII_2500_FM1_DTSEC9, SGMII_FM1_DTSEC2, PCIE2, PCIE3} },
+ {0x3335, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC5,
+ PCIE3} },
+ {0x3355, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC2, PCIE2, PCIE3} },
+ {0x3358, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC2, PCIE2, SATA1} },
+ {0x3555, {SGMII_FM1_DTSEC9, PCIE1, PCIE2, PCIE3} },
+ {0x3558, {SGMII_FM1_DTSEC9, PCIE1, PCIE2, SATA1} },
+ {0x7000, {PCIE1, PCIE1, PCIE1, PCIE1} },
+ {0x9998, {PCIE1, PCIE2, PCIE3, SATA1} },
+ {0x6058, {PCIE1, PCIE1, PCIE2, SATA1} },
+ {0x1455, {XFI_FM1_MAC9, QSGMII_FM1_A, PCIE2, PCIE3} },
+ {0x2455, {SGMII_2500_FM1_DTSEC9, QSGMII_FM1_A, PCIE2, PCIE3} },
+ {0x2255, {SGMII_2500_FM1_DTSEC9, SGMII_2500_FM1_DTSEC2, PCIE2, PCIE3} },
+ {0x3333, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC5,
+ SGMII_FM1_DTSEC6} },
+ {}
+};
+
+static struct serdes_config *serdes_cfg_tbl[] = {
+ serdes1_cfg_tbl,
+};
+
+enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane)
+{
+ struct serdes_config *ptr;
+
+ if (serdes >= ARRAY_SIZE(serdes_cfg_tbl))
+ return 0;
+
+ ptr = serdes_cfg_tbl[serdes];
+ while (ptr->protocol) {
+ if (ptr->protocol == cfg)
+ return ptr->lanes[lane];
+ ptr++;
+ }
+
+ return 0;
+}
+
+int is_serdes_prtcl_valid(int serdes, u32 prtcl)
+{
+ int i;
+ struct serdes_config *ptr;
+
+ if (serdes >= ARRAY_SIZE(serdes_cfg_tbl))
+ return 0;
+
+ ptr = serdes_cfg_tbl[serdes];
+ while (ptr->protocol) {
+ if (ptr->protocol == prtcl)
+ break;
+ ptr++;
+ }
+
+ if (!ptr->protocol)
+ return 0;
+
+ for (i = 0; i < SRDS_MAX_LANES; i++) {
+ if (ptr->lanes[i] != NONE)
+ return 1;
+ }
+
+ return 0;
+}
diff --git a/arch/arm/cpu/armv8/fsl-lsch3/ls2085a_serdes.c b/arch/arm/cpu/armv8/fsl-layerscape/ls2085a_serdes.c
similarity index 97%
rename from arch/arm/cpu/armv8/fsl-lsch3/ls2085a_serdes.c
rename to arch/arm/cpu/armv8/fsl-layerscape/ls2085a_serdes.c
index 0b79a501d9d1d3ea6f7a3f6ce9ad1f0f8161ca0e..ea3114cca4eb644366a5878ee706fd1e3c8501fc 100644
--- a/arch/arm/cpu/armv8/fsl-lsch3/ls2085a_serdes.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/ls2085a_serdes.c
@@ -1,12 +1,11 @@
/*
- * Copyright 2015 Freescale Semiconductor, Inc.
+ * Copyright 2014-2015 Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/arch/fsl_serdes.h>
-#include <asm/arch-fsl-lsch3/immap_lsch3.h>
struct serdes_config {
u8 protocol;
diff --git a/arch/arm/cpu/armv8/fsl-lsch3/mp.c b/arch/arm/cpu/armv8/fsl-layerscape/mp.c
similarity index 83%
rename from arch/arm/cpu/armv8/fsl-lsch3/mp.c
rename to arch/arm/cpu/armv8/fsl-layerscape/mp.c
index da7853a5af4043068624c1876009e58e614a62fd..0d600db09054570213623c1692248aa4d6df448b 100644
--- a/arch/arm/cpu/armv8/fsl-lsch3/mp.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/mp.c
@@ -1,5 +1,5 @@
/*
- * Copyright 2014 Freescale Semiconductor, Inc.
+ * Copyright 2014-2015 Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
@@ -7,9 +7,8 @@
#include <common.h>
#include <asm/io.h>
#include <asm/system.h>
-#include <asm/io.h>
-#include <asm/arch-fsl-lsch3/immap_lsch3.h>
-#include "mp.h"
+#include <asm/arch/mp.h>
+#include <asm/arch/soc.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -23,10 +22,14 @@ phys_addr_t determine_mp_bootpg(void)
return (phys_addr_t)&secondary_boot_code;
}
-int fsl_lsch3_wake_seconday_cores(void)
+int fsl_layerscape_wake_seconday_cores(void)
{
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+#ifdef CONFIG_FSL_LSCH3
struct ccsr_reset __iomem *rst = (void *)(CONFIG_SYS_FSL_RST_ADDR);
+#elif defined(CONFIG_FSL_LSCH2)
+ struct ccsr_scfg __iomem *scfg = (void *)(CONFIG_SYS_FSL_SCFG_ADDR);
+#endif
u32 cores, cpu_up_mask = 1;
int i, timeout = 10;
u64 *table = get_spin_tbl_addr();
@@ -48,13 +51,24 @@ int fsl_lsch3_wake_seconday_cores(void)
(CONFIG_MAX_CPUS*SPIN_TABLE_ELEM_SIZE));
printf("Waking secondary cores to start from %lx\n", gd->relocaddr);
- out_le32(&gur->bootlocptrh, (u32)(gd->relocaddr >> 32));
- out_le32(&gur->bootlocptrl, (u32)gd->relocaddr);
- out_le32(&gur->scratchrw[6], 1);
+
+#ifdef CONFIG_FSL_LSCH3
+ gur_out32(&gur->bootlocptrh, (u32)(gd->relocaddr >> 32));
+ gur_out32(&gur->bootlocptrl, (u32)gd->relocaddr);
+ gur_out32(&gur->scratchrw[6], 1);
asm volatile("dsb st" : : : "memory");
rst->brrl = cores;
asm volatile("dsb st" : : : "memory");
+#elif defined(CONFIG_FSL_LSCH2)
+ scfg_out32(&scfg->scratchrw[0], (u32)(gd->relocaddr >> 32));
+ scfg_out32(&scfg->scratchrw[1], (u32)gd->relocaddr);
+ asm volatile("dsb st" : : : "memory");
+ gur_out32(&gur->brrl, cores);
+ asm volatile("dsb st" : : : "memory");
+ /* Bootup online cores */
+ scfg_out32(&scfg->corebcr, cores);
+#endif
/* This is needed as a precautionary measure.
* If some code before this has accidentally released the secondary
* cores then the pre-bootloader code will trap them in a "wfe" unless
diff --git a/arch/arm/cpu/armv8/fsl-lsch3/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
similarity index 72%
rename from arch/arm/cpu/armv8/fsl-lsch3/soc.c
rename to arch/arm/cpu/armv8/fsl-layerscape/soc.c
index 2538001bca593fcb0ffc0de862463b2bbfc27ae3..637853d51f6ba092f63085a83bd8dd078d32241a 100644
--- a/arch/arm/cpu/armv8/fsl-lsch3/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -1,19 +1,18 @@
/*
- * Copyright 2015 Freescale Semiconductor
+ * Copyright 2014-2015 Freescale Semiconductor
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <fsl_ifc.h>
-#include <nand.h>
-#include <spl.h>
-#include <asm/arch-fsl-lsch3/soc.h>
+#include <asm/arch/soc.h>
#include <asm/io.h>
#include <asm/global_data.h>
DECLARE_GLOBAL_DATA_PTR;
+#ifdef CONFIG_LS2085A
static void erratum_a008751(void)
{
#ifdef CONFIG_SYS_FSL_ERRATUM_A008751
@@ -78,30 +77,27 @@ void fsl_lsch3_early_init_f(void)
erratum_a009203();
}
-#ifdef CONFIG_SPL_BUILD
-void board_init_f(ulong dummy)
+#elif defined(CONFIG_LS1043A)
+void fsl_lsch2_early_init_f(void)
{
- /* Clear global data */
- memset((void *)gd, 0, sizeof(gd_t));
+ struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
- arch_cpu_init();
- board_early_init_f();
- timer_init();
- env_init();
- gd->baudrate = getenv_ulong("baudrate", 10, CONFIG_BAUDRATE);
-
- serial_init();
- console_init_f();
- dram_init();
-
- /* Clear the BSS. */
- memset(__bss_start, 0, __bss_end - __bss_start);
+#ifdef CONFIG_FSL_IFC
+ init_early_memctl_regs(); /* tighten IFC timing */
+#endif
- board_init_r(NULL, 0);
+ /*
+ * Enable snoop requests and DVM message requests for
+ * Slave insterface S4 (A53 core cluster)
+ */
+ out_le32(&cci->slave[4].snoop_ctrl,
+ CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN);
}
+#endif
-u32 spl_boot_device(void)
+#ifdef CONFIG_BOARD_LATE_INIT
+int board_late_init(void)
{
- return BOOT_DEVICE_NAND;
+ return 0;
}
#endif
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/spl.c b/arch/arm/cpu/armv8/fsl-layerscape/spl.c
new file mode 100644
index 0000000000000000000000000000000000000000..ba551aaa6e89ddfc048fdddab3ff93115797af17
--- /dev/null
+++ b/arch/arm/cpu/armv8/fsl-layerscape/spl.c
@@ -0,0 +1,79 @@
+/*
+ * Copyright 2014-2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <spl.h>
+#include <asm/io.h>
+#include <fsl_ifc.h>
+#include <fsl_csu.h>
+#include <i2c.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+u32 spl_boot_device(void)
+{
+#ifdef CONFIG_SPL_MMC_SUPPORT
+ return BOOT_DEVICE_MMC1;
+#endif
+#ifdef CONFIG_SPL_NAND_SUPPORT
+ return BOOT_DEVICE_NAND;
+#endif
+ return 0;
+}
+
+u32 spl_boot_mode(void)
+{
+ switch (spl_boot_device()) {
+ case BOOT_DEVICE_MMC1:
+#ifdef CONFIG_SPL_FAT_SUPPORT
+ return MMCSD_MODE_FAT;
+#else
+ return MMCSD_MODE_RAW;
+#endif
+ case BOOT_DEVICE_NAND:
+ return 0;
+ default:
+ puts("spl: error: unsupported device\n");
+ hang();
+ }
+}
+
+#ifdef CONFIG_SPL_BUILD
+void board_init_f(ulong dummy)
+{
+ /* Set global data pointer */
+ gd = &gdata;
+ /* Clear global data */
+ memset((void *)gd, 0, sizeof(gd_t));
+#ifdef CONFIG_LS2085A
+ arch_cpu_init();
+#endif
+#ifdef CONFIG_FSL_IFC
+ init_early_memctl_regs();
+#endif
+ board_early_init_f();
+ timer_init();
+#ifdef CONFIG_LS2085A
+ env_init();
+#endif
+ get_clocks();
+
+ preloader_console_init();
+
+#ifdef CONFIG_SPL_I2C_SUPPORT
+ i2c_init_all();
+#endif
+ dram_init();
+
+ /* Clear the BSS */
+ memset(__bss_start, 0, __bss_end - __bss_start);
+
+#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
+ enable_layerscape_ns_access();
+#endif
+ board_init_r(NULL, 0);
+}
+#endif
diff --git a/arch/arm/cpu/armv8/fsl-lsch3/Makefile b/arch/arm/cpu/armv8/fsl-lsch3/Makefile
deleted file mode 100644
index 9f7815bd523bdc266423b4ff32a8d8d57e7b1b5a..0000000000000000000000000000000000000000
--- a/arch/arm/cpu/armv8/fsl-lsch3/Makefile
+++ /dev/null
@@ -1,13 +0,0 @@
-#
-# Copyright 2014, Freescale Semiconductor
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y += cpu.o
-obj-y += lowlevel.o
-obj-y += soc.o
-obj-y += speed.o
-obj-$(CONFIG_SYS_HAS_SERDES) += fsl_lsch3_serdes.o ls2085a_serdes.o
-obj-$(CONFIG_MP) += mp.o
-obj-$(CONFIG_OF_LIBFDT) += fdt.o
diff --git a/arch/arm/cpu/armv8/fsl-lsch3/speed.h b/arch/arm/cpu/armv8/fsl-lsch3/speed.h
deleted file mode 100644
index 15af5b9f91847029c554d5b88d861fcc4faa3b2f..0000000000000000000000000000000000000000
--- a/arch/arm/cpu/armv8/fsl-lsch3/speed.h
+++ /dev/null
@@ -1,7 +0,0 @@
-/*
- * Copyright 2014, Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-void get_sys_info(struct sys_info *sys_info);
diff --git a/arch/arm/include/asm/arch-fsl-lsch3/clock.h b/arch/arm/include/asm/arch-fsl-layerscape/clock.h
similarity index 56%
rename from arch/arm/include/asm/arch-fsl-lsch3/clock.h
rename to arch/arm/include/asm/arch-fsl-layerscape/clock.h
index 62bc53c2fec5ccea4ce8928806963327e570777d..69359135d59d11ccd4018b5ea1a656ac69927d8b 100644
--- a/arch/arm/include/asm/arch-fsl-lsch3/clock.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/clock.h
@@ -1,12 +1,12 @@
/*
- * Copyright 2014 Freescale Semiconductor, Inc.
+ * Copyright 2015 Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*
*/
-#ifndef __ASM_ARCH_FSL_LSCH3_CLOCK_H_
-#define __ASM_ARCH_FSL_LSCH3_CLOCK_H_
+#ifndef __ASM_ARCH_FSL_LAYERSCAPE_CLOCK_H_
+#define __ASM_ARCH_FSL_LAYERSCAPE_CLOCK_H_
#include <common.h>
@@ -21,4 +21,4 @@ enum mxc_clock {
unsigned int mxc_get_clock(enum mxc_clock clk);
-#endif /* __ASM_ARCH_FSL_LSCH3_CLOCK_H_ */
+#endif /* __ASM_ARCH_FSL_LAYERSCAPE_CLOCK_H_ */
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h
new file mode 100644
index 0000000000000000000000000000000000000000..87bb937582983a7c39282d6f5244a530d03452ca
--- /dev/null
+++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h
@@ -0,0 +1,143 @@
+/*
+ * Copyright 2015, Freescale Semiconductor
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _ASM_ARMV8_FSL_LAYERSCAPE_CONFIG_H_
+#define _ASM_ARMV8_FSL_LAYERSCAPE_CONFIG_H_
+
+#include <fsl_ddrc_version.h>
+
+#ifdef CONFIG_SYS_FSL_DDR4
+#define CONFIG_SYS_FSL_DDRC_GEN4
+#else
+#define CONFIG_SYS_FSL_DDRC_ARM_GEN3 /* Enable Freescale ARM DDR3 driver */
+#endif
+#define CONFIG_SYS_FSL_DDR /* Freescale DDR driver */
+#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0
+
+#if defined(CONFIG_LS2085A)
+#define CONFIG_MAX_CPUS 16
+#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
+#define CONFIG_NUM_DDR_CONTROLLERS 3
+#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4, 4 }
+#define SRDS_MAX_LANES 8
+#define CONFIG_SYS_FSL_SRDS_1
+#define CONFIG_SYS_FSL_SRDS_2
+#define CONFIG_SYS_PAGE_SIZE 0x10000
+#define CONFIG_SYS_CACHELINE_SIZE 64
+#ifndef L1_CACHE_BYTES
+#define L1_CACHE_SHIFT 6
+#define L1_CACHE_BYTES BIT(L1_CACHE_SHIFT)
+#endif
+
+#define CONFIG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */
+#define CONFIG_SYS_FSL_OCRAM_SIZE 0x00200000 /* 2M */
+
+/* DDR */
+#define CONFIG_SYS_FSL_DDR_LE
+#define CONFIG_SYS_LS2_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
+#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_LS2_DDR_BLOCK1_SIZE
+
+#define CONFIG_SYS_FSL_CCSR_GUR_LE
+#define CONFIG_SYS_FSL_CCSR_SCFG_LE
+#define CONFIG_SYS_FSL_ESDHC_LE
+#define CONFIG_SYS_FSL_IFC_LE
+
+#define CONFIG_SYS_MEMAC_LITTLE_ENDIAN
+
+/* Generic Interrupt Controller Definitions */
+#define GICD_BASE 0x06000000
+#define GICR_BASE 0x06100000
+
+/* SMMU Defintions */
+#define SMMU_BASE 0x05000000 /* GR0 Base */
+
+/* Cache Coherent Interconnect */
+#define CCI_MN_BASE 0x04000000
+#define CCI_MN_RNF_NODEID_LIST 0x180
+#define CCI_MN_DVM_DOMAIN_CTL 0x200
+#define CCI_MN_DVM_DOMAIN_CTL_SET 0x210
+
+#define CCI_RN_I_0_BASE (CCI_MN_BASE + 0x800000)
+#define CCI_RN_I_2_BASE (CCI_MN_BASE + 0x820000)
+#define CCI_RN_I_6_BASE (CCI_MN_BASE + 0x860000)
+#define CCI_RN_I_12_BASE (CCI_MN_BASE + 0x8C0000)
+#define CCI_RN_I_16_BASE (CCI_MN_BASE + 0x900000)
+#define CCI_RN_I_20_BASE (CCI_MN_BASE + 0x940000)
+
+#define CCI_S0_QOS_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x10)
+#define CCI_S1_QOS_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x110)
+#define CCI_S2_QOS_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x210)
+
+/* TZ Protection Controller Definitions */
+#define TZPC_BASE 0x02200000
+#define TZPCR0SIZE_BASE (TZPC_BASE)
+#define TZPCDECPROT_0_STAT_BASE (TZPC_BASE + 0x800)
+#define TZPCDECPROT_0_SET_BASE (TZPC_BASE + 0x804)
+#define TZPCDECPROT_0_CLR_BASE (TZPC_BASE + 0x808)
+#define TZPCDECPROT_1_STAT_BASE (TZPC_BASE + 0x80C)
+#define TZPCDECPROT_1_SET_BASE (TZPC_BASE + 0x810)
+#define TZPCDECPROT_1_CLR_BASE (TZPC_BASE + 0x814)
+#define TZPCDECPROT_2_STAT_BASE (TZPC_BASE + 0x818)
+#define TZPCDECPROT_2_SET_BASE (TZPC_BASE + 0x81C)
+#define TZPCDECPROT_2_CLR_BASE (TZPC_BASE + 0x820)
+
+#define CONFIG_SYS_FSL_ERRATUM_A008336
+#define CONFIG_SYS_FSL_ERRATUM_A008511
+#define CONFIG_SYS_FSL_ERRATUM_A008514
+#define CONFIG_SYS_FSL_ERRATUM_A008585
+#define CONFIG_SYS_FSL_ERRATUM_A008751
+#elif defined(CONFIG_LS1043A)
+#define CONFIG_MAX_CPUS 4
+#define CONFIG_SYS_CACHELINE_SIZE 64
+#define CONFIG_SYS_FMAN_V3
+#define CONFIG_SYS_NUM_FMAN 1
+#define CONFIG_SYS_NUM_FM1_DTSEC 7
+#define CONFIG_SYS_NUM_FM1_10GEC 1
+#define CONFIG_SYS_FSL_IFC_BANK_COUNT 4
+#define CONFIG_NUM_DDR_CONTROLLERS 1
+#define CONFIG_SYS_CCSRBAR_DEFAULT 0x01000000
+#define CONFIG_SYS_FSL_SEC_COMPAT 5
+#define CONFIG_SYS_FSL_OCRAM_BASE 0x10000000 /* initial RAM */
+#define CONFIG_SYS_FSL_OCRAM_SIZE 0x200000 /* 2 MiB */
+#define CONFIG_SYS_FSL_DDR_BE
+#define CONFIG_SYS_LS1_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
+#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_LS1_DDR_BLOCK1_SIZE
+
+#define CONFIG_SYS_FSL_CCSR_GUR_BE
+#define CONFIG_SYS_FSL_CCSR_SCFG_BE
+#define CONFIG_SYS_FSL_IFC_BE
+#define CONFIG_SYS_FSL_ESDHC_BE
+#define CONFIG_SYS_FSL_WDOG_BE
+#define CONFIG_SYS_FSL_DSPI_BE
+#define CONFIG_SYS_FSL_QSPI_BE
+
+#define QE_MURAM_SIZE 0x6000UL
+#define MAX_QE_RISC 1
+#define QE_NUM_OF_SNUM 28
+
+#define SRDS_MAX_LANES 4
+#define CONFIG_SYS_FSL_SRDS_1
+#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
+
+#define CONFIG_SYS_FSL_SFP_VER_3_2
+#define CONFIG_SYS_FSL_SNVS_LE
+#define CONFIG_SYS_FSL_SEC_LE
+#define CONFIG_SYS_FSL_SFP_BE
+#define CONFIG_SYS_FSL_SRK_LE
+#define CONFIG_KEY_REVOCATION
+
+/* SMMU Defintions */
+#define SMMU_BASE 0x09000000
+
+/* Generic Interrupt Controller Definitions */
+#define GICD_BASE 0x01401000
+#define GICC_BASE 0x01402000
+
+#else
+#error SoC not defined
+#endif
+
+#endif /* _ASM_ARMV8_FSL_LAYERSCAPE_CONFIG_H_ */
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
new file mode 100644
index 0000000000000000000000000000000000000000..29039963f129da2f1ee95737926cc902f1a51d99
--- /dev/null
+++ b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
@@ -0,0 +1,229 @@
+/*
+ * Copyright 2014-2015, Freescale Semiconductor
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _FSL_LAYERSCAPE_CPU_H
+#define _FSL_LAYERSCAPE_CPU_H
+
+static struct cpu_type cpu_type_list[] = {
+ CPU_TYPE_ENTRY(LS2085, LS2085, 8),
+ CPU_TYPE_ENTRY(LS2080, LS2080, 8),
+ CPU_TYPE_ENTRY(LS2045, LS2045, 4),
+ CPU_TYPE_ENTRY(LS1043, LS1043, 4),
+};
+
+#ifndef CONFIG_SYS_DCACHE_OFF
+
+#define SECTION_SHIFT_L0 39UL
+#define SECTION_SHIFT_L1 30UL
+#define SECTION_SHIFT_L2 21UL
+#define BLOCK_SIZE_L0 0x8000000000
+#define BLOCK_SIZE_L1 0x40000000
+#define BLOCK_SIZE_L2 0x200000
+#define NUM_OF_ENTRY 512
+#define TCR_EL2_PS_40BIT (2 << 16)
+
+#define LAYERSCAPE_VA_BITS (40)
+#define LAYERSCAPE_TCR (TCR_TG0_4K | \
+ TCR_EL2_PS_40BIT | \
+ TCR_SHARED_NON | \
+ TCR_ORGN_NC | \
+ TCR_IRGN_NC | \
+ TCR_T0SZ(LAYERSCAPE_VA_BITS))
+#define LAYERSCAPE_TCR_FINAL (TCR_TG0_4K | \
+ TCR_EL2_PS_40BIT | \
+ TCR_SHARED_OUTER | \
+ TCR_ORGN_WBWA | \
+ TCR_IRGN_WBWA | \
+ TCR_T0SZ(LAYERSCAPE_VA_BITS))
+
+#ifdef CONFIG_FSL_LSCH3
+#define CONFIG_SYS_FSL_CCSR_BASE 0x00000000
+#define CONFIG_SYS_FSL_CCSR_SIZE 0x10000000
+#define CONFIG_SYS_FSL_QSPI_BASE1 0x20000000
+#define CONFIG_SYS_FSL_QSPI_SIZE1 0x10000000
+#define CONFIG_SYS_FSL_IFC_BASE1 0x30000000
+#define CONFIG_SYS_FSL_IFC_SIZE1 0x10000000
+#define CONFIG_SYS_FSL_IFC_SIZE1_1 0x400000
+#define CONFIG_SYS_FSL_DRAM_BASE1 0x80000000
+#define CONFIG_SYS_FSL_DRAM_SIZE1 0x80000000
+#define CONFIG_SYS_FSL_QSPI_BASE2 0x400000000
+#define CONFIG_SYS_FSL_QSPI_SIZE2 0x100000000
+#define CONFIG_SYS_FSL_IFC_BASE2 0x500000000
+#define CONFIG_SYS_FSL_IFC_SIZE2 0x100000000
+#define CONFIG_SYS_FSL_DCSR_BASE 0x700000000
+#define CONFIG_SYS_FSL_DCSR_SIZE 0x40000000
+#define CONFIG_SYS_FSL_MC_BASE 0x80c000000
+#define CONFIG_SYS_FSL_MC_SIZE 0x4000000
+#define CONFIG_SYS_FSL_NI_BASE 0x810000000
+#define CONFIG_SYS_FSL_NI_SIZE 0x8000000
+#define CONFIG_SYS_FSL_QBMAN_BASE 0x818000000
+#define CONFIG_SYS_FSL_QBMAN_SIZE 0x8000000
+#define CONFIG_SYS_FSL_QBMAN_SIZE_1 0x4000000
+#define CONFIG_SYS_PCIE1_PHYS_SIZE 0x200000000
+#define CONFIG_SYS_PCIE2_PHYS_SIZE 0x200000000
+#define CONFIG_SYS_PCIE3_PHYS_SIZE 0x200000000
+#define CONFIG_SYS_PCIE4_PHYS_SIZE 0x200000000
+#define CONFIG_SYS_FSL_WRIOP1_BASE 0x4300000000
+#define CONFIG_SYS_FSL_WRIOP1_SIZE 0x100000000
+#define CONFIG_SYS_FSL_AIOP1_BASE 0x4b00000000
+#define CONFIG_SYS_FSL_AIOP1_SIZE 0x100000000
+#define CONFIG_SYS_FSL_PEBUF_BASE 0x4c00000000
+#define CONFIG_SYS_FSL_PEBUF_SIZE 0x400000000
+#define CONFIG_SYS_FSL_DRAM_BASE2 0x8080000000
+#define CONFIG_SYS_FSL_DRAM_SIZE2 0x7F80000000
+#elif defined(CONFIG_FSL_LSCH2)
+#define CONFIG_SYS_FSL_BOOTROM_BASE 0x0
+#define CONFIG_SYS_FSL_BOOTROM_SIZE 0x1000000
+#define CONFIG_SYS_FSL_CCSR_BASE 0x1000000
+#define CONFIG_SYS_FSL_CCSR_SIZE 0xf000000
+#define CONFIG_SYS_FSL_DCSR_BASE 0x20000000
+#define CONFIG_SYS_FSL_DCSR_SIZE 0x4000000
+#define CONFIG_SYS_FSL_QSPI_BASE 0x40000000
+#define CONFIG_SYS_FSL_QSPI_SIZE 0x20000000
+#define CONFIG_SYS_FSL_IFC_BASE 0x60000000
+#define CONFIG_SYS_FSL_IFC_SIZE 0x20000000
+#define CONFIG_SYS_FSL_DRAM_BASE1 0x80000000
+#define CONFIG_SYS_FSL_DRAM_SIZE1 0x80000000
+#define CONFIG_SYS_FSL_QBMAN_BASE 0x500000000
+#define CONFIG_SYS_FSL_QBMAN_SIZE 0x10000000
+#define CONFIG_SYS_FSL_DRAM_BASE2 0x880000000
+#define CONFIG_SYS_FSL_DRAM_SIZE2 0x780000000 /* 30GB */
+#define CONFIG_SYS_PCIE1_PHYS_SIZE 0x800000000
+#define CONFIG_SYS_PCIE2_PHYS_SIZE 0x800000000
+#define CONFIG_SYS_PCIE3_PHYS_SIZE 0x800000000
+#define CONFIG_SYS_FSL_DRAM_BASE3 0x8800000000
+#define CONFIG_SYS_FSL_DRAM_SIZE3 0x7800000000 /* 480GB */
+#endif
+
+struct sys_mmu_table {
+ u64 virt_addr;
+ u64 phys_addr;
+ u64 size;
+ u64 memory_type;
+ u64 share;
+};
+
+struct table_info {
+ u64 *ptr;
+ u64 table_base;
+ u64 entry_size;
+};
+
+static const struct sys_mmu_table early_mmu_table[] = {
+#ifdef CONFIG_FSL_LSCH3
+ { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
+ CONFIG_SYS_FSL_CCSR_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
+ { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
+ CONFIG_SYS_FSL_OCRAM_SIZE, MT_NORMAL, PMD_SECT_NON_SHARE },
+ /* For IFC Region #1, only the first 4MB is cache-enabled */
+ { CONFIG_SYS_FSL_IFC_BASE1, CONFIG_SYS_FSL_IFC_BASE1,
+ CONFIG_SYS_FSL_IFC_SIZE1_1, MT_NORMAL, PMD_SECT_NON_SHARE },
+ { CONFIG_SYS_FSL_IFC_BASE1 + CONFIG_SYS_FSL_IFC_SIZE1_1,
+ CONFIG_SYS_FSL_IFC_BASE1 + CONFIG_SYS_FSL_IFC_SIZE1_1,
+ CONFIG_SYS_FSL_IFC_SIZE1 - CONFIG_SYS_FSL_IFC_SIZE1_1,
+ MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
+ { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FSL_IFC_BASE1,
+ CONFIG_SYS_FSL_IFC_SIZE1, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
+ { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
+ CONFIG_SYS_FSL_DRAM_SIZE1, MT_NORMAL, PMD_SECT_OUTER_SHARE },
+ { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
+ CONFIG_SYS_FSL_DCSR_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
+ { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
+ CONFIG_SYS_FSL_DRAM_SIZE2, MT_NORMAL, PMD_SECT_OUTER_SHARE },
+#elif defined(CONFIG_FSL_LSCH2)
+ { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
+ CONFIG_SYS_FSL_CCSR_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
+ { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
+ CONFIG_SYS_FSL_OCRAM_SIZE, MT_NORMAL, PMD_SECT_NON_SHARE },
+ { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
+ CONFIG_SYS_FSL_DCSR_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
+ { CONFIG_SYS_FSL_IFC_BASE, CONFIG_SYS_FSL_IFC_BASE,
+ CONFIG_SYS_FSL_IFC_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
+ { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
+ CONFIG_SYS_FSL_DRAM_SIZE1, MT_NORMAL, PMD_SECT_OUTER_SHARE },
+ { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
+ CONFIG_SYS_FSL_DRAM_SIZE2, MT_NORMAL, PMD_SECT_OUTER_SHARE },
+#endif
+};
+
+static const struct sys_mmu_table final_mmu_table[] = {
+#ifdef CONFIG_FSL_LSCH3
+ { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
+ CONFIG_SYS_FSL_CCSR_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
+ { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
+ CONFIG_SYS_FSL_OCRAM_SIZE, MT_NORMAL, PMD_SECT_NON_SHARE },
+ { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
+ CONFIG_SYS_FSL_DRAM_SIZE1, MT_NORMAL, PMD_SECT_OUTER_SHARE },
+ { CONFIG_SYS_FSL_QSPI_BASE2, CONFIG_SYS_FSL_QSPI_BASE2,
+ CONFIG_SYS_FSL_QSPI_SIZE2, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
+ { CONFIG_SYS_FSL_IFC_BASE2, CONFIG_SYS_FSL_IFC_BASE2,
+ CONFIG_SYS_FSL_IFC_SIZE2, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
+ { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
+ CONFIG_SYS_FSL_DCSR_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
+ { CONFIG_SYS_FSL_MC_BASE, CONFIG_SYS_FSL_MC_BASE,
+ CONFIG_SYS_FSL_MC_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
+ { CONFIG_SYS_FSL_NI_BASE, CONFIG_SYS_FSL_NI_BASE,
+ CONFIG_SYS_FSL_NI_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
+ /* For QBMAN portal, only the first 64MB is cache-enabled */
+ { CONFIG_SYS_FSL_QBMAN_BASE, CONFIG_SYS_FSL_QBMAN_BASE,
+ CONFIG_SYS_FSL_QBMAN_SIZE_1, MT_NORMAL, PMD_SECT_NON_SHARE },
+ { CONFIG_SYS_FSL_QBMAN_BASE + CONFIG_SYS_FSL_QBMAN_SIZE_1,
+ CONFIG_SYS_FSL_QBMAN_BASE + CONFIG_SYS_FSL_QBMAN_SIZE_1,
+ CONFIG_SYS_FSL_QBMAN_SIZE - CONFIG_SYS_FSL_QBMAN_SIZE_1,
+ MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
+ { CONFIG_SYS_PCIE1_PHYS_ADDR, CONFIG_SYS_PCIE1_PHYS_ADDR,
+ CONFIG_SYS_PCIE1_PHYS_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
+ { CONFIG_SYS_PCIE2_PHYS_ADDR, CONFIG_SYS_PCIE2_PHYS_ADDR,
+ CONFIG_SYS_PCIE2_PHYS_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
+ { CONFIG_SYS_PCIE3_PHYS_ADDR, CONFIG_SYS_PCIE3_PHYS_ADDR,
+ CONFIG_SYS_PCIE3_PHYS_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
+#ifdef CONFIG_LS2085A
+ { CONFIG_SYS_PCIE4_PHYS_ADDR, CONFIG_SYS_PCIE4_PHYS_ADDR,
+ CONFIG_SYS_PCIE4_PHYS_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
+#endif
+ { CONFIG_SYS_FSL_WRIOP1_BASE, CONFIG_SYS_FSL_WRIOP1_BASE,
+ CONFIG_SYS_FSL_WRIOP1_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
+ { CONFIG_SYS_FSL_AIOP1_BASE, CONFIG_SYS_FSL_AIOP1_BASE,
+ CONFIG_SYS_FSL_AIOP1_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
+ { CONFIG_SYS_FSL_PEBUF_BASE, CONFIG_SYS_FSL_PEBUF_BASE,
+ CONFIG_SYS_FSL_PEBUF_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
+ { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
+ CONFIG_SYS_FSL_DRAM_SIZE2, MT_NORMAL, PMD_SECT_OUTER_SHARE },
+#elif defined(CONFIG_FSL_LSCH2)
+ { CONFIG_SYS_FSL_BOOTROM_BASE, CONFIG_SYS_FSL_BOOTROM_BASE,
+ CONFIG_SYS_FSL_BOOTROM_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
+ { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
+ CONFIG_SYS_FSL_CCSR_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
+ { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
+ CONFIG_SYS_FSL_OCRAM_SIZE, MT_NORMAL, PMD_SECT_NON_SHARE },
+ { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
+ CONFIG_SYS_FSL_DCSR_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
+ { CONFIG_SYS_FSL_QSPI_BASE, CONFIG_SYS_FSL_QSPI_BASE,
+ CONFIG_SYS_FSL_QSPI_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
+ { CONFIG_SYS_FSL_IFC_BASE, CONFIG_SYS_FSL_IFC_BASE,
+ CONFIG_SYS_FSL_IFC_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
+ { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
+ CONFIG_SYS_FSL_DRAM_SIZE1, MT_NORMAL,
+ PMD_SECT_OUTER_SHARE | PMD_SECT_NS },
+ { CONFIG_SYS_FSL_QBMAN_BASE, CONFIG_SYS_FSL_QBMAN_BASE,
+ CONFIG_SYS_FSL_QBMAN_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
+ { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
+ CONFIG_SYS_FSL_DRAM_SIZE2, MT_NORMAL, PMD_SECT_OUTER_SHARE },
+ { CONFIG_SYS_PCIE1_PHYS_ADDR, CONFIG_SYS_PCIE1_PHYS_ADDR,
+ CONFIG_SYS_PCIE1_PHYS_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
+ { CONFIG_SYS_PCIE2_PHYS_ADDR, CONFIG_SYS_PCIE2_PHYS_ADDR,
+ CONFIG_SYS_PCIE2_PHYS_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
+ { CONFIG_SYS_PCIE3_PHYS_ADDR, CONFIG_SYS_PCIE3_PHYS_ADDR,
+ CONFIG_SYS_PCIE3_PHYS_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
+ { CONFIG_SYS_FSL_DRAM_BASE3, CONFIG_SYS_FSL_DRAM_BASE3,
+ CONFIG_SYS_FSL_DRAM_SIZE3, MT_NORMAL, PMD_SECT_OUTER_SHARE },
+#endif
+};
+#endif
+
+int fsl_qoriq_core_to_cluster(unsigned int core);
+u32 cpu_mask(void);
+#endif /* _FSL_LAYERSCAPE_CPU_H */
diff --git a/arch/arm/include/asm/arch-fsl-lsch3/fdt.h b/arch/arm/include/asm/arch-fsl-layerscape/fdt.h
similarity index 71%
rename from arch/arm/include/asm/arch-fsl-lsch3/fdt.h
rename to arch/arm/include/asm/arch-fsl-layerscape/fdt.h
index 21d20fba21dd3f58308f980bf9db5c1a68a31497..4da73ab142477a7a6d4bc425ef47c28f73bf2e97 100644
--- a/arch/arm/include/asm/arch-fsl-lsch3/fdt.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/fdt.h
@@ -4,7 +4,11 @@
* SPDX-License-Identifier: GPL-2.0+
*/
+#ifndef _ASM_ARMV8_FSL_LAYERSCAPE_FDT_H_
+#define _ASM_ARMV8_FSL_LAYERSCAPE_FDT_H_
+
void alloc_stream_ids(int start_id, int count, u32 *stream_ids, int max_cnt);
void append_mmu_masters(void *blob, const char *smmu_path,
const char *master_name, u32 *stream_ids, int count);
void fdt_fixup_smmu_pcie(void *blob);
+#endif /* _ASM_ARMV8_FSL_LAYERSCAPE_FDT_H_ */
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h b/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h
new file mode 100644
index 0000000000000000000000000000000000000000..e1043b5a5fd4013b0a44328325ff67f62e8aa7f5
--- /dev/null
+++ b/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h
@@ -0,0 +1,157 @@
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __FSL_SERDES_H__
+#define __FSL_SERDES_H__
+
+#include <config.h>
+
+#if defined(CONFIG_LS2085A)
+enum srds_prtcl {
+ NONE = 0,
+ PCIE1,
+ PCIE2,
+ PCIE3,
+ PCIE4,
+ SATA1,
+ SATA2,
+ XAUI1,
+ XAUI2,
+ XFI1,
+ XFI2,
+ XFI3,
+ XFI4,
+ XFI5,
+ XFI6,
+ XFI7,
+ XFI8,
+ SGMII1,
+ SGMII2,
+ SGMII3,
+ SGMII4,
+ SGMII5,
+ SGMII6,
+ SGMII7,
+ SGMII8,
+ SGMII9,
+ SGMII10,
+ SGMII11,
+ SGMII12,
+ SGMII13,
+ SGMII14,
+ SGMII15,
+ SGMII16,
+ QSGMII_A, /* A indicates MACs 1-4 */
+ QSGMII_B, /* B indicates MACs 5-8 */
+ QSGMII_C, /* C indicates MACs 9-12 */
+ QSGMII_D, /* D indicates MACs 12-16 */
+ SERDES_PRCTL_COUNT
+};
+
+enum srds {
+ FSL_SRDS_1 = 0,
+ FSL_SRDS_2 = 1,
+};
+#elif defined(CONFIG_LS1043A)
+enum srds_prtcl {
+ NONE = 0,
+ PCIE1,
+ PCIE2,
+ PCIE3,
+ PCIE4,
+ SATA1,
+ SATA2,
+ SRIO1,
+ SRIO2,
+ SGMII_FM1_DTSEC1,
+ SGMII_FM1_DTSEC2,
+ SGMII_FM1_DTSEC3,
+ SGMII_FM1_DTSEC4,
+ SGMII_FM1_DTSEC5,
+ SGMII_FM1_DTSEC6,
+ SGMII_FM1_DTSEC9,
+ SGMII_FM1_DTSEC10,
+ SGMII_FM2_DTSEC1,
+ SGMII_FM2_DTSEC2,
+ SGMII_FM2_DTSEC3,
+ SGMII_FM2_DTSEC4,
+ SGMII_FM2_DTSEC5,
+ SGMII_FM2_DTSEC6,
+ SGMII_FM2_DTSEC9,
+ SGMII_FM2_DTSEC10,
+ SGMII_TSEC1,
+ SGMII_TSEC2,
+ SGMII_TSEC3,
+ SGMII_TSEC4,
+ XAUI_FM1,
+ XAUI_FM2,
+ AURORA,
+ CPRI1,
+ CPRI2,
+ CPRI3,
+ CPRI4,
+ CPRI5,
+ CPRI6,
+ CPRI7,
+ CPRI8,
+ XAUI_FM1_MAC9,
+ XAUI_FM1_MAC10,
+ XAUI_FM2_MAC9,
+ XAUI_FM2_MAC10,
+ HIGIG_FM1_MAC9,
+ HIGIG_FM1_MAC10,
+ HIGIG_FM2_MAC9,
+ HIGIG_FM2_MAC10,
+ QSGMII_FM1_A, /* A indicates MACs 1,2,5,6 */
+ QSGMII_FM1_B, /* B indicates MACs 5,6,9,10 */
+ QSGMII_FM2_A,
+ QSGMII_FM2_B,
+ XFI_FM1_MAC1,
+ XFI_FM1_MAC2,
+ XFI_FM1_MAC9,
+ XFI_FM1_MAC10,
+ XFI_FM2_MAC9,
+ XFI_FM2_MAC10,
+ INTERLAKEN,
+ QSGMII_SW1_A, /* Indicates ports on L2 Switch */
+ QSGMII_SW1_B,
+ SGMII_2500_FM1_DTSEC1,
+ SGMII_2500_FM1_DTSEC2,
+ SGMII_2500_FM1_DTSEC3,
+ SGMII_2500_FM1_DTSEC4,
+ SGMII_2500_FM1_DTSEC5,
+ SGMII_2500_FM1_DTSEC6,
+ SGMII_2500_FM1_DTSEC9,
+ SGMII_2500_FM1_DTSEC10,
+ SGMII_2500_FM2_DTSEC1,
+ SGMII_2500_FM2_DTSEC2,
+ SGMII_2500_FM2_DTSEC3,
+ SGMII_2500_FM2_DTSEC4,
+ SGMII_2500_FM2_DTSEC5,
+ SGMII_2500_FM2_DTSEC6,
+ SGMII_2500_FM2_DTSEC9,
+ SGMII_2500_FM2_DTSEC10,
+ SERDES_PRCTL_COUNT
+};
+
+enum srds {
+ FSL_SRDS_1 = 0,
+};
+
+#endif
+
+int is_serdes_configured(enum srds_prtcl device);
+void fsl_serdes_init(void);
+int serdes_get_first_lane(u32 sd, enum srds_prtcl device);
+enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane);
+int is_serdes_prtcl_valid(int serdes, u32 prtcl);
+
+#ifdef CONFIG_LS1043A
+const char *serdes_clock_to_string(u32 clock);
+int get_serdes_protocol(void);
+#endif
+
+#endif /* __FSL_SERDES_H__ */
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
new file mode 100644
index 0000000000000000000000000000000000000000..d941437d63ca3250663d2cd058feb83151080001
--- /dev/null
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
@@ -0,0 +1,555 @@
+/*
+ * Copyright 2013-2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __ARCH_FSL_LSCH2_IMMAP_H__
+#define __ARCH_FSL_LSCH2_IMMAP_H__
+
+#include <fsl_immap.h>
+
+#define CONFIG_SYS_IMMR 0x01000000
+#define CONFIG_SYS_DCSRBAR 0x20000000
+#define CONFIG_SYS_DCSR_DCFG_ADDR (CONFIG_SYS_DCSRBAR + 0x00220000)
+
+#define CONFIG_SYS_FSL_DDR_ADDR (CONFIG_SYS_IMMR + 0x00080000)
+#define CONFIG_SYS_CCI400_ADDR (CONFIG_SYS_IMMR + 0x00180000)
+#define CONFIG_SYS_GIC400_ADDR (CONFIG_SYS_IMMR + 0x00400000)
+#define CONFIG_SYS_IFC_ADDR (CONFIG_SYS_IMMR + 0x00530000)
+#define CONFIG_SYS_FSL_ESDHC_ADDR (CONFIG_SYS_IMMR + 0x00560000)
+#define CONFIG_SYS_FSL_CSU_ADDR (CONFIG_SYS_IMMR + 0x00510000)
+#define CONFIG_SYS_FSL_GUTS_ADDR (CONFIG_SYS_IMMR + 0x00ee0000)
+#define CONFIG_SYS_FSL_RST_ADDR (CONFIG_SYS_IMMR + 0x00ee00b0)
+#define CONFIG_SYS_FSL_SCFG_ADDR (CONFIG_SYS_IMMR + 0x00570000)
+#define CONFIG_SYS_FSL_FMAN_ADDR (CONFIG_SYS_IMMR + 0x00a00000)
+#define CONFIG_SYS_FSL_SERDES_ADDR (CONFIG_SYS_IMMR + 0x00ea0000)
+#define CONFIG_SYS_FSL_DCFG_ADDR (CONFIG_SYS_IMMR + 0x00ee0000)
+#define CONFIG_SYS_FSL_CLK_ADDR (CONFIG_SYS_IMMR + 0x00ee1000)
+#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x011c0500)
+#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x011c0600)
+#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_IMMR + 0x011d0500)
+#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_IMMR + 0x011d0600)
+#define CONFIG_SYS_FSL_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x01f00000)
+#define CONFIG_SYS_FSL_XHCI_USB2_ADDR (CONFIG_SYS_IMMR + 0x02000000)
+#define CONFIG_SYS_FSL_XHCI_USB3_ADDR (CONFIG_SYS_IMMR + 0x02100000)
+#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_IMMR + 0x2400000)
+#define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_IMMR + 0x2500000)
+#define CONFIG_SYS_PCIE3_ADDR (CONFIG_SYS_IMMR + 0x2600000)
+#define CONFIG_SYS_FSL_SEC_ADDR (CONFIG_SYS_IMMR + 0x700000)
+#define CONFIG_SYS_FSL_JR0_ADDR (CONFIG_SYS_IMMR + 0x710000)
+#define CONFIG_SYS_SNVS_ADDR (CONFIG_SYS_IMMR + 0xe90000)
+#define CONFIG_SYS_SFP_ADDR (CONFIG_SYS_IMMR + 0xe80200)
+
+#define CONFIG_SYS_FSL_TIMER_ADDR 0x02b00000
+
+#define I2C1_BASE_ADDR (CONFIG_SYS_IMMR + 0x01180000)
+#define I2C2_BASE_ADDR (CONFIG_SYS_IMMR + 0x01190000)
+#define I2C3_BASE_ADDR (CONFIG_SYS_IMMR + 0x011a0000)
+#define I2C4_BASE_ADDR (CONFIG_SYS_IMMR + 0x011b0000)
+
+#define WDOG1_BASE_ADDR (CONFIG_SYS_IMMR + 0x01ad0000)
+
+#define QSPI0_BASE_ADDR (CONFIG_SYS_IMMR + 0x00550000)
+#define DSPI1_BASE_ADDR (CONFIG_SYS_IMMR + 0x01100000)
+
+#define LPUART_BASE (CONFIG_SYS_IMMR + 0x01950000)
+
+#define AHCI_BASE_ADDR (CONFIG_SYS_IMMR + 0x02200000)
+
+#define CONFIG_SYS_PCIE1_PHYS_ADDR 0x4000000000ULL
+#define CONFIG_SYS_PCIE2_PHYS_ADDR 0x4800000000ULL
+#define CONFIG_SYS_PCIE3_PHYS_ADDR 0x5000000000ULL
+
+/* TZ Address Space Controller Definitions */
+#define TZASC1_BASE 0x01100000 /* as per CCSR map. */
+#define TZASC2_BASE 0x01110000 /* as per CCSR map. */
+#define TZASC3_BASE 0x01120000 /* as per CCSR map. */
+#define TZASC4_BASE 0x01130000 /* as per CCSR map. */
+#define TZASC_BUILD_CONFIG_REG(x) ((TZASC1_BASE + (x * 0x10000)))
+#define TZASC_ACTION_REG(x) ((TZASC1_BASE + (x * 0x10000)) + 0x004)
+#define TZASC_GATE_KEEPER(x) ((TZASC1_BASE + (x * 0x10000)) + 0x008)
+#define TZASC_REGION_BASE_LOW_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x100)
+#define TZASC_REGION_BASE_HIGH_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x104)
+#define TZASC_REGION_TOP_LOW_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x108)
+#define TZASC_REGION_TOP_HIGH_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x10C)
+#define TZASC_REGION_ATTRIBUTES_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x110)
+#define TZASC_REGION_ID_ACCESS_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x114)
+
+#define TP_ITYP_AV 0x00000001 /* Initiator available */
+#define TP_ITYP_TYPE(x) (((x) & 0x6) >> 1) /* Initiator Type */
+#define TP_ITYP_TYPE_ARM 0x0
+#define TP_ITYP_TYPE_PPC 0x1 /* PowerPC */
+#define TP_ITYP_TYPE_OTHER 0x2 /* StarCore DSP */
+#define TP_ITYP_TYPE_HA 0x3 /* HW Accelerator */
+#define TP_ITYP_THDS(x) (((x) & 0x18) >> 3) /* # threads */
+#define TP_ITYP_VER(x) (((x) & 0xe0) >> 5) /* Initiator Version */
+#define TY_ITYP_VER_A7 0x1
+#define TY_ITYP_VER_A53 0x2
+#define TY_ITYP_VER_A57 0x3
+
+#define TP_CLUSTER_EOC 0xc0000000 /* end of clusters */
+#define TP_CLUSTER_INIT_MASK 0x0000003f /* initiator mask */
+#define TP_INIT_PER_CLUSTER 4
+
+/*
+ * Define default values for some CCSR macros to make header files cleaner*
+ *
+ * To completely disable CCSR relocation in a board header file, define
+ * CONFIG_SYS_CCSR_DO_NOT_RELOCATE. This will force CONFIG_SYS_CCSRBAR_PHYS
+ * to a value that is the same as CONFIG_SYS_CCSRBAR.
+ */
+
+#ifdef CONFIG_SYS_CCSRBAR_PHYS
+#error "Do not define CONFIG_SYS_CCSRBAR_PHYS directly. Use \
+CONFIG_SYS_CCSRBAR_PHYS_LOW and/or CONFIG_SYS_CCSRBAR_PHYS_HIGH instead."
+#endif
+
+#ifdef CONFIG_SYS_CCSR_DO_NOT_RELOCATE
+#undef CONFIG_SYS_CCSRBAR_PHYS_HIGH
+#undef CONFIG_SYS_CCSRBAR_PHYS_LOW
+#define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0
+#endif
+
+#ifndef CONFIG_SYS_CCSRBAR
+#define CONFIG_SYS_CCSRBAR CONFIG_SYS_CCSRBAR_DEFAULT
+#endif
+
+#ifndef CONFIG_SYS_CCSRBAR_PHYS_HIGH
+#define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0
+#endif
+
+#ifndef CONFIG_SYS_CCSRBAR_PHYS_LOW
+#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR_DEFAULT
+#endif
+
+#define CONFIG_SYS_CCSRBAR_PHYS ((CONFIG_SYS_CCSRBAR_PHYS_HIGH * 1ull) << 32 | \
+ CONFIG_SYS_CCSRBAR_PHYS_LOW)
+
+struct sys_info {
+ unsigned long freq_processor[CONFIG_MAX_CPUS];
+ unsigned long freq_systembus;
+ unsigned long freq_ddrbus;
+ unsigned long freq_localbus;
+ unsigned long freq_sdhc;
+#ifdef CONFIG_SYS_DPAA_FMAN
+ unsigned long freq_fman[CONFIG_SYS_NUM_FMAN];
+#endif
+ unsigned long freq_qman;
+};
+
+#define CONFIG_SYS_FSL_FM1_OFFSET 0xa00000
+#define CONFIG_SYS_FSL_FM1_RX0_1G_OFFSET 0xa88000
+#define CONFIG_SYS_FSL_FM1_RX1_1G_OFFSET 0xa89000
+#define CONFIG_SYS_FSL_FM1_RX2_1G_OFFSET 0xa8a000
+#define CONFIG_SYS_FSL_FM1_RX3_1G_OFFSET 0xa8b000
+#define CONFIG_SYS_FSL_FM1_RX4_1G_OFFSET 0xa8c000
+#define CONFIG_SYS_FSL_FM1_RX5_1G_OFFSET 0xa8d000
+
+#define CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET 0xae0000
+#define CONFIG_SYS_FSL_FM1_ADDR \
+ (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_FM1_OFFSET)
+#define CONFIG_SYS_FSL_FM1_DTSEC1_ADDR \
+ (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET)
+
+/* Device Configuration and Pin Control */
+struct ccsr_gur {
+ u32 porsr1; /* POR status 1 */
+#define FSL_CHASSIS2_CCSR_PORSR1_RCW_MASK 0xFF800000
+ u32 porsr2; /* POR status 2 */
+ u8 res_008[0x20-0x8];
+ u32 gpporcr1; /* General-purpose POR configuration */
+ u32 gpporcr2;
+#define FSL_CHASSIS2_DCFG_FUSESR_VID_SHIFT 25
+#define FSL_CHASSIS2_DCFG_FUSESR_VID_MASK 0x1F
+#define FSL_CHASSIS2_DCFG_FUSESR_ALTVID_SHIFT 20
+#define FSL_CHASSIS2_DCFG_FUSESR_ALTVID_MASK 0x1F
+ u32 dcfg_fusesr; /* Fuse status register */
+ u8 res_02c[0x70-0x2c];
+ u32 devdisr; /* Device disable control */
+#define FSL_CHASSIS2_DEVDISR2_DTSEC1_1 0x80000000
+#define FSL_CHASSIS2_DEVDISR2_DTSEC1_2 0x40000000
+#define FSL_CHASSIS2_DEVDISR2_DTSEC1_3 0x20000000
+#define FSL_CHASSIS2_DEVDISR2_DTSEC1_4 0x10000000
+#define FSL_CHASSIS2_DEVDISR2_DTSEC1_5 0x08000000
+#define FSL_CHASSIS2_DEVDISR2_DTSEC1_6 0x04000000
+#define FSL_CHASSIS2_DEVDISR2_DTSEC1_9 0x00800000
+#define FSL_CHASSIS2_DEVDISR2_DTSEC1_10 0x00400000
+#define FSL_CHASSIS2_DEVDISR2_10GEC1_1 0x00800000
+#define FSL_CHASSIS2_DEVDISR2_10GEC1_2 0x00400000
+#define FSL_CHASSIS2_DEVDISR2_10GEC1_3 0x80000000
+#define FSL_CHASSIS2_DEVDISR2_10GEC1_4 0x40000000
+ u32 devdisr2; /* Device disable control 2 */
+ u32 devdisr3; /* Device disable control 3 */
+ u32 devdisr4; /* Device disable control 4 */
+ u32 devdisr5; /* Device disable control 5 */
+ u32 devdisr6; /* Device disable control 6 */
+ u32 devdisr7; /* Device disable control 7 */
+ u8 res_08c[0x94-0x8c];
+ u32 coredisru; /* uppper portion for support of 64 cores */
+ u32 coredisrl; /* lower portion for support of 64 cores */
+ u8 res_09c[0xa0-0x9c];
+ u32 pvr; /* Processor version */
+ u32 svr; /* System version */
+ u32 mvr; /* Manufacturing version */
+ u8 res_0ac[0xb0-0xac];
+ u32 rstcr; /* Reset control */
+ u32 rstrqpblsr; /* Reset request preboot loader status */
+ u8 res_0b8[0xc0-0xb8];
+ u32 rstrqmr1; /* Reset request mask */
+ u8 res_0c4[0xc8-0xc4];
+ u32 rstrqsr1; /* Reset request status */
+ u8 res_0cc[0xd4-0xcc];
+ u32 rstrqwdtmrl; /* Reset request WDT mask */
+ u8 res_0d8[0xdc-0xd8];
+ u32 rstrqwdtsrl; /* Reset request WDT status */
+ u8 res_0e0[0xe4-0xe0];
+ u32 brrl; /* Boot release */
+ u8 res_0e8[0x100-0xe8];
+ u32 rcwsr[16]; /* Reset control word status */
+#define FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_SHIFT 25
+#define FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_MASK 0x1f
+#define FSL_CHASSIS2_RCWSR0_MEM_PLL_RAT_SHIFT 16
+#define FSL_CHASSIS2_RCWSR0_MEM_PLL_RAT_MASK 0x3f
+#define FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK 0xffff0000
+#define FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT 16
+ u8 res_140[0x200-0x140];
+ u32 scratchrw[4]; /* Scratch Read/Write */
+ u8 res_210[0x300-0x210];
+ u32 scratchw1r[4]; /* Scratch Read (Write once) */
+ u8 res_310[0x400-0x310];
+ u32 crstsr[12];
+ u8 res_430[0x500-0x430];
+
+ /* PCI Express n Logical I/O Device Number register */
+ u32 dcfg_ccsr_pex1liodnr;
+ u32 dcfg_ccsr_pex2liodnr;
+ u32 dcfg_ccsr_pex3liodnr;
+ u32 dcfg_ccsr_pex4liodnr;
+ /* RIO n Logical I/O Device Number register */
+ u32 dcfg_ccsr_rio1liodnr;
+ u32 dcfg_ccsr_rio2liodnr;
+ u32 dcfg_ccsr_rio3liodnr;
+ u32 dcfg_ccsr_rio4liodnr;
+ /* USB Logical I/O Device Number register */
+ u32 dcfg_ccsr_usb1liodnr;
+ u32 dcfg_ccsr_usb2liodnr;
+ u32 dcfg_ccsr_usb3liodnr;
+ u32 dcfg_ccsr_usb4liodnr;
+ /* SD/MMC Logical I/O Device Number register */
+ u32 dcfg_ccsr_sdmmc1liodnr;
+ u32 dcfg_ccsr_sdmmc2liodnr;
+ u32 dcfg_ccsr_sdmmc3liodnr;
+ u32 dcfg_ccsr_sdmmc4liodnr;
+ /* RIO Message Unit Logical I/O Device Number register */
+ u32 dcfg_ccsr_riomaintliodnr;
+
+ u8 res_544[0x550-0x544];
+ u32 sataliodnr[4];
+ u8 res_560[0x570-0x560];
+
+ u32 dcfg_ccsr_misc1liodnr;
+ u32 dcfg_ccsr_misc2liodnr;
+ u32 dcfg_ccsr_misc3liodnr;
+ u32 dcfg_ccsr_misc4liodnr;
+ u32 dcfg_ccsr_dma1liodnr;
+ u32 dcfg_ccsr_dma2liodnr;
+ u32 dcfg_ccsr_dma3liodnr;
+ u32 dcfg_ccsr_dma4liodnr;
+ u32 dcfg_ccsr_spare1liodnr;
+ u32 dcfg_ccsr_spare2liodnr;
+ u32 dcfg_ccsr_spare3liodnr;
+ u32 dcfg_ccsr_spare4liodnr;
+ u8 res_5a0[0x600-0x5a0];
+ u32 dcfg_ccsr_pblsr;
+
+ u32 pamubypenr;
+ u32 dmacr1;
+
+ u8 res_60c[0x610-0x60c];
+ u32 dcfg_ccsr_gensr1;
+ u32 dcfg_ccsr_gensr2;
+ u32 dcfg_ccsr_gensr3;
+ u32 dcfg_ccsr_gensr4;
+ u32 dcfg_ccsr_gencr1;
+ u32 dcfg_ccsr_gencr2;
+ u32 dcfg_ccsr_gencr3;
+ u32 dcfg_ccsr_gencr4;
+ u32 dcfg_ccsr_gencr5;
+ u32 dcfg_ccsr_gencr6;
+ u32 dcfg_ccsr_gencr7;
+ u8 res_63c[0x658-0x63c];
+ u32 dcfg_ccsr_cgensr1;
+ u32 dcfg_ccsr_cgensr0;
+ u8 res_660[0x678-0x660];
+ u32 dcfg_ccsr_cgencr1;
+
+ u32 dcfg_ccsr_cgencr0;
+ u8 res_680[0x700-0x680];
+ u32 dcfg_ccsr_sriopstecr;
+ u32 dcfg_ccsr_dcsrcr;
+
+ u8 res_708[0x740-0x708]; /* add more registers when needed */
+ u32 tp_ityp[64]; /* Topology Initiator Type Register */
+ struct {
+ u32 upper;
+ u32 lower;
+ } tp_cluster[16];
+ u8 res_8c0[0xa00-0x8c0]; /* add more registers when needed */
+ u32 dcfg_ccsr_qmbm_warmrst;
+ u8 res_a04[0xa20-0xa04]; /* add more registers when needed */
+ u32 dcfg_ccsr_reserved0;
+ u32 dcfg_ccsr_reserved1;
+};
+
+#define SCFG_QSPI_CLKSEL 0x40100000
+#define SCFG_USBDRVVBUS_SELCR_USB1 0x00000000
+#define SCFG_USBDRVVBUS_SELCR_USB2 0x00000001
+#define SCFG_USBDRVVBUS_SELCR_USB3 0x00000002
+#define SCFG_USBPWRFAULT_INACTIVE 0x00000000
+#define SCFG_USBPWRFAULT_SHARED 0x00000001
+#define SCFG_USBPWRFAULT_DEDICATED 0x00000002
+#define SCFG_USBPWRFAULT_USB3_SHIFT 4
+#define SCFG_USBPWRFAULT_USB2_SHIFT 2
+#define SCFG_USBPWRFAULT_USB1_SHIFT 0
+
+#define SCFG_SNPCNFGCR_SECRDSNP 0x80000000
+#define SCFG_SNPCNFGCR_SECWRSNP 0x40000000
+
+/* Supplemental Configuration Unit */
+struct ccsr_scfg {
+ u8 res_000[0x100-0x000];
+ u32 usb2_icid;
+ u32 usb3_icid;
+ u8 res_108[0x114-0x108];
+ u32 dma_icid;
+ u32 sata_icid;
+ u32 usb1_icid;
+ u32 qe_icid;
+ u32 sdhc_icid;
+ u32 edma_icid;
+ u32 etr_icid;
+ u32 core_sft_rst[4];
+ u8 res_140[0x158-0x140];
+ u32 altcbar;
+ u32 qspi_cfg;
+ u8 res_160[0x180-0x160];
+ u32 dmamcr;
+ u8 res_184[0x18c-0x184];
+ u32 debug_icid;
+ u8 res_190[0x1a4-0x190];
+ u32 snpcnfgcr;
+ u8 res_1a8[0x1ac-0x1a8];
+ u32 intpcr;
+ u8 res_1b0[0x204-0x1b0];
+ u32 coresrencr;
+ u8 res_208[0x220-0x208];
+ u32 rvbar0_0;
+ u32 rvbar0_1;
+ u32 rvbar1_0;
+ u32 rvbar1_1;
+ u32 rvbar2_0;
+ u32 rvbar2_1;
+ u32 rvbar3_0;
+ u32 rvbar3_1;
+ u32 lpmcsr;
+ u8 res_244[0x400-0x244];
+ u32 qspidqscr;
+ u32 ecgtxcmcr;
+ u32 sdhciovselcr;
+ u32 rcwpmuxcr0;
+ u32 usbdrvvbus_selcr;
+ u32 usbpwrfault_selcr;
+ u32 usb_refclk_selcr1;
+ u32 usb_refclk_selcr2;
+ u32 usb_refclk_selcr3;
+ u8 res_424[0x600-0x424];
+ u32 scratchrw[4];
+ u8 res_610[0x680-0x610];
+ u32 corebcr;
+ u8 res_684[0x1000-0x684];
+ u32 pex1msiir;
+ u32 pex1msir;
+ u8 res_1008[0x2000-0x1008];
+ u32 pex2;
+ u32 pex2msir;
+ u8 res_2008[0x3000-0x2008];
+ u32 pex3msiir;
+ u32 pex3msir;
+};
+
+/* Clocking */
+struct ccsr_clk {
+ struct {
+ u32 clkcncsr; /* core cluster n clock control status */
+ u8 res_004[0x0c];
+ u32 clkcghwacsr; /* Clock generator n hardware accelerator */
+ u8 res_014[0x0c];
+ } clkcsr[4];
+ u8 res_040[0x780]; /* 0x100 */
+ struct {
+ u32 pllcngsr;
+ u8 res_804[0x1c];
+ } pllcgsr[2];
+ u8 res_840[0x1c0];
+ u32 clkpcsr; /* 0xa00 Platform clock domain control/status */
+ u8 res_a04[0x1fc];
+ u32 pllpgsr; /* 0xc00 Platform PLL General Status */
+ u8 res_c04[0x1c];
+ u32 plldgsr; /* 0xc20 DDR PLL General Status */
+ u8 res_c24[0x3dc];
+};
+
+/* System Counter */
+struct sctr_regs {
+ u32 cntcr;
+ u32 cntsr;
+ u32 cntcv1;
+ u32 cntcv2;
+ u32 resv1[4];
+ u32 cntfid0;
+ u32 cntfid1;
+ u32 resv2[1002];
+ u32 counterid[12];
+};
+
+#define SRDS_MAX_LANES 4
+struct ccsr_serdes {
+ struct {
+ u32 rstctl; /* Reset Control Register */
+#define SRDS_RSTCTL_RST 0x80000000
+#define SRDS_RSTCTL_RSTDONE 0x40000000
+#define SRDS_RSTCTL_RSTERR 0x20000000
+#define SRDS_RSTCTL_SWRST 0x10000000
+#define SRDS_RSTCTL_SDEN 0x00000020
+#define SRDS_RSTCTL_SDRST_B 0x00000040
+#define SRDS_RSTCTL_PLLRST_B 0x00000080
+ u32 pllcr0; /* PLL Control Register 0 */
+#define SRDS_PLLCR0_POFF 0x80000000
+#define SRDS_PLLCR0_RFCK_SEL_MASK 0x70000000
+#define SRDS_PLLCR0_RFCK_SEL_100 0x00000000
+#define SRDS_PLLCR0_RFCK_SEL_125 0x10000000
+#define SRDS_PLLCR0_RFCK_SEL_156_25 0x20000000
+#define SRDS_PLLCR0_RFCK_SEL_150 0x30000000
+#define SRDS_PLLCR0_RFCK_SEL_161_13 0x40000000
+#define SRDS_PLLCR0_RFCK_SEL_122_88 0x50000000
+#define SRDS_PLLCR0_PLL_LCK 0x00800000
+#define SRDS_PLLCR0_FRATE_SEL_MASK 0x000f0000
+#define SRDS_PLLCR0_FRATE_SEL_5 0x00000000
+#define SRDS_PLLCR0_FRATE_SEL_3_75 0x00050000
+#define SRDS_PLLCR0_FRATE_SEL_5_15 0x00060000
+#define SRDS_PLLCR0_FRATE_SEL_4 0x00070000
+#define SRDS_PLLCR0_FRATE_SEL_3_12 0x00090000
+#define SRDS_PLLCR0_FRATE_SEL_3 0x000a0000
+ u32 pllcr1; /* PLL Control Register 1 */
+#define SRDS_PLLCR1_PLL_BWSEL 0x08000000
+ u32 res_0c; /* 0x00c */
+ u32 pllcr3;
+ u32 pllcr4;
+ u8 res_18[0x20-0x18];
+ } bank[2];
+ u8 res_40[0x90-0x40];
+ u32 srdstcalcr; /* 0x90 TX Calibration Control */
+ u8 res_94[0xa0-0x94];
+ u32 srdsrcalcr; /* 0xa0 RX Calibration Control */
+ u8 res_a4[0xb0-0xa4];
+ u32 srdsgr0; /* 0xb0 General Register 0 */
+ u8 res_b4[0xe0-0xb4];
+ u32 srdspccr0; /* 0xe0 Protocol Converter Config 0 */
+ u32 srdspccr1; /* 0xe4 Protocol Converter Config 1 */
+ u32 srdspccr2; /* 0xe8 Protocol Converter Config 2 */
+ u32 srdspccr3; /* 0xec Protocol Converter Config 3 */
+ u32 srdspccr4; /* 0xf0 Protocol Converter Config 4 */
+ u8 res_f4[0x100-0xf4];
+ struct {
+ u32 lnpssr; /* 0x100, 0x120, ..., 0x1e0 */
+ u8 res_104[0x120-0x104];
+ } srdslnpssr[4];
+ u8 res_180[0x300-0x180];
+ u32 srdspexeqcr;
+ u32 srdspexeqpcr[11];
+ u8 res_330[0x400-0x330];
+ u32 srdspexapcr;
+ u8 res_404[0x440-0x404];
+ u32 srdspexbpcr;
+ u8 res_444[0x800-0x444];
+ struct {
+ u32 gcr0; /* 0x800 General Control Register 0 */
+ u32 gcr1; /* 0x804 General Control Register 1 */
+ u32 gcr2; /* 0x808 General Control Register 2 */
+ u32 sscr0;
+ u32 recr0; /* 0x810 Receive Equalization Control */
+ u32 recr1;
+ u32 tecr0; /* 0x818 Transmit Equalization Control */
+ u32 sscr1;
+ u32 ttlcr0; /* 0x820 Transition Tracking Loop Ctrl 0 */
+ u8 res_824[0x83c-0x824];
+ u32 tcsr3;
+ } lane[4]; /* Lane A, B, C, D, E, F, G, H */
+ u8 res_a00[0x1000-0xa00]; /* from 0xa00 to 0xfff */
+};
+
+#define CCI400_CTRLORD_TERM_BARRIER 0x00000008
+#define CCI400_CTRLORD_EN_BARRIER 0
+#define CCI400_SHAORD_NON_SHAREABLE 0x00000002
+#define CCI400_DVM_MESSAGE_REQ_EN 0x00000002
+#define CCI400_SNOOP_REQ_EN 0x00000001
+
+/* CCI-400 registers */
+struct ccsr_cci400 {
+ u32 ctrl_ord; /* Control Override */
+ u32 spec_ctrl; /* Speculation Control */
+ u32 secure_access; /* Secure Access */
+ u32 status; /* Status */
+ u32 impr_err; /* Imprecise Error */
+ u8 res_14[0x100 - 0x14];
+ u32 pmcr; /* Performance Monitor Control */
+ u8 res_104[0xfd0 - 0x104];
+ u32 pid[8]; /* Peripheral ID */
+ u32 cid[4]; /* Component ID */
+ struct {
+ u32 snoop_ctrl; /* Snoop Control */
+ u32 sha_ord; /* Shareable Override */
+ u8 res_1008[0x1100 - 0x1008];
+ u32 rc_qos_ord; /* read channel QoS Value Override */
+ u32 wc_qos_ord; /* read channel QoS Value Override */
+ u8 res_1108[0x110c - 0x1108];
+ u32 qos_ctrl; /* QoS Control */
+ u32 max_ot; /* Max OT */
+ u8 res_1114[0x1130 - 0x1114];
+ u32 target_lat; /* Target Latency */
+ u32 latency_regu; /* Latency Regulation */
+ u32 qos_range; /* QoS Range */
+ u8 res_113c[0x2000 - 0x113c];
+ } slave[5]; /* Slave Interface */
+ u8 res_6000[0x9004 - 0x6000];
+ u32 cycle_counter; /* Cycle counter */
+ u32 count_ctrl; /* Count Control */
+ u32 overflow_status; /* Overflow Flag Status */
+ u8 res_9010[0xa000 - 0x9010];
+ struct {
+ u32 event_select; /* Event Select */
+ u32 event_count; /* Event Count */
+ u32 counter_ctrl; /* Counter Control */
+ u32 overflow_status; /* Overflow Flag Status */
+ u8 res_a010[0xb000 - 0xa010];
+ } pcounter[4]; /* Performance Counter */
+ u8 res_e004[0x10000 - 0xe004];
+};
+
+/* MMU 500 */
+#define SMMU_SCR0 (SMMU_BASE + 0x0)
+#define SMMU_SCR1 (SMMU_BASE + 0x4)
+#define SMMU_SCR2 (SMMU_BASE + 0x8)
+#define SMMU_SACR (SMMU_BASE + 0x10)
+#define SMMU_IDR0 (SMMU_BASE + 0x20)
+#define SMMU_IDR1 (SMMU_BASE + 0x24)
+
+#define SMMU_NSCR0 (SMMU_BASE + 0x400)
+#define SMMU_NSCR2 (SMMU_BASE + 0x408)
+#define SMMU_NSACR (SMMU_BASE + 0x410)
+
+#define SCR0_CLIENTPD_MASK 0x00000001
+#define SCR0_USFCFG_MASK 0x00000400
+
+#endif /* __ARCH_FSL_LSCH2_IMMAP_H__*/
diff --git a/arch/arm/include/asm/arch-fsl-lsch3/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
similarity index 58%
rename from arch/arm/include/asm/arch-fsl-lsch3/immap_lsch3.h
rename to arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
index d6bee60385f04d8dee260dbb7a699a6ec38ffb8b..6a70d443055e49c52d1f348537b436e692f32b4e 100644
--- a/arch/arm/include/asm/arch-fsl-lsch3/immap_lsch3.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
@@ -6,9 +6,109 @@
* SPDX-License-Identifier: GPL-2.0+
*/
-#ifndef __ARCH_FSL_LSCH3_IMMAP_H
+#ifndef __ARCH_FSL_LSCH3_IMMAP_H_
#define __ARCH_FSL_LSCH3_IMMAP_H_
+#define CONFIG_SYS_IMMR 0x01000000
+#define CONFIG_SYS_FSL_DDR_ADDR (CONFIG_SYS_IMMR + 0x00080000)
+#define CONFIG_SYS_FSL_DDR2_ADDR (CONFIG_SYS_IMMR + 0x00090000)
+#define CONFIG_SYS_FSL_DDR3_ADDR 0x08210000
+#define CONFIG_SYS_FSL_GUTS_ADDR (CONFIG_SYS_IMMR + 0x00E00000)
+#define CONFIG_SYS_FSL_PMU_ADDR (CONFIG_SYS_IMMR + 0x00E30000)
+#define CONFIG_SYS_FSL_RST_ADDR (CONFIG_SYS_IMMR + 0x00E60000)
+#define CONFIG_SYS_FSL_CH3_CLK_GRPA_ADDR (CONFIG_SYS_IMMR + 0x00300000)
+#define CONFIG_SYS_FSL_CH3_CLK_GRPB_ADDR (CONFIG_SYS_IMMR + 0x00310000)
+#define CONFIG_SYS_FSL_CH3_CLK_CTRL_ADDR (CONFIG_SYS_IMMR + 0x00370000)
+#define CONFIG_SYS_FSL_ESDHC_ADDR (CONFIG_SYS_IMMR + 0x01140000)
+#define CONFIG_SYS_IFC_ADDR (CONFIG_SYS_IMMR + 0x01240000)
+#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x011C0500)
+#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x011C0600)
+#define CONFIG_SYS_FSL_TIMER_ADDR 0x023d0000
+#define CONFIG_SYS_FSL_PMU_CLTBENR (CONFIG_SYS_FSL_PMU_ADDR + \
+ 0x18A0)
+
+#define CONFIG_SYS_FSL_WRIOP1_ADDR (CONFIG_SYS_IMMR + 0x7B80000)
+#define CONFIG_SYS_FSL_WRIOP1_MDIO1 (CONFIG_SYS_FSL_WRIOP1_ADDR + 0x16000)
+#define CONFIG_SYS_FSL_WRIOP1_MDIO2 (CONFIG_SYS_FSL_WRIOP1_ADDR + 0x17000)
+#define CONFIG_SYS_FSL_LSCH3_SERDES_ADDR (CONFIG_SYS_IMMR + 0xEA0000)
+
+/* SP (Cortex-A5) related */
+#define CONFIG_SYS_FSL_SP_ADDR (CONFIG_SYS_IMMR + 0x00F00000)
+#define CONFIG_SYS_FSL_SP_VSG_GIC_ADDR (CONFIG_SYS_FSL_SP_ADDR)
+#define CONFIG_SYS_FSL_SP_VSG_GIC_VIGR1 (CONFIG_SYS_FSL_SP_ADDR)
+#define CONFIG_SYS_FSL_SP_VSG_GIC_VIGR2 \
+ (CONFIG_SYS_FSL_SP_ADDR + 0x0008)
+#define CONFIG_SYS_FSL_SP_LOOPBACK_DUART \
+ (CONFIG_SYS_FSL_SP_ADDR + 0x1000)
+
+#define CONFIG_SYS_FSL_DCSR_DDR_ADDR 0x70012c000ULL
+#define CONFIG_SYS_FSL_DCSR_DDR2_ADDR 0x70012d000ULL
+#define CONFIG_SYS_FSL_DCSR_DDR3_ADDR 0x700132000ULL
+#define CONFIG_SYS_FSL_DCSR_DDR4_ADDR 0x700133000ULL
+
+#define I2C1_BASE_ADDR (CONFIG_SYS_IMMR + 0x01000000)
+#define I2C2_BASE_ADDR (CONFIG_SYS_IMMR + 0x01010000)
+#define I2C3_BASE_ADDR (CONFIG_SYS_IMMR + 0x01020000)
+#define I2C4_BASE_ADDR (CONFIG_SYS_IMMR + 0x01030000)
+
+#define CONFIG_SYS_LS2085A_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x02100000)
+#define CONFIG_SYS_LS2085A_XHCI_USB2_ADDR (CONFIG_SYS_IMMR + 0x02110000)
+
+/* TZ Address Space Controller Definitions */
+#define TZASC1_BASE 0x01100000 /* as per CCSR map. */
+#define TZASC2_BASE 0x01110000 /* as per CCSR map. */
+#define TZASC3_BASE 0x01120000 /* as per CCSR map. */
+#define TZASC4_BASE 0x01130000 /* as per CCSR map. */
+#define TZASC_BUILD_CONFIG_REG(x) ((TZASC1_BASE + (x * 0x10000)))
+#define TZASC_ACTION_REG(x) ((TZASC1_BASE + (x * 0x10000)) + 0x004)
+#define TZASC_GATE_KEEPER(x) ((TZASC1_BASE + (x * 0x10000)) + 0x008)
+#define TZASC_REGION_BASE_LOW_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x100)
+#define TZASC_REGION_BASE_HIGH_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x104)
+#define TZASC_REGION_TOP_LOW_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x108)
+#define TZASC_REGION_TOP_HIGH_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x10C)
+#define TZASC_REGION_ATTRIBUTES_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x110)
+#define TZASC_REGION_ID_ACCESS_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x114)
+
+/* PCIe */
+#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_IMMR + 0x2400000)
+#define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_IMMR + 0x2500000)
+#define CONFIG_SYS_PCIE3_ADDR (CONFIG_SYS_IMMR + 0x2600000)
+#define CONFIG_SYS_PCIE4_ADDR (CONFIG_SYS_IMMR + 0x2700000)
+#define CONFIG_SYS_PCIE1_PHYS_ADDR 0x1000000000ULL
+#define CONFIG_SYS_PCIE2_PHYS_ADDR 0x1200000000ULL
+#define CONFIG_SYS_PCIE3_PHYS_ADDR 0x1400000000ULL
+#define CONFIG_SYS_PCIE4_PHYS_ADDR 0x1600000000ULL
+
+/* Device Configuration */
+#define DCFG_BASE 0x01e00000
+#define DCFG_PORSR1 0x000
+#define DCFG_PORSR1_RCW_SRC 0xff800000
+#define DCFG_PORSR1_RCW_SRC_NOR 0x12f00000
+#define DCFG_RCWSR13 0x130
+#define DCFG_RCWSR13_DSPI (0 << 8)
+
+#define DCFG_DCSR_BASE 0X700100000ULL
+#define DCFG_DCSR_PORCR1 0x000
+
+/* Supplemental Configuration */
+#define SCFG_BASE 0x01fc0000
+#define SCFG_USB3PRM1CR 0x000
+
+#define TP_ITYP_AV 0x00000001 /* Initiator available */
+#define TP_ITYP_TYPE(x) (((x) & 0x6) >> 1) /* Initiator Type */
+#define TP_ITYP_TYPE_ARM 0x0
+#define TP_ITYP_TYPE_PPC 0x1 /* PowerPC */
+#define TP_ITYP_TYPE_OTHER 0x2 /* StarCore DSP */
+#define TP_ITYP_TYPE_HA 0x3 /* HW Accelerator */
+#define TP_ITYP_THDS(x) (((x) & 0x18) >> 3) /* # threads */
+#define TP_ITYP_VER(x) (((x) & 0xe0) >> 5) /* Initiator Version */
+#define TY_ITYP_VER_A7 0x1
+#define TY_ITYP_VER_A53 0x2
+#define TY_ITYP_VER_A57 0x3
+
+#define TP_CLUSTER_EOC 0x80000000 /* end of clusters */
+#define TP_CLUSTER_INIT_MASK 0x0000003f /* initiator mask */
+#define TP_INIT_PER_CLUSTER 4
/* This is chassis generation 3 */
struct sys_info {
@@ -109,21 +209,6 @@ struct ccsr_gur {
u8 res_858[0x1000-0x858];
};
-#define TP_ITYP_AV 0x00000001 /* Initiator available */
-#define TP_ITYP_TYPE(x) (((x) & 0x6) >> 1) /* Initiator Type */
-#define TP_ITYP_TYPE_ARM 0x0
-#define TP_ITYP_TYPE_PPC 0x1 /* PowerPC */
-#define TP_ITYP_TYPE_OTHER 0x2 /* StarCore DSP */
-#define TP_ITYP_TYPE_HA 0x3 /* HW Accelerator */
-#define TP_ITYP_THDS(x) (((x) & 0x18) >> 3) /* # threads */
-#define TP_ITYP_VER(x) (((x) & 0xe0) >> 5) /* Initiator Version */
-#define TY_ITYP_VER_A7 0x1
-#define TY_ITYP_VER_A53 0x2
-#define TY_ITYP_VER_A57 0x3
-
-#define TP_CLUSTER_EOC 0x80000000 /* end of clusters */
-#define TP_CLUSTER_INIT_MASK 0x0000003f /* initiator mask */
-#define TP_INIT_PER_CLUSTER 4
struct ccsr_clk_cluster_group {
struct {
@@ -180,4 +265,4 @@ struct ccsr_reset {
u32 ip_rev1; /* 0xbf8 */
u32 ip_rev2; /* 0xbfc */
};
-#endif /* __ARCH_FSL_LSCH3_IMMAP_H */
+#endif /* __ARCH_FSL_LSCH3_IMMAP_H_ */
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/imx-regs.h b/arch/arm/include/asm/arch-fsl-layerscape/imx-regs.h
new file mode 100644
index 0000000000000000000000000000000000000000..57e417b9e08a281a5f226d516a6433187d7cf15c
--- /dev/null
+++ b/arch/arm/include/asm/arch-fsl-layerscape/imx-regs.h
@@ -0,0 +1,55 @@
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ */
+
+#ifndef __ASM_ARCH_FSL_LAYERSCAPE_IMX_REGS_H__
+#define __ASM_ARCH_FSL_LAYERSCAPE_IMX_REGS_H__
+
+#define I2C_QUIRK_REG /* enable 8-bit driver */
+
+#ifdef CONFIG_FSL_LPUART
+#ifdef CONFIG_LPUART_32B_REG
+struct lpuart_fsl {
+ u32 baud;
+ u32 stat;
+ u32 ctrl;
+ u32 data;
+ u32 match;
+ u32 modir;
+ u32 fifo;
+ u32 water;
+};
+#else
+struct lpuart_fsl {
+ u8 ubdh;
+ u8 ubdl;
+ u8 uc1;
+ u8 uc2;
+ u8 us1;
+ u8 us2;
+ u8 uc3;
+ u8 ud;
+ u8 uma1;
+ u8 uma2;
+ u8 uc4;
+ u8 uc5;
+ u8 ued;
+ u8 umodem;
+ u8 uir;
+ u8 reserved;
+ u8 upfifo;
+ u8 ucfifo;
+ u8 usfifo;
+ u8 utwfifo;
+ u8 utcfifo;
+ u8 urwfifo;
+ u8 urcfifo;
+ u8 rsvd[28];
+};
+#endif
+#endif /* CONFIG_FSL_LPUART */
+
+#endif /* __ASM_ARCH_FSL_LAYERSCAPE_IMX_REGS_H__ */
diff --git a/arch/arm/include/asm/arch-fsl-lsch3/ls2085a_stream_id.h b/arch/arm/include/asm/arch-fsl-layerscape/ls2085a_stream_id.h
similarity index 100%
rename from arch/arm/include/asm/arch-fsl-lsch3/ls2085a_stream_id.h
rename to arch/arm/include/asm/arch-fsl-layerscape/ls2085a_stream_id.h
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/mmu.h b/arch/arm/include/asm/arch-fsl-layerscape/mmu.h
new file mode 100644
index 0000000000000000000000000000000000000000..d54eacd4a038044518407870eeb4351b0fe195a4
--- /dev/null
+++ b/arch/arm/include/asm/arch-fsl-layerscape/mmu.h
@@ -0,0 +1,10 @@
+/*
+ * Copyright 2015, Freescale Semiconductor
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _ASM_ARMV8_FSL_LAYERSCAPE_MMU_H_
+#define _ASM_ARMV8_FSL_LAYERSCAPE_MMU_H_
+#include <asm/arch-armv8/mmu.h>
+#endif /* _ASM_ARMV8_FSL_LAYERSCAPE_MMU_H_ */
diff --git a/arch/arm/cpu/armv8/fsl-lsch3/mp.h b/arch/arm/include/asm/arch-fsl-layerscape/mp.h
similarity index 82%
rename from arch/arm/cpu/armv8/fsl-lsch3/mp.h
rename to arch/arm/include/asm/arch-fsl-layerscape/mp.h
index c985d6a6bad6ebce0d38b649000e4abffdaaf87a..e46e076f16b09c737fb3521f8dd1ec62a05f0bf8 100644
--- a/arch/arm/cpu/armv8/fsl-lsch3/mp.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/mp.h
@@ -1,11 +1,11 @@
/*
- * Copyright 2014, Freescale Semiconductor
+ * Copyright 2014-2015, Freescale Semiconductor
*
* SPDX-License-Identifier: GPL-2.0+
*/
-#ifndef _FSL_CH3_MP_H
-#define _FSL_CH3_MP_H
+#ifndef _FSL_LAYERSCAPE_MP_H
+#define _FSL_LAYERSCAPE_MP_H
/*
* Each spin table element is defined as
@@ -29,10 +29,10 @@ extern u64 __spin_table[];
extern u64 __real_cntfrq;
extern u64 *secondary_boot_code;
extern size_t __secondary_boot_code_size;
-int fsl_lsch3_wake_seconday_cores(void);
+int fsl_layerscape_wake_seconday_cores(void);
void *get_spin_tbl_addr(void);
phys_addr_t determine_mp_bootpg(void);
void secondary_boot_func(void);
int is_core_online(u64 cpu_id);
#endif
-#endif /* _FSL_CH3_MP_H */
+#endif /* _FSL_LAYERSCAPE_MP_H */
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h b/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h
new file mode 100644
index 0000000000000000000000000000000000000000..a3ccdb03c7f67969f86c4366175fd724f0447db4
--- /dev/null
+++ b/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h
@@ -0,0 +1,158 @@
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __FSL_NS_ACCESS_H_
+#define __FSL_NS_ACCESS_H_
+
+enum csu_cslx_ind {
+ CSU_CSLX_PCIE2_IO = 0,
+ CSU_CSLX_PCIE1_IO,
+ CSU_CSLX_MG2TPR_IP,
+ CSU_CSLX_IFC_MEM,
+ CSU_CSLX_OCRAM,
+ CSU_CSLX_GIC,
+ CSU_CSLX_PCIE1,
+ CSU_CSLX_OCRAM2,
+ CSU_CSLX_QSPI_MEM,
+ CSU_CSLX_PCIE2,
+ CSU_CSLX_SATA,
+ CSU_CSLX_USB1,
+ CSU_CSLX_QM_BM_SWPORTAL,
+ CSU_CSLX_PCIE3 = 16,
+ CSU_CSLX_PCIE3_IO,
+ CSU_CSLX_USB3 = 20,
+ CSU_CSLX_USB2,
+ CSU_CSLX_SERDES = 32,
+ CSU_CSLX_QDMA,
+ CSU_CSLX_LPUART2,
+ CSU_CSLX_LPUART1,
+ CSU_CSLX_LPUART4,
+ CSU_CSLX_LPUART3,
+ CSU_CSLX_LPUART6,
+ CSU_CSLX_LPUART5,
+ CSU_CSLX_DSPI1 = 41,
+ CSU_CSLX_QSPI,
+ CSU_CSLX_ESDHC,
+ CSU_CSLX_IFC = 45,
+ CSU_CSLX_I2C1,
+ CSU_CSLX_I2C3 = 48,
+ CSU_CSLX_I2C2,
+ CSU_CSLX_DUART2 = 50,
+ CSU_CSLX_DUART1,
+ CSU_CSLX_WDT2,
+ CSU_CSLX_WDT1,
+ CSU_CSLX_EDMA,
+ CSU_CSLX_SYS_CNT,
+ CSU_CSLX_DMA_MUX2,
+ CSU_CSLX_DMA_MUX1,
+ CSU_CSLX_DDR,
+ CSU_CSLX_QUICC,
+ CSU_CSLX_DCFG_CCU_RCPM = 60,
+ CSU_CSLX_SECURE_BOOTROM,
+ CSU_CSLX_SFP,
+ CSU_CSLX_TMU,
+ CSU_CSLX_SECURE_MONITOR,
+ CSU_CSLX_SCFG,
+ CSU_CSLX_FM = 66,
+ CSU_CSLX_SEC5_5,
+ CSU_CSLX_BM,
+ CSU_CSLX_QM,
+ CSU_CSLX_GPIO2 = 70,
+ CSU_CSLX_GPIO1,
+ CSU_CSLX_GPIO4,
+ CSU_CSLX_GPIO3,
+ CSU_CSLX_PLATFORM_CONT,
+ CSU_CSLX_CSU,
+ CSU_CSLX_IIC4 = 77,
+ CSU_CSLX_WDT4,
+ CSU_CSLX_WDT3,
+ CSU_CSLX_WDT5 = 81,
+ CSU_CSLX_FTM2 = 86,
+ CSU_CSLX_FTM1,
+ CSU_CSLX_FTM4,
+ CSU_CSLX_FTM3,
+ CSU_CSLX_FTM6 = 90,
+ CSU_CSLX_FTM5,
+ CSU_CSLX_FTM8,
+ CSU_CSLX_FTM7,
+ CSU_CSLX_DSCR = 121,
+};
+
+static struct csu_ns_dev ns_dev[] = {
+ {CSU_CSLX_PCIE2_IO, CSU_ALL_RW},
+ {CSU_CSLX_PCIE1_IO, CSU_ALL_RW},
+ {CSU_CSLX_MG2TPR_IP, CSU_ALL_RW},
+ {CSU_CSLX_IFC_MEM, CSU_ALL_RW},
+ {CSU_CSLX_OCRAM, CSU_ALL_RW},
+ {CSU_CSLX_GIC, CSU_ALL_RW},
+ {CSU_CSLX_PCIE1, CSU_ALL_RW},
+ {CSU_CSLX_OCRAM2, CSU_ALL_RW},
+ {CSU_CSLX_QSPI_MEM, CSU_ALL_RW},
+ {CSU_CSLX_PCIE2, CSU_ALL_RW},
+ {CSU_CSLX_SATA, CSU_ALL_RW},
+ {CSU_CSLX_USB1, CSU_ALL_RW},
+ {CSU_CSLX_QM_BM_SWPORTAL, CSU_ALL_RW},
+ {CSU_CSLX_PCIE3, CSU_ALL_RW},
+ {CSU_CSLX_PCIE3_IO, CSU_ALL_RW},
+ {CSU_CSLX_USB3, CSU_ALL_RW},
+ {CSU_CSLX_USB2, CSU_ALL_RW},
+ {CSU_CSLX_SERDES, CSU_ALL_RW},
+ {CSU_CSLX_QDMA, CSU_ALL_RW},
+ {CSU_CSLX_LPUART2, CSU_ALL_RW},
+ {CSU_CSLX_LPUART1, CSU_ALL_RW},
+ {CSU_CSLX_LPUART4, CSU_ALL_RW},
+ {CSU_CSLX_LPUART3, CSU_ALL_RW},
+ {CSU_CSLX_LPUART6, CSU_ALL_RW},
+ {CSU_CSLX_LPUART5, CSU_ALL_RW},
+ {CSU_CSLX_DSPI1, CSU_ALL_RW},
+ {CSU_CSLX_QSPI, CSU_ALL_RW},
+ {CSU_CSLX_ESDHC, CSU_ALL_RW},
+ {CSU_CSLX_IFC, CSU_ALL_RW},
+ {CSU_CSLX_I2C1, CSU_ALL_RW},
+ {CSU_CSLX_I2C3, CSU_ALL_RW},
+ {CSU_CSLX_I2C2, CSU_ALL_RW},
+ {CSU_CSLX_DUART2, CSU_ALL_RW},
+ {CSU_CSLX_DUART1, CSU_ALL_RW},
+ {CSU_CSLX_WDT2, CSU_ALL_RW},
+ {CSU_CSLX_WDT1, CSU_ALL_RW},
+ {CSU_CSLX_EDMA, CSU_ALL_RW},
+ {CSU_CSLX_SYS_CNT, CSU_ALL_RW},
+ {CSU_CSLX_DMA_MUX2, CSU_ALL_RW},
+ {CSU_CSLX_DMA_MUX1, CSU_ALL_RW},
+ {CSU_CSLX_DDR, CSU_ALL_RW},
+ {CSU_CSLX_QUICC, CSU_ALL_RW},
+ {CSU_CSLX_DCFG_CCU_RCPM, CSU_ALL_RW},
+ {CSU_CSLX_SECURE_BOOTROM, CSU_ALL_RW},
+ {CSU_CSLX_SFP, CSU_ALL_RW},
+ {CSU_CSLX_TMU, CSU_ALL_RW},
+ {CSU_CSLX_SECURE_MONITOR, CSU_ALL_RW},
+ {CSU_CSLX_SCFG, CSU_ALL_RW},
+ {CSU_CSLX_FM, CSU_ALL_RW},
+ {CSU_CSLX_SEC5_5, CSU_ALL_RW},
+ {CSU_CSLX_BM, CSU_ALL_RW},
+ {CSU_CSLX_QM, CSU_ALL_RW},
+ {CSU_CSLX_GPIO2, CSU_ALL_RW},
+ {CSU_CSLX_GPIO1, CSU_ALL_RW},
+ {CSU_CSLX_GPIO4, CSU_ALL_RW},
+ {CSU_CSLX_GPIO3, CSU_ALL_RW},
+ {CSU_CSLX_PLATFORM_CONT, CSU_ALL_RW},
+ {CSU_CSLX_CSU, CSU_ALL_RW},
+ {CSU_CSLX_IIC4, CSU_ALL_RW},
+ {CSU_CSLX_WDT4, CSU_ALL_RW},
+ {CSU_CSLX_WDT3, CSU_ALL_RW},
+ {CSU_CSLX_WDT5, CSU_ALL_RW},
+ {CSU_CSLX_FTM2, CSU_ALL_RW},
+ {CSU_CSLX_FTM1, CSU_ALL_RW},
+ {CSU_CSLX_FTM4, CSU_ALL_RW},
+ {CSU_CSLX_FTM3, CSU_ALL_RW},
+ {CSU_CSLX_FTM6, CSU_ALL_RW},
+ {CSU_CSLX_FTM5, CSU_ALL_RW},
+ {CSU_CSLX_FTM8, CSU_ALL_RW},
+ {CSU_CSLX_FTM7, CSU_ALL_RW},
+ {CSU_CSLX_DSCR, CSU_ALL_RW},
+};
+
+#endif
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/soc.h b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
new file mode 100644
index 0000000000000000000000000000000000000000..5ed456e4e296a34c6ce1887698ef613312f2fd82
--- /dev/null
+++ b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
@@ -0,0 +1,53 @@
+/*
+ * Copyright 2015 Freescale Semiconductor
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _ASM_ARMV8_FSL_LAYERSCAPE_SOC_H_
+#define _ASM_ARMV8_FSL_LAYERSCAPE_SOC_H_
+
+#ifdef CONFIG_SYS_FSL_CCSR_GUR_LE
+#define gur_in32(a) in_le32(a)
+#define gur_out32(a, v) out_le32(a, v)
+#elif defined(CONFIG_SYS_FSL_CCSR_GUR_BE)
+#define gur_in32(a) in_be32(a)
+#define gur_out32(a, v) out_be32(a, v)
+#endif
+
+#ifdef CONFIG_SYS_FSL_CCSR_SCFG_LE
+#define scfg_in32(a) in_le32(a)
+#define scfg_out32(a, v) out_le32(a, v)
+#elif defined(CONFIG_SYS_FSL_CCSR_SCFG_BE)
+#define scfg_in32(a) in_be32(a)
+#define scfg_out32(a, v) out_be32(a, v)
+#endif
+
+struct cpu_type {
+ char name[15];
+ u32 soc_ver;
+ u32 num_cores;
+};
+
+#define CPU_TYPE_ENTRY(n, v, nc) \
+ { .name = #n, .soc_ver = SVR_##v, .num_cores = (nc)}
+
+#define SVR_WO_E 0xFFFFFE
+#define SVR_LS1043 0x879204
+#define SVR_LS2045 0x870120
+#define SVR_LS2080 0x870110
+#define SVR_LS2085 0x870100
+
+#define SVR_MAJ(svr) (((svr) >> 4) & 0xf)
+#define SVR_MIN(svr) (((svr) >> 0) & 0xf)
+#define SVR_SOC_VER(svr) (((svr) >> 8) & SVR_WO_E)
+#define IS_E_PROCESSOR(svr) (!((svr >> 8) & 0x1))
+
+#ifdef CONFIG_FSL_LSCH3
+void fsl_lsch3_early_init_f(void);
+#elif defined(CONFIG_FSL_LSCH2)
+void fsl_lsch2_early_init_f(void);
+#endif
+
+void cpu_name(char *name);
+#endif /* _ASM_ARMV8_FSL_LAYERSCAPE_SOC_H_ */
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/speed.h b/arch/arm/include/asm/arch-fsl-layerscape/speed.h
new file mode 100644
index 0000000000000000000000000000000000000000..de795f6056d85a27f9b7dd527a385a5264196ced
--- /dev/null
+++ b/arch/arm/include/asm/arch-fsl-layerscape/speed.h
@@ -0,0 +1,10 @@
+/*
+ * Copyright 2014-2015, Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _FSL_LAYERSCAPE_SPEED_H
+#define _FSL_LAYERSCAPE_SPEED_H
+void get_sys_info(struct sys_info *sys_info);
+#endif /* _FSL_LAYERSCAPE_SPEED_H */
diff --git a/arch/arm/include/asm/arch-fsl-lsch3/config.h b/arch/arm/include/asm/arch-fsl-lsch3/config.h
deleted file mode 100644
index 96d6c98cb8312c38606e740fcc288b13e4e5303a..0000000000000000000000000000000000000000
--- a/arch/arm/include/asm/arch-fsl-lsch3/config.h
+++ /dev/null
@@ -1,185 +0,0 @@
-/*
- * Copyright 2014, Freescale Semiconductor
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef _ASM_ARMV8_FSL_LSCH3_CONFIG_
-#define _ASM_ARMV8_FSL_LSCH3_CONFIG_
-
-#include <fsl_ddrc_version.h>
-
-#define CONFIG_SYS_PAGE_SIZE 0x10000
-#define CONFIG_SYS_CACHELINE_SIZE 64
-
-#ifndef L1_CACHE_BYTES
-#define L1_CACHE_SHIFT 6
-#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
-#endif
-
-#define CONFIG_MP
-#define CONFIG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */
-#define CONFIG_SYS_FSL_OCRAM_SIZE 0x00200000 /* 2M */
-/* Link Definitions */
-#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0)
-
-#define CONFIG_SYS_IMMR 0x01000000
-#define CONFIG_SYS_FSL_DDR_ADDR (CONFIG_SYS_IMMR + 0x00080000)
-#define CONFIG_SYS_FSL_DDR2_ADDR (CONFIG_SYS_IMMR + 0x00090000)
-#define CONFIG_SYS_FSL_DDR3_ADDR 0x08210000
-#define CONFIG_SYS_FSL_GUTS_ADDR (CONFIG_SYS_IMMR + 0x00E00000)
-#define CONFIG_SYS_FSL_PMU_ADDR (CONFIG_SYS_IMMR + 0x00E30000)
-#define CONFIG_SYS_FSL_RST_ADDR (CONFIG_SYS_IMMR + 0x00E60000)
-#define CONFIG_SYS_FSL_CH3_CLK_GRPA_ADDR (CONFIG_SYS_IMMR + 0x00300000)
-#define CONFIG_SYS_FSL_CH3_CLK_GRPB_ADDR (CONFIG_SYS_IMMR + 0x00310000)
-#define CONFIG_SYS_FSL_CH3_CLK_CTRL_ADDR (CONFIG_SYS_IMMR + 0x00370000)
-#define CONFIG_SYS_FSL_ESDHC_ADDR (CONFIG_SYS_IMMR + 0x01140000)
-#define CONFIG_SYS_IFC_ADDR (CONFIG_SYS_IMMR + 0x01240000)
-#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x011C0500)
-#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x011C0600)
-#define CONFIG_SYS_FSL_TIMER_ADDR 0x023d0000
-#define CONFIG_SYS_FSL_PMU_CLTBENR (CONFIG_SYS_FSL_PMU_ADDR + \
- 0x18A0)
-
-#define CONFIG_SYS_FSL_WRIOP1_ADDR (CONFIG_SYS_IMMR + 0x7B80000)
-#define CONFIG_SYS_FSL_WRIOP1_MDIO1 (CONFIG_SYS_FSL_WRIOP1_ADDR + 0x16000)
-#define CONFIG_SYS_FSL_WRIOP1_MDIO2 (CONFIG_SYS_FSL_WRIOP1_ADDR + 0x17000)
-#define CONFIG_SYS_FSL_LSCH3_SERDES_ADDR (CONFIG_SYS_IMMR + 0xEA0000)
-
-/* SP (Cortex-A5) related */
-#define CONFIG_SYS_FSL_SP_ADDR (CONFIG_SYS_IMMR + 0x00F00000)
-#define CONFIG_SYS_FSL_SP_VSG_GIC_ADDR (CONFIG_SYS_FSL_SP_ADDR)
-#define CONFIG_SYS_FSL_SP_VSG_GIC_VIGR1 (CONFIG_SYS_FSL_SP_ADDR)
-#define CONFIG_SYS_FSL_SP_VSG_GIC_VIGR2 \
- (CONFIG_SYS_FSL_SP_ADDR + 0x0008)
-#define CONFIG_SYS_FSL_SP_LOOPBACK_DUART \
- (CONFIG_SYS_FSL_SP_ADDR + 0x1000)
-
-#define CONFIG_SYS_FSL_DCSR_DDR_ADDR 0x70012c000ULL
-#define CONFIG_SYS_FSL_DCSR_DDR2_ADDR 0x70012d000ULL
-#define CONFIG_SYS_FSL_DCSR_DDR3_ADDR 0x700132000ULL
-#define CONFIG_SYS_FSL_DCSR_DDR4_ADDR 0x700133000ULL
-
-#define I2C1_BASE_ADDR (CONFIG_SYS_IMMR + 0x01000000)
-#define I2C2_BASE_ADDR (CONFIG_SYS_IMMR + 0x01010000)
-#define I2C3_BASE_ADDR (CONFIG_SYS_IMMR + 0x01020000)
-#define I2C4_BASE_ADDR (CONFIG_SYS_IMMR + 0x01030000)
-
-#define CONFIG_SYS_LS2085A_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x02100000)
-#define CONFIG_SYS_LS2085A_XHCI_USB2_ADDR (CONFIG_SYS_IMMR + 0x02110000)
-
-/* TZ Protection Controller Definitions */
-#define TZPC_BASE 0x02200000
-#define TZPCR0SIZE_BASE (TZPC_BASE)
-#define TZPCDECPROT_0_STAT_BASE (TZPC_BASE + 0x800)
-#define TZPCDECPROT_0_SET_BASE (TZPC_BASE + 0x804)
-#define TZPCDECPROT_0_CLR_BASE (TZPC_BASE + 0x808)
-#define TZPCDECPROT_1_STAT_BASE (TZPC_BASE + 0x80C)
-#define TZPCDECPROT_1_SET_BASE (TZPC_BASE + 0x810)
-#define TZPCDECPROT_1_CLR_BASE (TZPC_BASE + 0x814)
-#define TZPCDECPROT_2_STAT_BASE (TZPC_BASE + 0x818)
-#define TZPCDECPROT_2_SET_BASE (TZPC_BASE + 0x81C)
-#define TZPCDECPROT_2_CLR_BASE (TZPC_BASE + 0x820)
-
-/* TZ Address Space Controller Definitions */
-#define TZASC1_BASE 0x01100000 /* as per CCSR map. */
-#define TZASC2_BASE 0x01110000 /* as per CCSR map. */
-#define TZASC3_BASE 0x01120000 /* as per CCSR map. */
-#define TZASC4_BASE 0x01130000 /* as per CCSR map. */
-#define TZASC_BUILD_CONFIG_REG(x) ((TZASC1_BASE + (x * 0x10000)))
-#define TZASC_ACTION_REG(x) ((TZASC1_BASE + (x * 0x10000)) + 0x004)
-#define TZASC_GATE_KEEPER(x) ((TZASC1_BASE + (x * 0x10000)) + 0x008)
-#define TZASC_REGION_BASE_LOW_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x100)
-#define TZASC_REGION_BASE_HIGH_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x104)
-#define TZASC_REGION_TOP_LOW_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x108)
-#define TZASC_REGION_TOP_HIGH_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x10C)
-#define TZASC_REGION_ATTRIBUTES_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x110)
-#define TZASC_REGION_ID_ACCESS_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x114)
-
-/* Generic Interrupt Controller Definitions */
-#define GICD_BASE 0x06000000
-#define GICR_BASE 0x06100000
-
-/* SMMU Defintions */
-#define SMMU_BASE 0x05000000 /* GR0 Base */
-
-/* DDR */
-#define CONFIG_SYS_FSL_DDR_LE
-#define CONFIG_VERY_BIG_RAM
-#ifdef CONFIG_SYS_FSL_DDR4
-#define CONFIG_SYS_FSL_DDRC_GEN4
-#else
-#define CONFIG_SYS_FSL_DDRC_ARM_GEN3 /* Enable Freescale ARM DDR3 driver */
-#endif
-#define CONFIG_SYS_FSL_DDR /* Freescale DDR driver */
-#define CONFIG_SYS_LS2_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
-#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_LS2_DDR_BLOCK1_SIZE
-#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0
-
-#define CONFIG_SYS_FSL_ESDHC_LE
-/* IFC */
-#define CONFIG_SYS_FSL_IFC_LE
-#define CONFIG_SYS_MEMAC_LITTLE_ENDIAN
-
-/* PCIe */
-#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_IMMR + 0x2400000)
-#define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_IMMR + 0x2500000)
-#define CONFIG_SYS_PCIE3_ADDR (CONFIG_SYS_IMMR + 0x2600000)
-#define CONFIG_SYS_PCIE4_ADDR (CONFIG_SYS_IMMR + 0x2700000)
-#define CONFIG_SYS_PCIE1_PHYS_ADDR 0x1000000000ULL
-#define CONFIG_SYS_PCIE2_PHYS_ADDR 0x1200000000ULL
-#define CONFIG_SYS_PCIE3_PHYS_ADDR 0x1400000000ULL
-#define CONFIG_SYS_PCIE4_PHYS_ADDR 0x1600000000ULL
-
-/* Cache Coherent Interconnect */
-#define CCI_MN_BASE 0x04000000
-#define CCI_MN_RNF_NODEID_LIST 0x180
-#define CCI_MN_DVM_DOMAIN_CTL 0x200
-#define CCI_MN_DVM_DOMAIN_CTL_SET 0x210
-
-#define CCI_RN_I_0_BASE (CCI_MN_BASE + 0x800000)
-#define CCI_RN_I_2_BASE (CCI_MN_BASE + 0x820000)
-#define CCI_RN_I_6_BASE (CCI_MN_BASE + 0x860000)
-#define CCI_RN_I_12_BASE (CCI_MN_BASE + 0x8C0000)
-#define CCI_RN_I_16_BASE (CCI_MN_BASE + 0x900000)
-#define CCI_RN_I_20_BASE (CCI_MN_BASE + 0x940000)
-
-#define CCI_S0_QOS_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x10)
-#define CCI_S1_QOS_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x110)
-#define CCI_S2_QOS_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x210)
-
-/* Device Configuration */
-#define DCFG_BASE 0x01e00000
-#define DCFG_PORSR1 0x000
-#define DCFG_PORSR1_RCW_SRC 0xff800000
-#define DCFG_PORSR1_RCW_SRC_NOR 0x12f00000
-#define DCFG_RCWSR13 0x130
-#define DCFG_RCWSR13_DSPI (0 << 8)
-
-#define DCFG_DCSR_BASE 0X700100000ULL
-#define DCFG_DCSR_PORCR1 0x000
-
-/* Supplemental Configuration */
-#define SCFG_BASE 0x01fc0000
-#define SCFG_USB3PRM1CR 0x000
-
-#ifdef CONFIG_LS2085A
-#define CONFIG_MAX_CPUS 16
-#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
-#define CONFIG_NUM_DDR_CONTROLLERS 3
-#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4, 4 }
-#define CONFIG_SYS_FSL_SRDS_1
-#define CONFIG_SYS_FSL_SRDS_2
-#else
-#error SoC not defined
-#endif
-
-#ifdef CONFIG_LS2085A
-#define CONFIG_SYS_FSL_ERRATUM_A008336
-#define CONFIG_SYS_FSL_ERRATUM_A008511
-#define CONFIG_SYS_FSL_ERRATUM_A008514
-#define CONFIG_SYS_FSL_ERRATUM_A008585
-#define CONFIG_SYS_FSL_ERRATUM_A008751
-#endif
-
-#endif /* _ASM_ARMV8_FSL_LSCH3_CONFIG_ */
diff --git a/arch/arm/include/asm/arch-fsl-lsch3/fsl_serdes.h b/arch/arm/include/asm/arch-fsl-lsch3/fsl_serdes.h
deleted file mode 100644
index 2810f3f6d90e9ba322f773d9a07b83e49f7be234..0000000000000000000000000000000000000000
--- a/arch/arm/include/asm/arch-fsl-lsch3/fsl_serdes.h
+++ /dev/null
@@ -1,67 +0,0 @@
-/*
- * Copyright 2015 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __FSL_SERDES_H
-#define __FSL_SERDES_H
-
-#include <config.h>
-
-#define SRDS_MAX_LANES 8
-
-enum srds_prtcl {
- NONE = 0,
- PCIE1,
- PCIE2,
- PCIE3,
- PCIE4,
- SATA1,
- SATA2,
- XAUI1,
- XAUI2,
- XFI1,
- XFI2,
- XFI3,
- XFI4,
- XFI5,
- XFI6,
- XFI7,
- XFI8,
- SGMII1,
- SGMII2,
- SGMII3,
- SGMII4,
- SGMII5,
- SGMII6,
- SGMII7,
- SGMII8,
- SGMII9,
- SGMII10,
- SGMII11,
- SGMII12,
- SGMII13,
- SGMII14,
- SGMII15,
- SGMII16,
- QSGMII_A, /* A indicates MACs 1-4 */
- QSGMII_B, /* B indicates MACs 5-8 */
- QSGMII_C, /* C indicates MACs 9-12 */
- QSGMII_D, /* D indicates MACs 12-16 */
- SERDES_PRCTL_COUNT
-};
-
-enum srds {
- FSL_SRDS_1 = 0,
- FSL_SRDS_2 = 1,
-};
-
-int is_serdes_configured(enum srds_prtcl device);
-void fsl_serdes_init(void);
-
-int serdes_get_first_lane(u32 sd, enum srds_prtcl device);
-enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane);
-int is_serdes_prtcl_valid(int serdes, u32 prtcl);
-
-#endif /* __FSL_SERDES_H */
diff --git a/arch/arm/include/asm/arch-fsl-lsch3/gpio.h b/arch/arm/include/asm/arch-fsl-lsch3/gpio.h
deleted file mode 100644
index f23a78c62d35dfa88f22595985f4d80dee93818c..0000000000000000000000000000000000000000
--- a/arch/arm/include/asm/arch-fsl-lsch3/gpio.h
+++ /dev/null
@@ -1,9 +0,0 @@
-/*
- * Copyright 2014, Freescale Semiconductor
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef _ASM_ARMV8_FSL_LSCH3_GPIO_H_
-#define _ASM_ARMV8_FSL_LSCH3_GPIO_H_
-#endif /* _ASM_ARMV8_FSL_LSCH3_GPIO_H_ */
diff --git a/arch/arm/include/asm/arch-fsl-lsch3/imx-regs.h b/arch/arm/include/asm/arch-fsl-lsch3/imx-regs.h
deleted file mode 100644
index 8f005353b4f59a63e6288c678137c09a09202af4..0000000000000000000000000000000000000000
--- a/arch/arm/include/asm/arch-fsl-lsch3/imx-regs.h
+++ /dev/null
@@ -1,13 +0,0 @@
-/*
- * Copyright 2014 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- *
- */
-
-#ifndef __ASM_ARCH_FSL_LSCH3_IMX_REGS_H_
-#define __ASM_ARCH_FSL_LSCH3_IMX_REGS_H_
-
-#define I2C_QUIRK_REG /* enable 8-bit driver */
-
-#endif /* __ASM_ARCH_FSL_LSCH3_IMX_REGS_H_ */
diff --git a/arch/arm/include/asm/arch-fsl-lsch3/soc.h b/arch/arm/include/asm/arch-fsl-lsch3/soc.h
deleted file mode 100644
index 9a292720721519354ee36d0c29b9c05acbd2db68..0000000000000000000000000000000000000000
--- a/arch/arm/include/asm/arch-fsl-lsch3/soc.h
+++ /dev/null
@@ -1,28 +0,0 @@
-/*
- * Copyright 2015 Freescale Semiconductor
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-struct cpu_type {
- char name[15];
- u32 soc_ver;
- u32 num_cores;
-};
-
-#define CPU_TYPE_ENTRY(n, v, nc) \
- { .name = #n, .soc_ver = SVR_##v, .num_cores = (nc)}
-
-#define SVR_WO_E 0xFFFFFE
-#define SVR_LS2045 0x870120
-#define SVR_LS2080 0x870110
-#define SVR_LS2085 0x870100
-
-#define SVR_MAJ(svr) (((svr) >> 4) & 0xf)
-#define SVR_MIN(svr) (((svr) >> 0) & 0xf)
-#define SVR_SOC_VER(svr) (((svr) >> 8) & SVR_WO_E)
-#define IS_E_PROCESSOR(svr) (!((svr >> 8) & 0x1))
-
-void fsl_lsch3_early_init_f(void);
-void cpu_name(char *name);
-
diff --git a/arch/arm/include/asm/arch-ls102xa/config.h b/arch/arm/include/asm/arch-ls102xa/config.h
index bcaf7bf2e418ddc587e23fb692c461bca1165a8e..f066480c0c546fbadf699345b4c38098d1e8d58d 100644
--- a/arch/arm/include/asm/arch-ls102xa/config.h
+++ b/arch/arm/include/asm/arch-ls102xa/config.h
@@ -79,6 +79,21 @@
#define CONFIG_SYS_PCIE2_PHYS_ADDR (CONFIG_SYS_PCIE2_PHYS_BASE + \
CONFIG_SYS_PCIE2_VIRT_ADDR)
+/* SATA */
+#define AHCI_BASE_ADDR (CONFIG_SYS_IMMR + 0x02200000)
+#define CONFIG_BOARD_LATE_INIT
+#define CONFIG_CMD_SCSI
+#define CONFIG_LIBATA
+#define CONFIG_SCSI_AHCI
+#define CONFIG_SCSI_AHCI_PLAT
+#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1
+#define CONFIG_SYS_SCSI_MAX_LUN 1
+#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
+ CONFIG_SYS_SCSI_MAX_LUN)
+#define CONFIG_CMD_FAT
+#define CONFIG_DOS_PARTITION
+#define CONFIG_SYS_FSL_ERRATUM_A008407
+
#ifdef CONFIG_DDR_SPD
#define CONFIG_SYS_FSL_DDR_BE
#define CONFIG_VERY_BIG_RAM
diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
index 60aa0d3b6f43bdf5db72c975ad5268c83de033ff..09ed9809f11606d2f3f75dce34a0d931dfef7f40 100644
--- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
+++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
@@ -144,6 +144,7 @@ struct ccsr_gur {
};
#define SCFG_ETSECDMAMCR_LE_BD_FR 0x00000c00
+#define SCFG_SNPCNFGCR_SEC_RD_WR 0xc0000000
#define SCFG_ETSECCMCR_GE2_CLK125 0x04000000
#define SCFG_ETSECCMCR_GE0_CLK125 0x00000000
#define SCFG_ETSECCMCR_GE1_CLK125 0x08000000
@@ -397,4 +398,28 @@ struct ccsr_cci400 {
u8 res_e004[0x10000 - 0xe004];
};
+/* AHCI (sata) register map */
+struct ccsr_ahci {
+ u32 res1[0xa4/4]; /* 0x0 - 0xa4 */
+ u32 pcfg; /* port config */
+ u32 ppcfg; /* port phy1 config */
+ u32 pp2c; /* port phy2 config */
+ u32 pp3c; /* port phy3 config */
+ u32 pp4c; /* port phy4 config */
+ u32 pp5c; /* port phy5 config */
+ u32 paxic; /* port AXI config */
+ u32 axicc; /* AXI cache control */
+ u32 axipc; /* AXI PROT control */
+ u32 ptc; /* port Trans Config */
+ u32 pts; /* port Trans Status */
+ u32 plc; /* port link config */
+ u32 plc1; /* port link config1 */
+ u32 plc2; /* port link config2 */
+ u32 pls; /* port link status */
+ u32 pls1; /* port link status1 */
+ u32 pcmdc; /* port CMD config */
+ u32 ppcs; /* port phy control status */
+ u32 pberr; /* port 0/1 BIST error */
+ u32 cmds; /* port 0/1 CMD status error */
+};
#endif /* __ASM_ARCH_LS102XA_IMMAP_H_ */
diff --git a/arch/arm/include/asm/arch-ls102xa/ls102xa_sata.h b/arch/arm/include/asm/arch-ls102xa/ls102xa_sata.h
new file mode 100644
index 0000000000000000000000000000000000000000..d097a6a14c2ec61554f425aea83db0d0a2d82cf0
--- /dev/null
+++ b/arch/arm/include/asm/arch-ls102xa/ls102xa_sata.h
@@ -0,0 +1,11 @@
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __FSL_SATA_H_
+#define __FSL_SATA_H_
+
+int ls1021a_sata_init(void);
+#endif
diff --git a/arch/arm/include/asm/arch-ls102xa/ns_access.h b/arch/arm/include/asm/arch-ls102xa/ns_access.h
index b53f69951ad0ccdd031d6750538b0be3342f6f55..a921fb6d14ee0d7f7b7d791fe4772cec7c998a09 100644
--- a/arch/arm/include/asm/arch-ls102xa/ns_access.h
+++ b/arch/arm/include/asm/arch-ls102xa/ns_access.h
@@ -7,22 +7,6 @@
#ifndef __FSL_NS_ACCESS_H_
#define __FSL_NS_ACCESS_H_
-enum csu_cslx_access {
- CSU_NS_SUP_R = 0x08,
- CSU_NS_SUP_W = 0x80,
- CSU_NS_SUP_RW = 0x88,
- CSU_NS_USER_R = 0x04,
- CSU_NS_USER_W = 0x40,
- CSU_NS_USER_RW = 0x44,
- CSU_S_SUP_R = 0x02,
- CSU_S_SUP_W = 0x20,
- CSU_S_SUP_RW = 0x22,
- CSU_S_USER_R = 0x01,
- CSU_S_USER_W = 0x10,
- CSU_S_USER_RW = 0x11,
- CSU_ALL_RW = 0xff,
-};
-
enum csu_cslx_ind {
CSU_CSLX_PCIE2_IO = 0,
CSU_CSLX_PCIE1_IO,
@@ -108,11 +92,88 @@ enum csu_cslx_ind {
CSU_CSLX_MAX,
};
-struct csu_ns_dev {
- unsigned long ind;
- uint32_t val;
+static struct csu_ns_dev ns_dev[] = {
+ { CSU_CSLX_PCIE2_IO, CSU_ALL_RW },
+ { CSU_CSLX_PCIE1_IO, CSU_ALL_RW },
+ { CSU_CSLX_MG2TPR_IP, CSU_ALL_RW },
+ { CSU_CSLX_IFC_MEM, CSU_ALL_RW },
+ { CSU_CSLX_OCRAM, CSU_ALL_RW },
+ { CSU_CSLX_GIC, CSU_ALL_RW },
+ { CSU_CSLX_PCIE1, CSU_ALL_RW },
+ { CSU_CSLX_OCRAM2, CSU_ALL_RW },
+ { CSU_CSLX_QSPI_MEM, CSU_ALL_RW },
+ { CSU_CSLX_PCIE2, CSU_ALL_RW },
+ { CSU_CSLX_SATA, CSU_ALL_RW },
+ { CSU_CSLX_USB3, CSU_ALL_RW },
+ { CSU_CSLX_SERDES, CSU_ALL_RW },
+ { CSU_CSLX_QDMA, CSU_ALL_RW },
+ { CSU_CSLX_LPUART2, CSU_ALL_RW },
+ { CSU_CSLX_LPUART1, CSU_ALL_RW },
+ { CSU_CSLX_LPUART4, CSU_ALL_RW },
+ { CSU_CSLX_LPUART3, CSU_ALL_RW },
+ { CSU_CSLX_LPUART6, CSU_ALL_RW },
+ { CSU_CSLX_LPUART5, CSU_ALL_RW },
+ { CSU_CSLX_DSPI2, CSU_ALL_RW },
+ { CSU_CSLX_DSPI1, CSU_ALL_RW },
+ { CSU_CSLX_QSPI, CSU_ALL_RW },
+ { CSU_CSLX_ESDHC, CSU_ALL_RW },
+ { CSU_CSLX_2D_ACE, CSU_ALL_RW },
+ { CSU_CSLX_IFC, CSU_ALL_RW },
+ { CSU_CSLX_I2C1, CSU_ALL_RW },
+ { CSU_CSLX_USB2, CSU_ALL_RW },
+ { CSU_CSLX_I2C3, CSU_ALL_RW },
+ { CSU_CSLX_I2C2, CSU_ALL_RW },
+ { CSU_CSLX_DUART2, CSU_ALL_RW },
+ { CSU_CSLX_DUART1, CSU_ALL_RW },
+ { CSU_CSLX_WDT2, CSU_ALL_RW },
+ { CSU_CSLX_WDT1, CSU_ALL_RW },
+ { CSU_CSLX_EDMA, CSU_ALL_RW },
+ { CSU_CSLX_SYS_CNT, CSU_ALL_RW },
+ { CSU_CSLX_DMA_MUX2, CSU_ALL_RW },
+ { CSU_CSLX_DMA_MUX1, CSU_ALL_RW },
+ { CSU_CSLX_DDR, CSU_ALL_RW },
+ { CSU_CSLX_QUICC, CSU_ALL_RW },
+ { CSU_CSLX_DCFG_CCU_RCPM, CSU_ALL_RW },
+ { CSU_CSLX_SECURE_BOOTROM, CSU_ALL_RW },
+ { CSU_CSLX_SFP, CSU_ALL_RW },
+ { CSU_CSLX_TMU, CSU_ALL_RW },
+ { CSU_CSLX_SECURE_MONITOR, CSU_ALL_RW },
+ { CSU_CSLX_RESERVED0, CSU_ALL_RW },
+ { CSU_CSLX_ETSEC1, CSU_ALL_RW },
+ { CSU_CSLX_SEC5_5, CSU_ALL_RW },
+ { CSU_CSLX_ETSEC3, CSU_ALL_RW },
+ { CSU_CSLX_ETSEC2, CSU_ALL_RW },
+ { CSU_CSLX_GPIO2, CSU_ALL_RW },
+ { CSU_CSLX_GPIO1, CSU_ALL_RW },
+ { CSU_CSLX_GPIO4, CSU_ALL_RW },
+ { CSU_CSLX_GPIO3, CSU_ALL_RW },
+ { CSU_CSLX_PLATFORM_CONT, CSU_ALL_RW },
+ { CSU_CSLX_CSU, CSU_ALL_RW },
+ { CSU_CSLX_ASRC, CSU_ALL_RW },
+ { CSU_CSLX_SPDIF, CSU_ALL_RW },
+ { CSU_CSLX_FLEXCAN2, CSU_ALL_RW },
+ { CSU_CSLX_FLEXCAN1, CSU_ALL_RW },
+ { CSU_CSLX_FLEXCAN4, CSU_ALL_RW },
+ { CSU_CSLX_FLEXCAN3, CSU_ALL_RW },
+ { CSU_CSLX_SAI2, CSU_ALL_RW },
+ { CSU_CSLX_SAI1, CSU_ALL_RW },
+ { CSU_CSLX_SAI4, CSU_ALL_RW },
+ { CSU_CSLX_SAI3, CSU_ALL_RW },
+ { CSU_CSLX_FTM2, CSU_ALL_RW },
+ { CSU_CSLX_FTM1, CSU_ALL_RW },
+ { CSU_CSLX_FTM4, CSU_ALL_RW },
+ { CSU_CSLX_FTM3, CSU_ALL_RW },
+ { CSU_CSLX_FTM6, CSU_ALL_RW },
+ { CSU_CSLX_FTM5, CSU_ALL_RW },
+ { CSU_CSLX_FTM8, CSU_ALL_RW },
+ { CSU_CSLX_FTM7, CSU_ALL_RW },
+ { CSU_CSLX_COP_DCSR, CSU_ALL_RW },
+ { CSU_CSLX_EPU, CSU_ALL_RW },
+ { CSU_CSLX_GDI, CSU_ALL_RW },
+ { CSU_CSLX_DDI, CSU_ALL_RW },
+ { CSU_CSLX_RESERVED1, CSU_ALL_RW },
+ { CSU_CSLX_USB3_PHY, CSU_ALL_RW },
+ { CSU_CSLX_RESERVED2, CSU_ALL_RW },
};
-void enable_devices_ns_access(struct csu_ns_dev *ns_dev, uint32_t num);
-
#endif
diff --git a/arch/arm/include/asm/armv8/mmu.h b/arch/arm/include/asm/armv8/mmu.h
index 587ee39909917d272d788d1cc81b7f68cae96faa..d8d9af45db4f186a528bf56e90ffda51f05775f4 100644
--- a/arch/arm/include/asm/armv8/mmu.h
+++ b/arch/arm/include/asm/armv8/mmu.h
@@ -65,6 +65,7 @@
/*
* Section
*/
+#define PMD_SECT_NS (1 << 5)
#define PMD_SECT_NON_SHARE (0 << 8)
#define PMD_SECT_OUTER_SHARE (2 << 8)
#define PMD_SECT_INNER_SHARE (3 << 8)
diff --git a/arch/arm/include/asm/config.h b/arch/arm/include/asm/config.h
index 22fff02778f0e7cecdf163a6e9bd6f4026c2e3cc..435fc4521c2e1198ba49f13d8c5cc743236e0a2b 100644
--- a/arch/arm/include/asm/config.h
+++ b/arch/arm/include/asm/config.h
@@ -15,14 +15,11 @@
#define CONFIG_STATIC_RELA
#endif
-#ifdef CONFIG_FSL_LSCH3
-#include <asm/arch-fsl-lsch3/config.h>
-#endif
-
#if defined(CONFIG_LS102XA) || \
defined(CONFIG_CPU_PXA27X) || \
defined(CONFIG_CPU_MONAHANS) || \
- defined(CONFIG_CPU_PXA25X)
+ defined(CONFIG_CPU_PXA25X) || \
+ defined(CONFIG_FSL_LAYERSCAPE)
#include <asm/arch/config.h>
#endif
diff --git a/arch/arm/include/asm/io.h b/arch/arm/include/asm/io.h
index bfbe0a0988b47b2eafc636ca238f35087d7a5e5f..75773bdbe079701026986037f3bc019c5fc45b12 100644
--- a/arch/arm/include/asm/io.h
+++ b/arch/arm/include/asm/io.h
@@ -46,7 +46,7 @@ static inline void sync(void)
static inline void *
map_physmem(phys_addr_t paddr, unsigned long len, unsigned long flags)
{
- return (void *)paddr;
+ return (void *)((unsigned long)paddr);
}
/*
@@ -59,7 +59,7 @@ static inline void unmap_physmem(void *vaddr, unsigned long flags)
static inline phys_addr_t virt_to_phys(void * vaddr)
{
- return (phys_addr_t)(vaddr);
+ return (phys_addr_t)((unsigned long)vaddr);
}
/*
diff --git a/arch/arm/include/asm/types.h b/arch/arm/include/asm/types.h
index ee77c4179f1aa04c24d37944b870c69ddebb13c3..388058e04c5b88a3aa62a22dc54dc3634a4cc65f 100644
--- a/arch/arm/include/asm/types.h
+++ b/arch/arm/include/asm/types.h
@@ -45,12 +45,16 @@ typedef unsigned long long u64;
#define BITS_PER_LONG 32
#endif /* CONFIG_ARM64 */
-/* Dma addresses are 32-bits wide. */
-
+#ifdef CONFIG_PHYS_64BIT
+typedef unsigned long long dma_addr_t;
+typedef unsigned long long phys_addr_t;
+typedef unsigned long long phys_size_t;
+#else
+/* DMA addresses are 32-bits wide */
typedef u32 dma_addr_t;
-
typedef unsigned long phys_addr_t;
typedef unsigned long phys_size_t;
+#endif
#endif /* __KERNEL__ */
diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h
index 0c9d85ec9669fd2fcf6c1aa9377c78fe242f7580..101b8db0ee455d97593c9fc8b51edeb3bfa9a0f3 100644
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -19,7 +19,7 @@
#include <fsl_sec.h>
#include <fsl_sfp.h>
#include <asm/fsl_lbc.h>
-#include <asm/fsl_fman.h>
+#include <fsl_fman.h>
#include <fsl_immap.h>
typedef struct ccsr_local {
diff --git a/board/freescale/b4860qds/eth_b4860qds.c b/board/freescale/b4860qds/eth_b4860qds.c
index 501d4b3aff5d62a412b4180443e995e2b1f6021e..df90476a772c1ca8f97ee8fcae731970019be00c 100644
--- a/board/freescale/b4860qds/eth_b4860qds.c
+++ b/board/freescale/b4860qds/eth_b4860qds.c
@@ -26,7 +26,7 @@
#include <fsl_mdio.h>
#include <malloc.h>
#include <fdt_support.h>
-#include <asm/fsl_dtsec.h>
+#include <fsl_dtsec.h>
#include "../common/ngpixis.h"
#include "../common/fman.h"
diff --git a/board/freescale/common/Makefile b/board/freescale/common/Makefile
index 87d05780fe08701d6a36fa0f6b146b791c0fc35c..51d2814a434dd515fede2063f9b4607ca3accfe4 100644
--- a/board/freescale/common/Makefile
+++ b/board/freescale/common/Makefile
@@ -71,7 +71,7 @@ obj-$(CONFIG_P4080DS) += p_corenet/
obj-$(CONFIG_P5020DS) += p_corenet/
obj-$(CONFIG_P5040DS) += p_corenet/
-obj-$(CONFIG_LS102XA_NS_ACCESS) += ns_access.o
+obj-$(CONFIG_LAYERSCAPE_NS_ACCESS) += ns_access.o
ifdef CONFIG_SECURE_BOOT
obj-$(CONFIG_CMD_ESBC_VALIDATE) += fsl_validate.o cmd_esbc_validate.o
diff --git a/board/freescale/common/arm_sleep.c b/board/freescale/common/arm_sleep.c
index 8e8b7fa204ffa9ab2dd85b6f3f68bba8c3623a41..a498c65f040d35ff1172d9f109fe03fef754ccaf 100644
--- a/board/freescale/common/arm_sleep.c
+++ b/board/freescale/common/arm_sleep.c
@@ -12,7 +12,6 @@
#include <asm/secure.h>
#endif
#include <asm/armv7.h>
-#include <asm/cache.h>
#if defined(CONFIG_LS102XA)
#include <asm/arch/immap_ls102xa.h>
@@ -65,8 +64,6 @@ static void dp_ddr_restore(void)
for (i = 0; i < DDR_BUFF_LEN / 8; i++)
*dst++ = *src++;
-
- flush_dcache_all();
}
static void dp_resume_prepare(void)
@@ -74,7 +71,6 @@ static void dp_resume_prepare(void)
dp_ddr_restore();
board_sleep_prepare();
armv7_init_nonsec();
- cleanup_before_linux();
#ifdef CONFIG_U_QE
u_qe_resume();
#endif
diff --git a/board/freescale/common/fman.c b/board/freescale/common/fman.c
index 9dc540211e41b88ad300b9849fe7236c70707808..26cf5175c77f757b289b9a360f5cc54278c46db1 100644
--- a/board/freescale/common/fman.c
+++ b/board/freescale/common/fman.c
@@ -1,5 +1,5 @@
/*
- * Copyright 2011 Freescale Semiconductor, Inc.
+ * Copyright 2011-2015 Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
@@ -10,7 +10,11 @@
#include <fdt_support.h>
#include <fm_eth.h>
+#ifdef CONFIG_FSL_LAYERSCAPE
+#include <asm/arch/fsl_serdes.h>
+#else
#include <asm/fsl_serdes.h>
+#endif
/*
* Given the following ...
diff --git a/board/freescale/common/fsl_validate.c b/board/freescale/common/fsl_validate.c
index 5283648a4d090df468b3487603ce542a109aa396..73b6718db9c869b42970de161424210f12f10f07 100644
--- a/board/freescale/common/fsl_validate.c
+++ b/board/freescale/common/fsl_validate.c
@@ -63,12 +63,12 @@ static u32 check_ie(struct fsl_secboot_img_priv *img)
* address
*/
#if defined(CONFIG_MPC85xx)
-int get_csf_base_addr(ulong *csf_addr, ulong *flash_base_addr)
+int get_csf_base_addr(u32 *csf_addr, u32 *flash_base_addr)
{
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
u32 csf_hdr_addr = in_be32(&gur->scratchrw[0]);
u32 csf_flash_offset = csf_hdr_addr & ~(CONFIG_SYS_PBI_FLASH_BASE);
- ulong flash_addr, addr;
+ u32 flash_addr, addr;
int found = 0;
int i = 0;
@@ -76,7 +76,7 @@ int get_csf_base_addr(ulong *csf_addr, ulong *flash_base_addr)
flash_addr = flash_info[i].start[0];
addr = flash_info[i].start[0] + csf_flash_offset;
if (memcmp((u8 *)addr, barker_code, ESBC_BARKER_LEN) == 0) {
- debug("Barker found on addr %lx\n", addr);
+ debug("Barker found on addr %x\n", addr);
found = 1;
break;
}
@@ -94,7 +94,7 @@ int get_csf_base_addr(ulong *csf_addr, ulong *flash_base_addr)
/* For platforms like LS1020, correct flash address is present in
* the header. So the function reqturns flash base address as 0
*/
-int get_csf_base_addr(ulong *csf_addr, ulong *flash_base_addr)
+int get_csf_base_addr(u32 *csf_addr, u32 *flash_base_addr)
{
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
u32 csf_hdr_addr = in_be32(&gur->scratchrw[0]);
@@ -108,11 +108,11 @@ int get_csf_base_addr(ulong *csf_addr, ulong *flash_base_addr)
}
#endif
-static int get_ie_info_addr(ulong *ie_addr)
+static int get_ie_info_addr(u32 *ie_addr)
{
struct fsl_secboot_img_hdr *hdr;
struct fsl_secboot_sg_table *sg_tbl;
- ulong flash_base_addr, csf_addr;
+ u32 flash_base_addr, csf_addr;
if (get_csf_base_addr(&csf_addr, &flash_base_addr))
return -1;
@@ -127,11 +127,11 @@ static int get_ie_info_addr(ulong *ie_addr)
*/
#if defined(CONFIG_FSL_TRUST_ARCH_v1) && defined(CONFIG_FSL_CORENET)
sg_tbl = (struct fsl_secboot_sg_table *)
- (((ulong)hdr->psgtable & ~(CONFIG_SYS_PBI_FLASH_BASE)) +
+ (((u32)hdr->psgtable & ~(CONFIG_SYS_PBI_FLASH_BASE)) +
flash_base_addr);
#else
sg_tbl = (struct fsl_secboot_sg_table *)(csf_addr +
- (ulong)hdr->psgtable);
+ (u32)hdr->psgtable);
#endif
/* IE Key Table is the first entry in the SG Table */
@@ -142,7 +142,7 @@ static int get_ie_info_addr(ulong *ie_addr)
*ie_addr = sg_tbl->src_addr;
#endif
- debug("IE Table address is %lx\n", *ie_addr);
+ debug("IE Table address is %x\n", *ie_addr);
return 0;
}
@@ -246,7 +246,7 @@ static void fsl_secboot_image_verification_failure(void)
struct ccsr_sfp_regs *sfp_regs = (void *)(CONFIG_SYS_SFP_ADDR);
u32 sts = sec_mon_in32(&sec_mon_regs->hp_stat);
- u32 its = sfp_in32(&sfp_regs->ospr) & ITS_MASK >> ITS_BIT;
+ u32 its = (sfp_in32(&sfp_regs->ospr) & ITS_MASK) >> ITS_BIT;
/*
* Read the SEC_MON status register
@@ -549,7 +549,7 @@ static int read_validate_esbc_client_header(struct fsl_secboot_img_priv *img)
if (memcmp(hdr->barker, barker_code, ESBC_BARKER_LEN))
return ERROR_ESBC_CLIENT_HEADER_BARKER;
- sprintf(buf, "%p", hdr->pimg);
+ sprintf(buf, "%x", hdr->pimg);
setenv("img_addr", buf);
if (!hdr->img_size)
diff --git a/board/freescale/common/ns_access.c b/board/freescale/common/ns_access.c
index d7de9822d031ee0a2eba26530043fe5db94ec389..d8d16c520f8234468c8a8f3c7dbe1638c6f70743 100644
--- a/board/freescale/common/ns_access.c
+++ b/board/freescale/common/ns_access.c
@@ -6,9 +6,10 @@
#include <common.h>
#include <asm/io.h>
+#include <fsl_csu.h>
#include <asm/arch/ns_access.h>
-void enable_devices_ns_access(struct csu_ns_dev *ns_dev, uint32_t num)
+static void enable_devices_ns_access(struct csu_ns_dev *ns_dev, uint32_t num)
{
u32 *base = (u32 *)CONFIG_SYS_FSL_CSU_ADDR;
u32 *reg;
@@ -28,3 +29,8 @@ void enable_devices_ns_access(struct csu_ns_dev *ns_dev, uint32_t num)
out_be32(reg, val);
}
}
+
+void enable_layerscape_ns_access(void)
+{
+ enable_devices_ns_access(ns_dev, ARRAY_SIZE(ns_dev));
+}
diff --git a/board/freescale/corenet_ds/eth_hydra.c b/board/freescale/corenet_ds/eth_hydra.c
index 396103f9906e1b3b67d3138bdae3d30028e05eee..172a55b9883bff1245bcc3fbea5918f40b2ec6c3 100644
--- a/board/freescale/corenet_ds/eth_hydra.c
+++ b/board/freescale/corenet_ds/eth_hydra.c
@@ -55,7 +55,7 @@
#include <fsl_mdio.h>
#include <malloc.h>
#include <fdt_support.h>
-#include <asm/fsl_dtsec.h>
+#include <fsl_dtsec.h>
#include "../common/ngpixis.h"
#include "../common/fman.h"
diff --git a/board/freescale/corenet_ds/eth_p4080.c b/board/freescale/corenet_ds/eth_p4080.c
index 5cbec7f5f269a7e5b56e97dc0eeed8f5bdcdaaaa..c68dc2c246562c9d61c9255ae3b1e5a7dd02664e 100644
--- a/board/freescale/corenet_ds/eth_p4080.c
+++ b/board/freescale/corenet_ds/eth_p4080.c
@@ -24,7 +24,7 @@
#include "../common/ngpixis.h"
#include "../common/fman.h"
-#include <asm/fsl_dtsec.h>
+#include <fsl_dtsec.h>
#define EMI_NONE 0xffffffff
#define EMI_MASK 0xf0000000
diff --git a/board/freescale/corenet_ds/eth_superhydra.c b/board/freescale/corenet_ds/eth_superhydra.c
index ad1bffd74bfc76fdd06a07cfc9742408d109b47f..62b163580b2d38fbb7b2350f5a4aea2694da0696 100644
--- a/board/freescale/corenet_ds/eth_superhydra.c
+++ b/board/freescale/corenet_ds/eth_superhydra.c
@@ -55,7 +55,7 @@
#include <fsl_mdio.h>
#include <malloc.h>
#include <fdt_support.h>
-#include <asm/fsl_dtsec.h>
+#include <fsl_dtsec.h>
#include "../common/ngpixis.h"
#include "../common/fman.h"
diff --git a/board/freescale/ls1021aqds/ls1021aqds.c b/board/freescale/ls1021aqds/ls1021aqds.c
index 655fc644fe90e036578cd37b3e177df6050392af..d889ad50fd04d83d88197234c9fc70f6d0ac35bd 100644
--- a/board/freescale/ls1021aqds/ls1021aqds.c
+++ b/board/freescale/ls1021aqds/ls1021aqds.c
@@ -8,13 +8,14 @@
#include <i2c.h>
#include <asm/io.h>
#include <asm/arch/immap_ls102xa.h>
-#include <asm/arch/ns_access.h>
#include <asm/arch/clock.h>
#include <asm/arch/fsl_serdes.h>
#include <asm/arch/ls102xa_stream_id.h>
#include <asm/arch/ls102xa_devdis.h>
+#include <asm/arch/ls102xa_sata.h>
#include <hwconfig.h>
#include <mmc.h>
+#include <fsl_csu.h>
#include <fsl_esdhc.h>
#include <fsl_ifc.h>
#include <fsl_sec.h>
@@ -56,92 +57,6 @@ enum {
GE1_CLK125,
};
-#ifdef CONFIG_LS102XA_NS_ACCESS
-static struct csu_ns_dev ns_dev[] = {
- { CSU_CSLX_PCIE2_IO, CSU_ALL_RW },
- { CSU_CSLX_PCIE1_IO, CSU_ALL_RW },
- { CSU_CSLX_MG2TPR_IP, CSU_ALL_RW },
- { CSU_CSLX_IFC_MEM, CSU_ALL_RW },
- { CSU_CSLX_OCRAM, CSU_ALL_RW },
- { CSU_CSLX_GIC, CSU_ALL_RW },
- { CSU_CSLX_PCIE1, CSU_ALL_RW },
- { CSU_CSLX_OCRAM2, CSU_ALL_RW },
- { CSU_CSLX_QSPI_MEM, CSU_ALL_RW },
- { CSU_CSLX_PCIE2, CSU_ALL_RW },
- { CSU_CSLX_SATA, CSU_ALL_RW },
- { CSU_CSLX_USB3, CSU_ALL_RW },
- { CSU_CSLX_SERDES, CSU_ALL_RW },
- { CSU_CSLX_QDMA, CSU_ALL_RW },
- { CSU_CSLX_LPUART2, CSU_ALL_RW },
- { CSU_CSLX_LPUART1, CSU_ALL_RW },
- { CSU_CSLX_LPUART4, CSU_ALL_RW },
- { CSU_CSLX_LPUART3, CSU_ALL_RW },
- { CSU_CSLX_LPUART6, CSU_ALL_RW },
- { CSU_CSLX_LPUART5, CSU_ALL_RW },
- { CSU_CSLX_DSPI2, CSU_ALL_RW },
- { CSU_CSLX_DSPI1, CSU_ALL_RW },
- { CSU_CSLX_QSPI, CSU_ALL_RW },
- { CSU_CSLX_ESDHC, CSU_ALL_RW },
- { CSU_CSLX_2D_ACE, CSU_ALL_RW },
- { CSU_CSLX_IFC, CSU_ALL_RW },
- { CSU_CSLX_I2C1, CSU_ALL_RW },
- { CSU_CSLX_USB2, CSU_ALL_RW },
- { CSU_CSLX_I2C3, CSU_ALL_RW },
- { CSU_CSLX_I2C2, CSU_ALL_RW },
- { CSU_CSLX_DUART2, CSU_ALL_RW },
- { CSU_CSLX_DUART1, CSU_ALL_RW },
- { CSU_CSLX_WDT2, CSU_ALL_RW },
- { CSU_CSLX_WDT1, CSU_ALL_RW },
- { CSU_CSLX_EDMA, CSU_ALL_RW },
- { CSU_CSLX_SYS_CNT, CSU_ALL_RW },
- { CSU_CSLX_DMA_MUX2, CSU_ALL_RW },
- { CSU_CSLX_DMA_MUX1, CSU_ALL_RW },
- { CSU_CSLX_DDR, CSU_ALL_RW },
- { CSU_CSLX_QUICC, CSU_ALL_RW },
- { CSU_CSLX_DCFG_CCU_RCPM, CSU_ALL_RW },
- { CSU_CSLX_SECURE_BOOTROM, CSU_ALL_RW },
- { CSU_CSLX_SFP, CSU_ALL_RW },
- { CSU_CSLX_TMU, CSU_ALL_RW },
- { CSU_CSLX_SECURE_MONITOR, CSU_ALL_RW },
- { CSU_CSLX_RESERVED0, CSU_ALL_RW },
- { CSU_CSLX_ETSEC1, CSU_ALL_RW },
- { CSU_CSLX_SEC5_5, CSU_ALL_RW },
- { CSU_CSLX_ETSEC3, CSU_ALL_RW },
- { CSU_CSLX_ETSEC2, CSU_ALL_RW },
- { CSU_CSLX_GPIO2, CSU_ALL_RW },
- { CSU_CSLX_GPIO1, CSU_ALL_RW },
- { CSU_CSLX_GPIO4, CSU_ALL_RW },
- { CSU_CSLX_GPIO3, CSU_ALL_RW },
- { CSU_CSLX_PLATFORM_CONT, CSU_ALL_RW },
- { CSU_CSLX_CSU, CSU_ALL_RW },
- { CSU_CSLX_ASRC, CSU_ALL_RW },
- { CSU_CSLX_SPDIF, CSU_ALL_RW },
- { CSU_CSLX_FLEXCAN2, CSU_ALL_RW },
- { CSU_CSLX_FLEXCAN1, CSU_ALL_RW },
- { CSU_CSLX_FLEXCAN4, CSU_ALL_RW },
- { CSU_CSLX_FLEXCAN3, CSU_ALL_RW },
- { CSU_CSLX_SAI2, CSU_ALL_RW },
- { CSU_CSLX_SAI1, CSU_ALL_RW },
- { CSU_CSLX_SAI4, CSU_ALL_RW },
- { CSU_CSLX_SAI3, CSU_ALL_RW },
- { CSU_CSLX_FTM2, CSU_ALL_RW },
- { CSU_CSLX_FTM1, CSU_ALL_RW },
- { CSU_CSLX_FTM4, CSU_ALL_RW },
- { CSU_CSLX_FTM3, CSU_ALL_RW },
- { CSU_CSLX_FTM6, CSU_ALL_RW },
- { CSU_CSLX_FTM5, CSU_ALL_RW },
- { CSU_CSLX_FTM8, CSU_ALL_RW },
- { CSU_CSLX_FTM7, CSU_ALL_RW },
- { CSU_CSLX_COP_DCSR, CSU_ALL_RW },
- { CSU_CSLX_EPU, CSU_ALL_RW },
- { CSU_CSLX_GDI, CSU_ALL_RW },
- { CSU_CSLX_DDI, CSU_ALL_RW },
- { CSU_CSLX_RESERVED1, CSU_ALL_RW },
- { CSU_CSLX_USB3_PHY, CSU_ALL_RW },
- { CSU_CSLX_RESERVED2, CSU_ALL_RW },
-};
-#endif
-
int checkboard(void)
{
#ifndef CONFIG_QSPI_BOOT
@@ -382,9 +297,8 @@ void board_init_f(ulong dummy)
dram_init();
/* Allow OCRAM access permission as R/W */
-#ifdef CONFIG_LS102XA_NS_ACCESS
- enable_devices_ns_access(&ns_dev[4], 1);
- enable_devices_ns_access(&ns_dev[7], 1);
+#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
+ enable_layerscape_ns_access();
#endif
board_init_r(NULL, 0);
@@ -494,6 +408,17 @@ int config_serdes_mux(void)
return 0;
}
+#ifdef CONFIG_BOARD_LATE_INIT
+int board_late_init(void)
+{
+#ifdef CONFIG_SCSI_AHCI_PLAT
+ ls1021a_sata_init();
+#endif
+
+ return 0;
+}
+#endif
+
int misc_init_r(void)
{
int conflict_flag;
@@ -602,8 +527,8 @@ int board_init(void)
ls102xa_config_smmu_stream_id(dev_stream_id,
ARRAY_SIZE(dev_stream_id));
-#ifdef CONFIG_LS102XA_NS_ACCESS
- enable_devices_ns_access(ns_dev, ARRAY_SIZE(ns_dev));
+#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
+ enable_layerscape_ns_access();
#endif
#ifdef CONFIG_U_QE
@@ -627,8 +552,8 @@ void board_sleep_prepare(void)
}
-#ifdef CONFIG_LS102XA_NS_ACCESS
- enable_devices_ns_access(ns_dev, ARRAY_SIZE(ns_dev));
+#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
+ enable_layerscape_ns_access();
#endif
}
#endif
diff --git a/board/freescale/ls1021atwr/MAINTAINERS b/board/freescale/ls1021atwr/MAINTAINERS
index e9f6f0a973a15ea6761a734b4690a0b3b028eb79..b997bb00eceda03316539a41376017dd12f1af58 100644
--- a/board/freescale/ls1021atwr/MAINTAINERS
+++ b/board/freescale/ls1021atwr/MAINTAINERS
@@ -6,5 +6,6 @@ F: include/configs/ls1021atwr.h
F: configs/ls1021atwr_nor_defconfig
F: configs/ls1021atwr_nor_SECURE_BOOT_defconfig
F: configs/ls1021atwr_nor_lpuart_defconfig
-F: configs/ls1021atwr_sdcard_defconfig
+F: configs/ls1021atwr_sdcard_ifc_defconfig
+F: configs/ls1021atwr_sdcard_qspi_defconfig
F: configs/ls1021atwr_qspi_defconfig
diff --git a/board/freescale/ls1021atwr/ls1021atwr.c b/board/freescale/ls1021atwr/ls1021atwr.c
index 228dbf81bb25eba2c2758f39836ee61778d38467..4918c1192e2bd268cd6fd748853971445c049c77 100644
--- a/board/freescale/ls1021atwr/ls1021atwr.c
+++ b/board/freescale/ls1021atwr/ls1021atwr.c
@@ -8,13 +8,14 @@
#include <i2c.h>
#include <asm/io.h>
#include <asm/arch/immap_ls102xa.h>
-#include <asm/arch/ns_access.h>
#include <asm/arch/clock.h>
#include <asm/arch/fsl_serdes.h>
#include <asm/arch/ls102xa_stream_id.h>
#include <asm/arch/ls102xa_devdis.h>
+#include <asm/arch/ls102xa_sata.h>
#include <hwconfig.h>
#include <mmc.h>
+#include <fsl_csu.h>
#include <fsl_esdhc.h>
#include <fsl_ifc.h>
#include <fsl_immap.h>
@@ -69,92 +70,6 @@ DECLARE_GLOBAL_DATA_PTR;
#define PIN_QE_LCD_MUX_LCD 0x0
#define PIN_QE_LCD_MUX_QE 0x1
-#ifdef CONFIG_LS102XA_NS_ACCESS
-static struct csu_ns_dev ns_dev[] = {
- { CSU_CSLX_PCIE2_IO, CSU_ALL_RW },
- { CSU_CSLX_PCIE1_IO, CSU_ALL_RW },
- { CSU_CSLX_MG2TPR_IP, CSU_ALL_RW },
- { CSU_CSLX_IFC_MEM, CSU_ALL_RW },
- { CSU_CSLX_OCRAM, CSU_ALL_RW },
- { CSU_CSLX_GIC, CSU_ALL_RW },
- { CSU_CSLX_PCIE1, CSU_ALL_RW },
- { CSU_CSLX_OCRAM2, CSU_ALL_RW },
- { CSU_CSLX_QSPI_MEM, CSU_ALL_RW },
- { CSU_CSLX_PCIE2, CSU_ALL_RW },
- { CSU_CSLX_SATA, CSU_ALL_RW },
- { CSU_CSLX_USB3, CSU_ALL_RW },
- { CSU_CSLX_SERDES, CSU_ALL_RW },
- { CSU_CSLX_QDMA, CSU_ALL_RW },
- { CSU_CSLX_LPUART2, CSU_ALL_RW },
- { CSU_CSLX_LPUART1, CSU_ALL_RW },
- { CSU_CSLX_LPUART4, CSU_ALL_RW },
- { CSU_CSLX_LPUART3, CSU_ALL_RW },
- { CSU_CSLX_LPUART6, CSU_ALL_RW },
- { CSU_CSLX_LPUART5, CSU_ALL_RW },
- { CSU_CSLX_DSPI2, CSU_ALL_RW },
- { CSU_CSLX_DSPI1, CSU_ALL_RW },
- { CSU_CSLX_QSPI, CSU_ALL_RW },
- { CSU_CSLX_ESDHC, CSU_ALL_RW },
- { CSU_CSLX_2D_ACE, CSU_ALL_RW },
- { CSU_CSLX_IFC, CSU_ALL_RW },
- { CSU_CSLX_I2C1, CSU_ALL_RW },
- { CSU_CSLX_USB2, CSU_ALL_RW },
- { CSU_CSLX_I2C3, CSU_ALL_RW },
- { CSU_CSLX_I2C2, CSU_ALL_RW },
- { CSU_CSLX_DUART2, CSU_ALL_RW },
- { CSU_CSLX_DUART1, CSU_ALL_RW },
- { CSU_CSLX_WDT2, CSU_ALL_RW },
- { CSU_CSLX_WDT1, CSU_ALL_RW },
- { CSU_CSLX_EDMA, CSU_ALL_RW },
- { CSU_CSLX_SYS_CNT, CSU_ALL_RW },
- { CSU_CSLX_DMA_MUX2, CSU_ALL_RW },
- { CSU_CSLX_DMA_MUX1, CSU_ALL_RW },
- { CSU_CSLX_DDR, CSU_ALL_RW },
- { CSU_CSLX_QUICC, CSU_ALL_RW },
- { CSU_CSLX_DCFG_CCU_RCPM, CSU_ALL_RW },
- { CSU_CSLX_SECURE_BOOTROM, CSU_ALL_RW },
- { CSU_CSLX_SFP, CSU_ALL_RW },
- { CSU_CSLX_TMU, CSU_ALL_RW },
- { CSU_CSLX_SECURE_MONITOR, CSU_ALL_RW },
- { CSU_CSLX_RESERVED0, CSU_ALL_RW },
- { CSU_CSLX_ETSEC1, CSU_ALL_RW },
- { CSU_CSLX_SEC5_5, CSU_ALL_RW },
- { CSU_CSLX_ETSEC3, CSU_ALL_RW },
- { CSU_CSLX_ETSEC2, CSU_ALL_RW },
- { CSU_CSLX_GPIO2, CSU_ALL_RW },
- { CSU_CSLX_GPIO1, CSU_ALL_RW },
- { CSU_CSLX_GPIO4, CSU_ALL_RW },
- { CSU_CSLX_GPIO3, CSU_ALL_RW },
- { CSU_CSLX_PLATFORM_CONT, CSU_ALL_RW },
- { CSU_CSLX_CSU, CSU_ALL_RW },
- { CSU_CSLX_ASRC, CSU_ALL_RW },
- { CSU_CSLX_SPDIF, CSU_ALL_RW },
- { CSU_CSLX_FLEXCAN2, CSU_ALL_RW },
- { CSU_CSLX_FLEXCAN1, CSU_ALL_RW },
- { CSU_CSLX_FLEXCAN4, CSU_ALL_RW },
- { CSU_CSLX_FLEXCAN3, CSU_ALL_RW },
- { CSU_CSLX_SAI2, CSU_ALL_RW },
- { CSU_CSLX_SAI1, CSU_ALL_RW },
- { CSU_CSLX_SAI4, CSU_ALL_RW },
- { CSU_CSLX_SAI3, CSU_ALL_RW },
- { CSU_CSLX_FTM2, CSU_ALL_RW },
- { CSU_CSLX_FTM1, CSU_ALL_RW },
- { CSU_CSLX_FTM4, CSU_ALL_RW },
- { CSU_CSLX_FTM3, CSU_ALL_RW },
- { CSU_CSLX_FTM6, CSU_ALL_RW },
- { CSU_CSLX_FTM5, CSU_ALL_RW },
- { CSU_CSLX_FTM8, CSU_ALL_RW },
- { CSU_CSLX_FTM7, CSU_ALL_RW },
- { CSU_CSLX_COP_DCSR, CSU_ALL_RW },
- { CSU_CSLX_EPU, CSU_ALL_RW },
- { CSU_CSLX_GDI, CSU_ALL_RW },
- { CSU_CSLX_DDI, CSU_ALL_RW },
- { CSU_CSLX_RESERVED1, CSU_ALL_RW },
- { CSU_CSLX_USB3_PHY, CSU_ALL_RW },
- { CSU_CSLX_RESERVED2, CSU_ALL_RW },
-};
-#endif
-
struct cpld_data {
u8 cpld_ver; /* cpld revision */
u8 cpld_ver_sub; /* cpld sub revision */
@@ -175,7 +90,7 @@ struct cpld_data {
u8 rev2; /* Reserved */
};
-#ifndef CONFIG_QSPI_BOOT
+#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
static void convert_serdes_mux(int type, int need_reset);
void cpld_show(void)
@@ -216,7 +131,7 @@ void cpld_show(void)
int checkboard(void)
{
puts("Board: LS1021ATWR\n");
-#ifndef CONFIG_QSPI_BOOT
+#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
cpld_show();
#endif
@@ -380,7 +295,7 @@ int board_eth_init(bd_t *bis)
}
#endif
-#ifndef CONFIG_QSPI_BOOT
+#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
int config_serdes_mux(void)
{
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
@@ -414,7 +329,7 @@ int config_serdes_mux(void)
}
#endif
-#ifndef CONFIG_QSPI_BOOT
+#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
int config_board_mux(void)
{
struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
@@ -521,8 +436,10 @@ int board_early_init_f(void)
}
#if defined(CONFIG_DEEP_SLEEP)
- if (is_warm_boot())
- fsl_dp_disable_console();
+ if (is_warm_boot()) {
+ timer_init();
+ dram_init();
+ }
#endif
return 0;
@@ -531,6 +448,8 @@ int board_early_init_f(void)
#ifdef CONFIG_SPL_BUILD
void board_init_f(ulong dummy)
{
+ void (*second_uboot)(void);
+
/* Clear the BSS */
memset(__bss_start, 0, __bss_end - __bss_start);
@@ -546,11 +465,22 @@ void board_init_f(ulong dummy)
dram_init();
/* Allow OCRAM access permission as R/W */
-#ifdef CONFIG_LS102XA_NS_ACCESS
- enable_devices_ns_access(&ns_dev[4], 1);
- enable_devices_ns_access(&ns_dev[7], 1);
+#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
+ enable_layerscape_ns_access();
+ enable_layerscape_ns_access();
#endif
+ /*
+ * if it is woken up from deep sleep, then jump to second
+ * stage uboot and continue executing without recopying
+ * it from SD since it has already been reserved in memeory
+ * in last boot.
+ */
+ if (is_warm_boot()) {
+ second_uboot = (void (*)(void))CONFIG_SYS_TEXT_BASE;
+ second_uboot();
+ }
+
board_init_r(NULL, 0);
}
#endif
@@ -627,7 +557,7 @@ int board_init(void)
{
#ifndef CONFIG_SYS_FSL_NO_SERDES
fsl_serdes_init();
-#ifndef CONFIG_QSPI_BOOT
+#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
config_serdes_mux();
#endif
#endif
@@ -637,8 +567,8 @@ int board_init(void)
ls102xa_config_smmu_stream_id(dev_stream_id,
ARRAY_SIZE(dev_stream_id));
-#ifdef CONFIG_LS102XA_NS_ACCESS
- enable_devices_ns_access(ns_dev, ARRAY_SIZE(ns_dev));
+#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
+ enable_layerscape_ns_access();
#endif
#ifdef CONFIG_U_QE
@@ -651,13 +581,24 @@ int board_init(void)
return 0;
}
+#ifdef CONFIG_BOARD_LATE_INIT
+int board_late_init(void)
+{
+#ifdef CONFIG_SCSI_AHCI_PLAT
+ ls1021a_sata_init();
+#endif
+
+ return 0;
+}
+#endif
+
#if defined(CONFIG_MISC_INIT_R)
int misc_init_r(void)
{
#ifdef CONFIG_FSL_DEVICE_DISABLE
device_disable(devdis_tbl, ARRAY_SIZE(devdis_tbl));
#endif
-#ifndef CONFIG_QSPI_BOOT
+#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
config_board_mux();
#endif
@@ -670,8 +611,8 @@ int misc_init_r(void)
#if defined(CONFIG_DEEP_SLEEP)
void board_sleep_prepare(void)
{
-#ifdef CONFIG_LS102XA_NS_ACCESS
- enable_devices_ns_access(ns_dev, ARRAY_SIZE(ns_dev));
+#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
+ enable_layerscape_ns_access();
#endif
}
#endif
@@ -706,7 +647,7 @@ u16 flash_read16(void *addr)
return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00);
}
-#ifndef CONFIG_QSPI_BOOT
+#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
static void convert_flash_bank(char bank)
{
struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
diff --git a/board/freescale/ls1021atwr/ls102xa_rcw_sd.cfg b/board/freescale/ls1021atwr/ls102xa_rcw_sd.cfg
deleted file mode 100644
index 9c3e3b080b15a631d29066579df00b771563dc19..0000000000000000000000000000000000000000
--- a/board/freescale/ls1021atwr/ls102xa_rcw_sd.cfg
+++ /dev/null
@@ -1,14 +0,0 @@
-#PBL preamble and RCW header
-aa55aa55 01ee0100
-
-#enable IFC, disable QSPI and DSPI
-0608000a 00000000 00000000 00000000
-20000000 00407900 60040a00 21046000
-00000000 00000000 00000000 00038000
-00080000 881b7340 00000000 00000000
-
-#disable IFC, enable QSPI and DSPI
-#0608000a 00000000 00000000 00000000
-#20000000 00407900 60040a00 21046000
-#00000000 00000000 00000000 00038000
-#20084800 881b7340 00000000 00000000
diff --git a/board/freescale/ls1021atwr/ls102xa_rcw_sd_ifc.cfg b/board/freescale/ls1021atwr/ls102xa_rcw_sd_ifc.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..205606f4d2fcb76e2215a8c8b6fd6f3647d567e3
--- /dev/null
+++ b/board/freescale/ls1021atwr/ls102xa_rcw_sd_ifc.cfg
@@ -0,0 +1,8 @@
+#PBL preamble and RCW header
+aa55aa55 01ee0100
+
+#enable IFC, disable QSPI and DSPI
+0608000a 00000000 00000000 00000000
+30000000 00007900 60040a00 21046000
+00000000 00000000 00000000 20000000
+00080000 881b7340 00000000 00000000
diff --git a/board/freescale/ls1021atwr/ls102xa_rcw_sd_qspi.cfg b/board/freescale/ls1021atwr/ls102xa_rcw_sd_qspi.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..6767e09388042c0bfd54a06cc5b24bfabbc94eb2
--- /dev/null
+++ b/board/freescale/ls1021atwr/ls102xa_rcw_sd_qspi.cfg
@@ -0,0 +1,8 @@
+#PBL preamble and RCW header
+aa55aa55 01ee0100
+
+#disable IFC, enable QSPI and DSPI
+0608000a 00000000 00000000 00000000
+30000000 00007900 60040a00 21046000
+00000000 00000000 00000000 20000000
+20024800 881b7340 00000000 00000000
diff --git a/board/freescale/ls1043ardb/Kconfig b/board/freescale/ls1043ardb/Kconfig
new file mode 100644
index 0000000000000000000000000000000000000000..51818ec5801673ac140608f7f5541a073e363abf
--- /dev/null
+++ b/board/freescale/ls1043ardb/Kconfig
@@ -0,0 +1,16 @@
+
+if TARGET_LS1043ARDB
+
+config SYS_BOARD
+ default "ls1043ardb"
+
+config SYS_VENDOR
+ default "freescale"
+
+config SYS_SOC
+ default "fsl-layerscape"
+
+config SYS_CONFIG_NAME
+ default "ls1043ardb"
+
+endif
diff --git a/board/freescale/ls1043ardb/MAINTAINERS b/board/freescale/ls1043ardb/MAINTAINERS
new file mode 100644
index 0000000000000000000000000000000000000000..b8f6be249f852d8e75d539b720c1a247b6d1c770
--- /dev/null
+++ b/board/freescale/ls1043ardb/MAINTAINERS
@@ -0,0 +1,7 @@
+LS1043A BOARD
+M: Mingkai Hu <Mingkai.hu@freescale.com>
+S: Maintained
+F: board/freescale/ls1043ardb/
+F: board/freescale/ls1043ardb/ls1043ardb.c
+F: include/configs/ls1043ardb.h
+F: configs/ls1043ardb_defconfig
diff --git a/board/freescale/ls1043ardb/Makefile b/board/freescale/ls1043ardb/Makefile
new file mode 100644
index 0000000000000000000000000000000000000000..5fe1cc93932a484148f19c702e4888de70f41e14
--- /dev/null
+++ b/board/freescale/ls1043ardb/Makefile
@@ -0,0 +1,10 @@
+#
+# Copyright 2015 Freescale Semiconductor
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += cpld.o
+obj-y += ddr.o
+obj-y += ls1043ardb.o
+obj-$(CONFIG_SYS_DPAA_FMAN) += eth.o
diff --git a/board/freescale/ls1043ardb/README b/board/freescale/ls1043ardb/README
new file mode 100644
index 0000000000000000000000000000000000000000..0556e73b3aeee5e947aca007e04e047e067302d6
--- /dev/null
+++ b/board/freescale/ls1043ardb/README
@@ -0,0 +1,87 @@
+Overview
+--------
+The LS1043A Reference Design Board (RDB) is a high-performance computing,
+evaluation, and development platform that supports the QorIQ LS1043A
+LayerScape Architecture processor. The LS1043ARDB provides SW development
+platform for the Freescale LS1043A processor series, with a complete
+debugging environment. The LS1043A RDB is lead-free and RoHS-compliant.
+
+LS1043A SoC Overview
+--------------------
+The LS1043A integrated multicore processor combines four ARM Cortex-A53
+processor cores with datapath acceleration optimized for L2/3 packet
+processing, single pass security offload and robust traffic management
+and quality of service.
+
+The LS1043A SoC includes the following function and features:
+ - Four 64-bit ARM Cortex-A53 CPUs
+ - 1 MB unified L2 Cache
+ - One 32-bit DDR3L/DDR4 SDRAM memory controllers with ECC and interleaving
+ support
+ - Data Path Acceleration Architecture (DPAA) incorporating acceleration the
+ the following functions:
+ - Packet parsing, classification, and distribution (FMan)
+ - Queue management for scheduling, packet sequencing, and congestion
+ management (QMan)
+ - Hardware buffer management for buffer allocation and de-allocation (BMan)
+ - Cryptography acceleration (SEC)
+ - Ethernet interfaces by FMan
+ - Up to 1 x XFI supporting 10G interface
+ - Up to 1 x QSGMII
+ - Up to 4 x SGMII supporting 1000Mbps
+ - Up to 2 x SGMII supporting 2500Mbps
+ - Up to 2 x RGMII supporting 1000Mbps
+ - High-speed peripheral interfaces
+ - Three PCIe 2.0 controllers, one supporting x4 operation
+ - One serial ATA (SATA 3.0) controllers
+ - Additional peripheral interfaces
+ - Three high-speed USB 3.0 controllers with integrated PHY
+ - Enhanced secure digital host controller (eSDXC/eMMC)
+ - Quad Serial Peripheral Interface (QSPI) Controller
+ - Serial peripheral interface (SPI) controller
+ - Four I2C controllers
+ - Two DUARTs
+ - Integrated flash controller supporting NAND and NOR flash
+ - QorIQ platform's trust architecture 2.1
+
+ LS1043ARDB board Overview
+ -----------------------
+ - SERDES Connections, 4 lanes supporting:
+ - PCI Express 2.0 with two PCIe connectors supporting: miniPCIe card and
+ standard PCIe card
+ - QSGMII with x4 RJ45 connector
+ - XFI with x1 RJ45 connector
+ - DDR Controller
+ - 2GB 32bits DDR4 SDRAM. Support rates of up to 1600MT/s
+ -IFC/Local Bus
+ - One 128MB NOR flash 16-bit data bus
+ - One 512 MB NAND flash with ECC support
+ - CPLD connection
+ - USB 3.0
+ - Two super speed USB 3.0 Type A ports
+ - SDHC: connects directly to a full SD/MMC slot
+ - DSPI: 16 MB high-speed flash Memory for boot code and storage (up to 108MHz)
+ - 4 I2C controllers
+ - UART
+ - Two 4-pin serial ports at up to 115.2 Kbit/s
+ - Two DB9 D-Type connectors supporting one Serial port each
+ - ARM JTAG support
+
+Memory map from core's view
+----------------------------
+Start Address End Address Description Size
+0x00_0000_0000 0x00_000F_FFFF Secure Boot ROM 1MB
+0x00_0100_0000 0x00_0FFF_FFFF CCSRBAR 240MB
+0x00_1000_0000 0x00_1000_FFFF OCRAM0 64KB
+0x00_1001_0000 0x00_1001_FFFF OCRAM1 64KB
+0x00_2000_0000 0x00_20FF_FFFF DCSR 16MB
+0x00_6000_0000 0x00_67FF_FFFF IFC - NOR Flash 128MB
+0x00_7E80_0000 0x00_7E80_FFFF IFC - NAND Flash 64KB
+0x00_7FB0_0000 0x00_7FB0_0FFF IFC - FPGA 4KB
+0x00_8000_0000 0x00_FFFF_FFFF DRAM1 2GB
+
+Booting Options
+---------------
+a) NOR boot
+b) NAND boot
+c) SD boot
diff --git a/board/freescale/ls1043ardb/cpld.c b/board/freescale/ls1043ardb/cpld.c
new file mode 100644
index 0000000000000000000000000000000000000000..78c28246a823d1ce4935e8e7757c78fb6f426c56
--- /dev/null
+++ b/board/freescale/ls1043ardb/cpld.c
@@ -0,0 +1,152 @@
+/*
+ * Copyright 2015 Freescale Semiconductor
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * Freescale LS1043ARDB board-specific CPLD controlling supports.
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/io.h>
+#include "cpld.h"
+
+u8 cpld_read(unsigned int reg)
+{
+ void *p = (void *)CONFIG_SYS_CPLD_BASE;
+
+ return in_8(p + reg);
+}
+
+void cpld_write(unsigned int reg, u8 value)
+{
+ void *p = (void *)CONFIG_SYS_CPLD_BASE;
+
+ out_8(p + reg, value);
+}
+
+/* Set the boot bank to the alternate bank */
+void cpld_set_altbank(void)
+{
+ u8 reg4 = CPLD_READ(soft_mux_on);
+ u8 reg7 = CPLD_READ(vbank);
+
+ CPLD_WRITE(soft_mux_on, reg4 | CPLD_SW_MUX_BANK_SEL);
+
+ reg7 = (reg7 & ~CPLD_BANK_SEL_MASK) | CPLD_BANK_SEL_ALTBANK;
+ CPLD_WRITE(vbank, reg7);
+
+ CPLD_WRITE(system_rst, 1);
+}
+
+/* Set the boot bank to the default bank */
+void cpld_set_defbank(void)
+{
+ CPLD_WRITE(global_rst, 1);
+}
+
+void cpld_set_nand(void)
+{
+ u16 reg = CPLD_CFG_RCW_SRC_NAND;
+ u8 reg5 = (u8)(reg >> 1);
+ u8 reg6 = (u8)(reg & 1);
+
+ cpld_rev_bit(®5);
+
+ CPLD_WRITE(soft_mux_on, 1);
+
+ CPLD_WRITE(cfg_rcw_src1, reg5);
+ CPLD_WRITE(cfg_rcw_src2, reg6);
+
+ CPLD_WRITE(system_rst, 1);
+}
+
+void cpld_set_sd(void)
+{
+ u16 reg = CPLD_CFG_RCW_SRC_SD;
+ u8 reg5 = (u8)(reg >> 1);
+ u8 reg6 = (u8)(reg & 1);
+
+ cpld_rev_bit(®5);
+
+ CPLD_WRITE(soft_mux_on, 1);
+
+ CPLD_WRITE(cfg_rcw_src1, reg5);
+ CPLD_WRITE(cfg_rcw_src2, reg6);
+
+ CPLD_WRITE(system_rst, 1);
+}
+#ifdef DEBUG
+static void cpld_dump_regs(void)
+{
+ printf("cpld_ver = %x\n", CPLD_READ(cpld_ver));
+ printf("cpld_ver_sub = %x\n", CPLD_READ(cpld_ver_sub));
+ printf("pcba_ver = %x\n", CPLD_READ(pcba_ver));
+ printf("soft_mux_on = %x\n", CPLD_READ(soft_mux_on));
+ printf("cfg_rcw_src1 = %x\n", CPLD_READ(cfg_rcw_src1));
+ printf("cfg_rcw_src2 = %x\n", CPLD_READ(cfg_rcw_src2));
+ printf("vbank = %x\n", CPLD_READ(vbank));
+ printf("sysclk_sel = %x\n", CPLD_READ(sysclk_sel));
+ printf("uart_sel = %x\n", CPLD_READ(uart_sel));
+ printf("sd1refclk_sel = %x\n", CPLD_READ(sd1refclk_sel));
+ printf("tdmclk_mux_sel = %x\n", CPLD_READ(tdmclk_mux_sel));
+ printf("sdhc_spics_sel = %x\n", CPLD_READ(sdhc_spics_sel));
+ printf("status_led = %x\n", CPLD_READ(status_led));
+ putc('\n');
+}
+#endif
+
+void cpld_rev_bit(unsigned char *value)
+{
+ u8 rev_val, val;
+ int i;
+
+ val = *value;
+ rev_val = val & 1;
+ for (i = 1; i <= 7; i++) {
+ val >>= 1;
+ rev_val <<= 1;
+ rev_val |= val & 1;
+ }
+
+ *value = rev_val;
+}
+
+int do_cpld(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ int rc = 0;
+
+ if (argc <= 1)
+ return cmd_usage(cmdtp);
+
+ if (strcmp(argv[1], "reset") == 0) {
+ if (strcmp(argv[2], "altbank") == 0)
+ cpld_set_altbank();
+ else if (strcmp(argv[2], "nand") == 0)
+ cpld_set_nand();
+ else if (strcmp(argv[2], "sd") == 0)
+ cpld_set_sd();
+ else
+ cpld_set_defbank();
+#ifdef DEBUG
+ } else if (strcmp(argv[1], "dump") == 0) {
+ cpld_dump_regs();
+#endif
+ } else {
+ rc = cmd_usage(cmdtp);
+ }
+
+ return rc;
+}
+
+U_BOOT_CMD(
+ cpld, CONFIG_SYS_MAXARGS, 1, do_cpld,
+ "Reset the board or alternate bank",
+ "reset: reset to default bank\n"
+ "cpld reset altbank: reset to alternate bank\n"
+ "cpld reset nand: reset to boot from NAND flash\n"
+ "cpld reset sd: reset to boot from SD card\n"
+#ifdef DEBUG
+ "cpld dump - display the CPLD registers\n"
+#endif
+);
diff --git a/board/freescale/ls1043ardb/cpld.h b/board/freescale/ls1043ardb/cpld.h
new file mode 100644
index 0000000000000000000000000000000000000000..bd59c0e5d58e19c6d24eee72f92d0e0d74862d46
--- /dev/null
+++ b/board/freescale/ls1043ardb/cpld.h
@@ -0,0 +1,45 @@
+/*
+ * Copyright 2015 Freescale Semiconductor
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CPLD_H__
+#define __CPLD_H__
+
+/*
+ * CPLD register set of LS1043ARDB board-specific.
+ */
+struct cpld_data {
+ u8 cpld_ver; /* 0x0 - CPLD Major Revision Register */
+ u8 cpld_ver_sub; /* 0x1 - CPLD Minor Revision Register */
+ u8 pcba_ver; /* 0x2 - PCBA Revision Register */
+ u8 system_rst; /* 0x3 - system reset register */
+ u8 soft_mux_on; /* 0x4 - Switch Control Enable Register */
+ u8 cfg_rcw_src1; /* 0x5 - Reset config word 1 */
+ u8 cfg_rcw_src2; /* 0x6 - Reset config word 1 */
+ u8 vbank; /* 0x7 - Flash bank selection Control */
+ u8 sysclk_sel; /* 0x8 - */
+ u8 uart_sel; /* 0x9 - */
+ u8 sd1refclk_sel; /* 0xA - */
+ u8 tdmclk_mux_sel; /* 0xB - */
+ u8 sdhc_spics_sel; /* 0xC - */
+ u8 status_led; /* 0xD - */
+ u8 global_rst; /* 0xE - */
+};
+
+u8 cpld_read(unsigned int reg);
+void cpld_write(unsigned int reg, u8 value);
+void cpld_rev_bit(unsigned char *value);
+
+#define CPLD_READ(reg) cpld_read(offsetof(struct cpld_data, reg))
+#define CPLD_WRITE(reg, value) \
+ cpld_write(offsetof(struct cpld_data, reg), value)
+
+/* CPLD on IFC */
+#define CPLD_SW_MUX_BANK_SEL 0x40
+#define CPLD_BANK_SEL_MASK 0x07
+#define CPLD_BANK_SEL_ALTBANK 0x04
+#define CPLD_CFG_RCW_SRC_NAND 0x106
+#define CPLD_CFG_RCW_SRC_SD 0x040
+#endif
diff --git a/board/freescale/ls1043ardb/ddr.c b/board/freescale/ls1043ardb/ddr.c
new file mode 100644
index 0000000000000000000000000000000000000000..b181579e8e4d31668e4685fa6f117508f8dd107f
--- /dev/null
+++ b/board/freescale/ls1043ardb/ddr.c
@@ -0,0 +1,191 @@
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
+#include "ddr.h"
+#ifdef CONFIG_FSL_DEEP_SLEEP
+#include <fsl_sleep.h>
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void fsl_ddr_board_options(memctl_options_t *popts,
+ dimm_params_t *pdimm,
+ unsigned int ctrl_num)
+{
+ const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
+ ulong ddr_freq;
+
+ if (ctrl_num > 1) {
+ printf("Not supported controller number %d\n", ctrl_num);
+ return;
+ }
+ if (!pdimm->n_ranks)
+ return;
+
+ pbsp = udimms[0];
+
+ /* Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr
+ * freqency and n_banks specified in board_specific_parameters table.
+ */
+ ddr_freq = get_ddr_freq(0) / 1000000;
+ while (pbsp->datarate_mhz_high) {
+ if (pbsp->n_ranks == pdimm->n_ranks) {
+ if (ddr_freq <= pbsp->datarate_mhz_high) {
+ popts->clk_adjust = pbsp->clk_adjust;
+ popts->wrlvl_start = pbsp->wrlvl_start;
+ popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
+ popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
+ popts->cpo_override = pbsp->cpo_override;
+ popts->write_data_delay =
+ pbsp->write_data_delay;
+ goto found;
+ }
+ pbsp_highest = pbsp;
+ }
+ pbsp++;
+ }
+
+ if (pbsp_highest) {
+ printf("Error: board specific timing not found for %lu MT/s\n",
+ ddr_freq);
+ printf("Trying to use the highest speed (%u) parameters\n",
+ pbsp_highest->datarate_mhz_high);
+ popts->clk_adjust = pbsp_highest->clk_adjust;
+ popts->wrlvl_start = pbsp_highest->wrlvl_start;
+ popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
+ popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
+ } else {
+ panic("DIMM is not supported by this board");
+ }
+found:
+ debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n",
+ pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb);
+
+ /* force DDR bus width to 32 bits */
+ popts->data_bus_width = 1;
+ popts->otf_burst_chop_en = 0;
+ popts->burst_length = DDR_BL8;
+
+ /*
+ * Factors to consider for half-strength driver enable:
+ * - number of DIMMs installed
+ */
+ popts->half_strength_driver_enable = 1;
+ /*
+ * Write leveling override
+ */
+ popts->wrlvl_override = 1;
+ popts->wrlvl_sample = 0xf;
+
+ /*
+ * Rtt and Rtt_WR override
+ */
+ popts->rtt_override = 0;
+
+ /* Enable ZQ calibration */
+ popts->zq_en = 1;
+
+ popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_80ohm);
+ popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_80ohm) |
+ DDR_CDR2_VREF_OVRD(70); /* Vref = 70% */
+}
+
+/* DDR model number: MT40A512M8HX-093E */
+#ifdef CONFIG_SYS_DDR_RAW_TIMING
+dimm_params_t ddr_raw_timing = {
+ .n_ranks = 1,
+ .rank_density = 2147483648u,
+ .capacity = 2147483648u,
+ .primary_sdram_width = 32,
+ .ec_sdram_width = 0,
+ .registered_dimm = 0,
+ .mirrored_dimm = 0,
+ .n_row_addr = 15,
+ .n_col_addr = 10,
+ .bank_addr_bits = 0,
+ .bank_group_bits = 2,
+ .edc_config = 0,
+ .burst_lengths_bitmask = 0x0c,
+
+ .tckmin_x_ps = 938,
+ .tckmax_ps = 1500,
+ .caslat_x = 0x000DFA00,
+ .taa_ps = 13500,
+ .trcd_ps = 13500,
+ .trp_ps = 13500,
+ .tras_ps = 33000,
+ .trc_ps = 46500,
+ .trfc1_ps = 260000,
+ .trfc2_ps = 160000,
+ .trfc4_ps = 110000,
+ .tfaw_ps = 21000,
+ .trrds_ps = 3700,
+ .trrdl_ps = 5300,
+ .tccdl_ps = 5355,
+ .refresh_rate_ps = 7800000,
+ .dq_mapping[0] = 0x0,
+ .dq_mapping[1] = 0x0,
+ .dq_mapping[2] = 0x0,
+ .dq_mapping[3] = 0x0,
+ .dq_mapping[4] = 0x0,
+ .dq_mapping[5] = 0x0,
+ .dq_mapping[6] = 0x0,
+ .dq_mapping[7] = 0x0,
+ .dq_mapping[8] = 0x0,
+ .dq_mapping[9] = 0x0,
+ .dq_mapping[10] = 0x0,
+ .dq_mapping[11] = 0x0,
+ .dq_mapping[12] = 0x0,
+ .dq_mapping[13] = 0x0,
+ .dq_mapping[14] = 0x0,
+ .dq_mapping[15] = 0x0,
+ .dq_mapping[16] = 0x0,
+ .dq_mapping[17] = 0x0,
+ .dq_mapping_ors = 0,
+};
+
+int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
+ unsigned int controller_number,
+ unsigned int dimm_number)
+{
+ static const char dimm_model[] = "Fixed DDR on board";
+
+ if (((controller_number == 0) && (dimm_number == 0)) ||
+ ((controller_number == 1) && (dimm_number == 0))) {
+ memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t));
+ memset(pdimm->mpart, 0, sizeof(pdimm->mpart));
+ memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1);
+ }
+
+ return 0;
+}
+#endif
+
+phys_size_t initdram(int board_type)
+{
+ phys_size_t dram_size;
+
+#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_SPL)
+ puts("Initializing DDR....\n");
+ dram_size = fsl_ddr_sdram();
+#else
+ dram_size = fsl_ddr_sdram_size();
+#endif
+#ifdef CONFIG_FSL_DEEP_SLEEP
+ fsl_dp_ddr_restore();
+#endif
+
+ return dram_size;
+}
+
+void dram_init_banksize(void)
+{
+ gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+ gd->bd->bi_dram[0].size = gd->ram_size;
+}
diff --git a/board/freescale/ls1043ardb/ddr.h b/board/freescale/ls1043ardb/ddr.h
new file mode 100644
index 0000000000000000000000000000000000000000..b17eb8088538b0f242d1182084c0450caae2c35e
--- /dev/null
+++ b/board/freescale/ls1043ardb/ddr.h
@@ -0,0 +1,45 @@
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __DDR_H__
+#define __DDR_H__
+struct board_specific_parameters {
+ u32 n_ranks;
+ u32 datarate_mhz_high;
+ u32 rank_gb;
+ u32 clk_adjust;
+ u32 wrlvl_start;
+ u32 wrlvl_ctl_2;
+ u32 wrlvl_ctl_3;
+ u32 cpo_override;
+ u32 write_data_delay;
+ u32 force_2t;
+};
+
+/*
+ * These tables contain all valid speeds we want to override with board
+ * specific parameters. datarate_mhz_high values need to be in ascending order
+ * for each n_ranks group.
+ */
+static const struct board_specific_parameters udimm0[] = {
+ /*
+ * memory controller 0
+ * num| hi| rank| clk| wrlvl | wrlvl | wrlvl | cpo |wrdata|2T
+ * ranks| mhz| GB |adjst| start | ctl2 | ctl3 | |delay |
+ */
+#ifdef CONFIG_SYS_FSL_DDR4
+ {1, 1666, 0, 6, 7, 0x07090800, 0x00000000,},
+ {1, 1900, 0, 6, 7, 0x07090800, 0x00000000,},
+ {1, 2200, 0, 6, 7, 0x07090800, 0x00000000,},
+#endif
+ {}
+};
+
+static const struct board_specific_parameters *udimms[] = {
+ udimm0,
+};
+
+#endif
diff --git a/board/freescale/ls1043ardb/eth.c b/board/freescale/ls1043ardb/eth.c
new file mode 100644
index 0000000000000000000000000000000000000000..61f2b5d4471fa921564dbf6ae0bfade477782298
--- /dev/null
+++ b/board/freescale/ls1043ardb/eth.c
@@ -0,0 +1,77 @@
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#include <common.h>
+#include <asm/io.h>
+#include <netdev.h>
+#include <fm_eth.h>
+#include <fsl_dtsec.h>
+#include <fsl_mdio.h>
+#include <malloc.h>
+
+#include "../common/fman.h"
+
+int board_eth_init(bd_t *bis)
+{
+#ifdef CONFIG_FMAN_ENET
+ int i;
+ struct memac_mdio_info dtsec_mdio_info;
+ struct memac_mdio_info tgec_mdio_info;
+ struct mii_dev *dev;
+ u32 srds_s1;
+ struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+
+ srds_s1 = in_be32(&gur->rcwsr[4]) &
+ FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK;
+ srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT;
+
+ dtsec_mdio_info.regs =
+ (struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR;
+
+ dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
+
+ /* Register the 1G MDIO bus */
+ fm_memac_mdio_init(bis, &dtsec_mdio_info);
+
+ tgec_mdio_info.regs =
+ (struct memac_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR;
+ tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
+
+ /* Register the 10G MDIO bus */
+ fm_memac_mdio_init(bis, &tgec_mdio_info);
+
+ /* Set the two on-board RGMII PHY address */
+ fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY1_ADDR);
+ fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY2_ADDR);
+
+ /* QSGMII on lane B, MAC 1/2/5/6 */
+ fm_info_set_phy_address(FM1_DTSEC1, QSGMII_PORT1_PHY_ADDR);
+ fm_info_set_phy_address(FM1_DTSEC2, QSGMII_PORT2_PHY_ADDR);
+ fm_info_set_phy_address(FM1_DTSEC5, QSGMII_PORT3_PHY_ADDR);
+ fm_info_set_phy_address(FM1_DTSEC6, QSGMII_PORT4_PHY_ADDR);
+
+ switch (srds_s1) {
+ case 0x1455:
+ break;
+ default:
+ printf("Invalid SerDes protocol 0x%x for LS1043ARDB\n",
+ srds_s1);
+ break;
+ }
+
+ dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME);
+ for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++)
+ fm_info_set_mdio(i, dev);
+
+ /* XFI on lane A, MAC 9 */
+ fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR);
+ dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME);
+ fm_info_set_mdio(FM1_10GEC1, dev);
+
+ cpu_eth_init(bis);
+#endif
+
+ return pci_eth_init(bis);
+}
diff --git a/board/freescale/ls1043ardb/ls1043ardb.c b/board/freescale/ls1043ardb/ls1043ardb.c
new file mode 100644
index 0000000000000000000000000000000000000000..9032ed36c852274fbf804ea7c361daa4cfefd9ae
--- /dev/null
+++ b/board/freescale/ls1043ardb/ls1043ardb.c
@@ -0,0 +1,142 @@
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/fsl_serdes.h>
+#include <asm/arch/soc.h>
+#include <hwconfig.h>
+#include <ahci.h>
+#include <mmc.h>
+#include <scsi.h>
+#include <fm_eth.h>
+#include <fsl_csu.h>
+#include <fsl_esdhc.h>
+#include <fsl_ifc.h>
+#include "cpld.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int checkboard(void)
+{
+ static const char *freq[3] = {"100.00MHZ", "156.25MHZ"};
+#ifndef CONFIG_SD_BOOT
+ u8 cfg_rcw_src1, cfg_rcw_src2;
+ u32 cfg_rcw_src;
+#endif
+ u32 sd1refclk_sel;
+
+ printf("Board: LS1043ARDB, boot from ");
+
+#ifdef CONFIG_SD_BOOT
+ puts("SD\n");
+#else
+ cfg_rcw_src1 = CPLD_READ(cfg_rcw_src1);
+ cfg_rcw_src2 = CPLD_READ(cfg_rcw_src2);
+ cpld_rev_bit(&cfg_rcw_src1);
+ cfg_rcw_src = cfg_rcw_src1;
+ cfg_rcw_src = (cfg_rcw_src << 1) | cfg_rcw_src2;
+
+ if (cfg_rcw_src == 0x25)
+ printf("vBank %d\n", CPLD_READ(vbank));
+ else if (cfg_rcw_src == 0x106)
+ puts("NAND\n");
+ else
+ printf("Invalid setting of SW4\n");
+#endif
+
+ printf("CPLD: V%x.%x\nPCBA: V%x.0\n", CPLD_READ(cpld_ver),
+ CPLD_READ(cpld_ver_sub), CPLD_READ(pcba_ver));
+
+ puts("SERDES Reference Clocks:\n");
+ sd1refclk_sel = CPLD_READ(sd1refclk_sel);
+ printf("SD1_CLK1 = %s, SD1_CLK2 = %s\n", freq[sd1refclk_sel], freq[0]);
+
+ return 0;
+}
+
+int dram_init(void)
+{
+ gd->ram_size = initdram(0);
+
+ return 0;
+}
+
+int board_early_init_f(void)
+{
+ fsl_lsch2_early_init_f();
+ return 0;
+}
+
+int board_init(void)
+{
+ struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
+
+ /*
+ * Set CCI-400 control override register to enable barrier
+ * transaction
+ */
+ out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
+
+#ifdef CONFIG_FSL_IFC
+ init_final_memctl_regs();
+#endif
+
+#ifdef CONFIG_ENV_IS_NOWHERE
+ gd->env_addr = (ulong)&default_environment[0];
+#endif
+
+#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
+ enable_layerscape_ns_access();
+#endif
+
+ return 0;
+}
+
+int config_board_mux(void)
+{
+ return 0;
+}
+
+#if defined(CONFIG_MISC_INIT_R)
+int misc_init_r(void)
+{
+ config_board_mux();
+
+ return 0;
+}
+#endif
+
+int ft_board_setup(void *blob, bd_t *bd)
+{
+ ft_cpu_setup(blob, bd);
+
+#ifdef CONFIG_SYS_DPAA_FMAN
+ fdt_fixup_fman_ethernet(blob);
+#endif
+ return 0;
+}
+
+u8 flash_read8(void *addr)
+{
+ return __raw_readb(addr + 1);
+}
+
+void flash_write16(u16 val, void *addr)
+{
+ u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00));
+
+ __raw_writew(shftval, addr);
+}
+
+u16 flash_read16(void *addr)
+{
+ u16 val = __raw_readw(addr);
+
+ return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00);
+}
diff --git a/board/freescale/ls1043ardb/ls1043ardb_pbi.cfg b/board/freescale/ls1043ardb/ls1043ardb_pbi.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..f072274f474cf6e364716740464bbb91ed94e16d
--- /dev/null
+++ b/board/freescale/ls1043ardb/ls1043ardb_pbi.cfg
@@ -0,0 +1,14 @@
+#Configure Scratch register
+09570600 00000000
+09570604 10000000
+#Alt base register
+09570158 00001000
+#Disable CCI barrier tranaction
+09570178 0000e010
+09180000 00000008
+#USB PHY frequency sel
+09570418 0000009e
+0957041c 0000009e
+09570420 0000009e
+#flush PBI data
+096100c0 000fffff
diff --git a/board/freescale/ls1043ardb/ls1043ardb_rcw_nand.cfg b/board/freescale/ls1043ardb/ls1043ardb_rcw_nand.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..935ffc0102141d69c458d9d488d2ece34b84d376
--- /dev/null
+++ b/board/freescale/ls1043ardb/ls1043ardb_rcw_nand.cfg
@@ -0,0 +1,7 @@
+#PBL preamble and RCW header
+aa55aa55 01ee0100
+# serdes protocol
+0810000f 0c000000 00000000 00000000
+14550002 80004012 e0106000 61002000
+00000000 00000000 00000000 00038800
+00000000 00001100 00000096 00000001
diff --git a/board/freescale/ls1043ardb/ls1043ardb_rcw_sd.cfg b/board/freescale/ls1043ardb/ls1043ardb_rcw_sd.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..28cd95859d20655b47e2e191f917578403da49cb
--- /dev/null
+++ b/board/freescale/ls1043ardb/ls1043ardb_rcw_sd.cfg
@@ -0,0 +1,7 @@
+#PBL preamble and RCW header
+aa55aa55 01ee0100
+# RCW
+0810000f 0c000000 00000000 00000000
+14550002 80004012 60040000 61002000
+00000000 00000000 00000000 00038800
+00000000 00001100 00000096 00000001
diff --git a/board/freescale/ls2085a/Kconfig b/board/freescale/ls2085a/Kconfig
index f51afc8234422a576b314dcedd4e4d6b7674e03f..042f85b3670d7aab8cdf9163bf52f4e2014fca71 100644
--- a/board/freescale/ls2085a/Kconfig
+++ b/board/freescale/ls2085a/Kconfig
@@ -7,7 +7,7 @@ config SYS_VENDOR
default "freescale"
config SYS_SOC
- default "fsl-lsch3"
+ default "fsl-layerscape"
config SYS_CONFIG_NAME
default "ls2085a_emu"
@@ -23,7 +23,7 @@ config SYS_VENDOR
default "freescale"
config SYS_SOC
- default "fsl-lsch3"
+ default "fsl-layerscape"
config SYS_CONFIG_NAME
default "ls2085a_simu"
diff --git a/board/freescale/ls2085a/ls2085a.c b/board/freescale/ls2085a/ls2085a.c
index 73c44102c4442551b942805e65f23e45a2e0ab74..27481e2ba3a0d4328e38c820bea9d9b58f8b460d 100644
--- a/board/freescale/ls2085a/ls2085a.c
+++ b/board/freescale/ls2085a/ls2085a.c
@@ -15,7 +15,7 @@
#include <fsl_debug_server.h>
#include <fsl-mc/fsl_mc.h>
#include <environment.h>
-#include <asm/arch-fsl-lsch3/soc.h>
+#include <asm/arch/soc.h>
DECLARE_GLOBAL_DATA_PTR;
diff --git a/board/freescale/ls2085aqds/Kconfig b/board/freescale/ls2085aqds/Kconfig
index deb640d4746500120524820049958639d6c9be41..8d6acbac93c7f6864f915de6187e186cabf9fd8a 100644
--- a/board/freescale/ls2085aqds/Kconfig
+++ b/board/freescale/ls2085aqds/Kconfig
@@ -8,7 +8,7 @@ config SYS_VENDOR
default "freescale"
config SYS_SOC
- default "fsl-lsch3"
+ default "fsl-layerscape"
config SYS_CONFIG_NAME
default "ls2085aqds"
diff --git a/board/freescale/ls2085aqds/eth.c b/board/freescale/ls2085aqds/eth.c
index 007b433d811d294b63d91e4fa53a0b606778448a..b8a2bf49e685aef90353deb4607b119e9cc799f5 100644
--- a/board/freescale/ls2085aqds/eth.c
+++ b/board/freescale/ls2085aqds/eth.c
@@ -8,7 +8,6 @@
#include <netdev.h>
#include <asm/io.h>
#include <asm/arch/fsl_serdes.h>
-#include <asm/arch-fsl-lsch3/immap_lsch3.h>
#include <hwconfig.h>
#include <fsl_mdio.h>
#include <malloc.h>
diff --git a/board/freescale/ls2085aqds/ls2085aqds.c b/board/freescale/ls2085aqds/ls2085aqds.c
index 2315bdb1304623a16833ca760788253d3fdcbe96..b02d6e86b43f9eadc42fcbc00c956da7e8809735 100644
--- a/board/freescale/ls2085aqds/ls2085aqds.c
+++ b/board/freescale/ls2085aqds/ls2085aqds.c
@@ -17,7 +17,7 @@
#include <environment.h>
#include <i2c.h>
#include <rtc.h>
-#include <asm/arch-fsl-lsch3/soc.h>
+#include <asm/arch/soc.h>
#include <hwconfig.h>
#include "../common/qixis.h"
diff --git a/board/freescale/ls2085ardb/Kconfig b/board/freescale/ls2085ardb/Kconfig
index 85a3dcdc452725dfe3441bcfcfd8902992138556..cb40db9b55d5229845df89578722c888ae68e495 100644
--- a/board/freescale/ls2085ardb/Kconfig
+++ b/board/freescale/ls2085ardb/Kconfig
@@ -8,7 +8,7 @@ config SYS_VENDOR
default "freescale"
config SYS_SOC
- default "fsl-lsch3"
+ default "fsl-layerscape"
config SYS_CONFIG_NAME
default "ls2085ardb"
diff --git a/board/freescale/ls2085ardb/eth_ls2085rdb.c b/board/freescale/ls2085ardb/eth_ls2085rdb.c
index 0a1163ab8ed15e83d35e34818efc1f138d363492..d578757dfde860f51d92142670844f491dbce3d6 100644
--- a/board/freescale/ls2085ardb/eth_ls2085rdb.c
+++ b/board/freescale/ls2085ardb/eth_ls2085rdb.c
@@ -16,7 +16,6 @@
#include <asm/io.h>
#include <exports.h>
#include <asm/arch/fsl_serdes.h>
-#include <asm/arch-fsl-lsch3/immap_lsch3.h>
#include <fsl-mc/ldpaa_wriop.h>
DECLARE_GLOBAL_DATA_PTR;
diff --git a/board/freescale/ls2085ardb/ls2085ardb.c b/board/freescale/ls2085ardb/ls2085ardb.c
index 5e7997c8698290488d1a0bf13355b7fc7ea1ebed..18953b8ecbfd5648ac8b90c29476cfb75b14a660 100644
--- a/board/freescale/ls2085ardb/ls2085ardb.c
+++ b/board/freescale/ls2085ardb/ls2085ardb.c
@@ -17,7 +17,7 @@
#include <fsl-mc/fsl_mc.h>
#include <environment.h>
#include <i2c.h>
-#include <asm/arch-fsl-lsch3/soc.h>
+#include <asm/arch/soc.h>
#include "../common/qixis.h"
#include "ls2085ardb_qixis.h"
diff --git a/board/freescale/p1023rdb/p1023rdb.c b/board/freescale/p1023rdb/p1023rdb.c
index 56f561a50582f6d76b0e61ee2db540d0709bc970..074b71326f00e59cee4a24d345565f4a1c47a79d 100644
--- a/board/freescale/p1023rdb/p1023rdb.c
+++ b/board/freescale/p1023rdb/p1023rdb.c
@@ -26,7 +26,7 @@
#include <fsl_mdio.h>
#include <miiphy.h>
#include <phy.h>
-#include <asm/fsl_dtsec.h>
+#include <fsl_dtsec.h>
DECLARE_GLOBAL_DATA_PTR;
diff --git a/board/freescale/p2041rdb/eth.c b/board/freescale/p2041rdb/eth.c
index 532eeac84bebd78ff9d67b44bc8aa7d7fa2c1b99..95fe85bbfaa224dd9462063218ef94d8b904d865 100644
--- a/board/freescale/p2041rdb/eth.c
+++ b/board/freescale/p2041rdb/eth.c
@@ -19,7 +19,7 @@
#include <fm_eth.h>
#include <fsl_mdio.h>
#include <malloc.h>
-#include <asm/fsl_dtsec.h>
+#include <fsl_dtsec.h>
#include "cpld.h"
#include "../common/fman.h"
diff --git a/board/freescale/t102xqds/eth_t102xqds.c b/board/freescale/t102xqds/eth_t102xqds.c
index 441d6a3e6142ed8903f3886fc03b460eb1397fc2..99c23f79f47114938aef34efc8bf14eb270aaaee 100644
--- a/board/freescale/t102xqds/eth_t102xqds.c
+++ b/board/freescale/t102xqds/eth_t102xqds.c
@@ -21,7 +21,7 @@
#include <fsl_mdio.h>
#include <miiphy.h>
#include <phy.h>
-#include <asm/fsl_dtsec.h>
+#include <fsl_dtsec.h>
#include <asm/fsl_serdes.h>
#include "../common/qixis.h"
#include "../common/fman.h"
diff --git a/board/freescale/t102xrdb/eth_t102xrdb.c b/board/freescale/t102xrdb/eth_t102xrdb.c
index 856ec6e227961d3be13f745ad55ffd82b8e45673..02b283d26ff03be3e537b4ae605da00920b325a3 100644
--- a/board/freescale/t102xrdb/eth_t102xrdb.c
+++ b/board/freescale/t102xrdb/eth_t102xrdb.c
@@ -21,7 +21,7 @@
#include <fsl_mdio.h>
#include <miiphy.h>
#include <phy.h>
-#include <asm/fsl_dtsec.h>
+#include <fsl_dtsec.h>
#include <asm/fsl_serdes.h>
#include "../common/fman.h"
diff --git a/board/freescale/t1040qds/eth.c b/board/freescale/t1040qds/eth.c
index 8c8293426bb622428bca78ffbd2e7c885f1afc2e..8bf34fa79ac6dfe93afeaeaf76d6b39456743b22 100644
--- a/board/freescale/t1040qds/eth.c
+++ b/board/freescale/t1040qds/eth.c
@@ -17,7 +17,7 @@
#include <fm_eth.h>
#include <fsl_mdio.h>
#include <malloc.h>
-#include <asm/fsl_dtsec.h>
+#include <fsl_dtsec.h>
#include <vsc9953.h>
#include "../common/fman.h"
diff --git a/board/freescale/t104xrdb/eth.c b/board/freescale/t104xrdb/eth.c
index 71d0457d43210db7ff5d4979a40284f6ec85ca01..52cd1122493b272078d2668ebf80ba6eb458e246 100644
--- a/board/freescale/t104xrdb/eth.c
+++ b/board/freescale/t104xrdb/eth.c
@@ -11,7 +11,7 @@
#include <fm_eth.h>
#include <fsl_mdio.h>
#include <malloc.h>
-#include <asm/fsl_dtsec.h>
+#include <fsl_dtsec.h>
#include <vsc9953.h>
#include "../common/fman.h"
diff --git a/board/freescale/t208xqds/eth_t208xqds.c b/board/freescale/t208xqds/eth_t208xqds.c
index b82e9e7540208e49da8311805b563850d5b0e44d..1c0ce2492ca2e5742764f1ec8cfc0e37abc32829 100644
--- a/board/freescale/t208xqds/eth_t208xqds.c
+++ b/board/freescale/t208xqds/eth_t208xqds.c
@@ -21,7 +21,7 @@
#include <fsl_mdio.h>
#include <miiphy.h>
#include <phy.h>
-#include <asm/fsl_dtsec.h>
+#include <fsl_dtsec.h>
#include <asm/fsl_serdes.h>
#include <hwconfig.h>
#include "../common/qixis.h"
diff --git a/board/freescale/t208xrdb/eth_t208xrdb.c b/board/freescale/t208xrdb/eth_t208xrdb.c
index cbbc62583139c7eb2897add7895523d52b88ba2e..ea51195698a86f3ccb2f556b2ebef7268c7f154c 100644
--- a/board/freescale/t208xrdb/eth_t208xrdb.c
+++ b/board/freescale/t208xrdb/eth_t208xrdb.c
@@ -21,7 +21,7 @@
#include <fsl_mdio.h>
#include <miiphy.h>
#include <phy.h>
-#include <asm/fsl_dtsec.h>
+#include <fsl_dtsec.h>
#include <asm/fsl_serdes.h>
int board_eth_init(bd_t *bis)
diff --git a/board/freescale/t4qds/eth.c b/board/freescale/t4qds/eth.c
index 9b416b138ae615872c657bb9e5d80f9eed5ecea9..2dfdcbbd398e126cefd139f8a2d05af5490f4f3e 100644
--- a/board/freescale/t4qds/eth.c
+++ b/board/freescale/t4qds/eth.c
@@ -21,7 +21,7 @@
#include <fsl_mdio.h>
#include <miiphy.h>
#include <phy.h>
-#include <asm/fsl_dtsec.h>
+#include <fsl_dtsec.h>
#include <asm/fsl_serdes.h>
#include <hwconfig.h>
#include "../common/qixis.h"
diff --git a/board/freescale/t4rdb/eth.c b/board/freescale/t4rdb/eth.c
index 879bd1a347b55697f34919d379bd446b6b79d77f..e563a6169aec86dee5fccb78bae346017a1acfd5 100644
--- a/board/freescale/t4rdb/eth.c
+++ b/board/freescale/t4rdb/eth.c
@@ -23,7 +23,7 @@
#include <fsl_mdio.h>
#include <miiphy.h>
#include <phy.h>
-#include <asm/fsl_dtsec.h>
+#include <fsl_dtsec.h>
#include <asm/fsl_serdes.h>
#include <hwconfig.h>
diff --git a/common/board_f.c b/common/board_f.c
index 486e828fe8a740e73fd32fce05b3d7ad26c522b9..7632041b73410bf776cbd8d11bc4a9749ca45a5d 100644
--- a/common/board_f.c
+++ b/common/board_f.c
@@ -806,7 +806,7 @@ static init_fnc_t init_sequence_f[] = {
#if defined(CONFIG_BOARD_POSTCLK_INIT)
board_postclk_init,
#endif
-#ifdef CONFIG_FSL_CLK
+#ifdef CONFIG_SYS_FSL_CLK
get_clocks,
#endif
#ifdef CONFIG_M68K
diff --git a/common/fdt_support.c b/common/fdt_support.c
index f86365e8f0da60caddb0444518e72bb8e46ea0b7..a7ff2dfb81f8ea3cbe54298d9fe758a246c31e55 100644
--- a/common/fdt_support.c
+++ b/common/fdt_support.c
@@ -158,25 +158,30 @@ static int fdt_fixup_stdout(void *fdt, int chosenoff)
aliasoff = fdt_path_offset(fdt, "/aliases");
if (aliasoff < 0) {
err = aliasoff;
- goto error;
+ goto noalias;
}
path = fdt_getprop(fdt, aliasoff, sername, &len);
if (!path) {
err = len;
- goto error;
+ goto noalias;
}
/* fdt_setprop may break "path" so we copy it to tmp buffer */
memcpy(tmp, path, len);
err = fdt_setprop(fdt, chosenoff, "linux,stdout-path", tmp, len);
-error:
if (err < 0)
printf("WARNING: could not set linux,stdout-path %s.\n",
fdt_strerror(err));
return err;
+
+noalias:
+ printf("WARNING: %s: could not read %s alias: %s\n",
+ __func__, sername, fdt_strerror(err));
+
+ return 0;
}
#else
static int fdt_fixup_stdout(void *fdt, int chosenoff)
diff --git a/configs/ls1021atwr_sdcard_defconfig b/configs/ls1021atwr_sdcard_ifc_defconfig
similarity index 82%
rename from configs/ls1021atwr_sdcard_defconfig
rename to configs/ls1021atwr_sdcard_ifc_defconfig
index f1709edb3696d47be60f2d58028923d5f78ce104..2136ab285df1f0f2cc34ba66d3cd543fbc40b960 100644
--- a/configs/ls1021atwr_sdcard_defconfig
+++ b/configs/ls1021atwr_sdcard_ifc_defconfig
@@ -2,6 +2,5 @@ CONFIG_ARM=y
CONFIG_TARGET_LS1021ATWR=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT"
-# CONFIG_CMD_SETEXPR is not set
CONFIG_NETDEVICES=y
CONFIG_E1000=y
diff --git a/configs/ls1021atwr_sdcard_qspi_defconfig b/configs/ls1021atwr_sdcard_qspi_defconfig
new file mode 100644
index 0000000000000000000000000000000000000000..458578b80d79f575d70312ec7949d53e3f5a5f8b
--- /dev/null
+++ b/configs/ls1021atwr_sdcard_qspi_defconfig
@@ -0,0 +1,11 @@
+CONFIG_ARM=y
+CONFIG_TARGET_LS1021ATWR=y
+CONFIG_SPL=y
+CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT,SD_BOOT_QSPI"
+CONFIG_DEFAULT_DEVICE_TREE="ls1021a-twr"
+CONFIG_OF_CONTROL=y
+CONFIG_DM=y
+CONFIG_SPI_FLASH=y
+CONFIG_NETDEVICES=y
+CONFIG_E1000=y
+CONFIG_DM_SPI=y
diff --git a/configs/ls1043ardb_defconfig b/configs/ls1043ardb_defconfig
new file mode 100644
index 0000000000000000000000000000000000000000..ae84d2e5c506dba13e35bdeac6c906841bfd0ebe
--- /dev/null
+++ b/configs/ls1043ardb_defconfig
@@ -0,0 +1,4 @@
+CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4"
+CONFIG_ARM=y
+CONFIG_TARGET_LS1043ARDB=y
+CONFIG_FSL_LAYERSCAPE=y
diff --git a/configs/ls1043ardb_nand_defconfig b/configs/ls1043ardb_nand_defconfig
new file mode 100644
index 0000000000000000000000000000000000000000..fffaca06319e33343ef5aa00970e88c181bf938b
--- /dev/null
+++ b/configs/ls1043ardb_nand_defconfig
@@ -0,0 +1,4 @@
+CONFIG_SPL=y
+CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,NAND_BOOT,SYS_FSL_DDR4"
+CONFIG_ARM=y
+CONFIG_TARGET_LS1043ARDB=y
diff --git a/configs/ls1043ardb_sdcard_defconfig b/configs/ls1043ardb_sdcard_defconfig
new file mode 100644
index 0000000000000000000000000000000000000000..5fe04706c3247ea18bc8dcccdb04ef75901885ae
--- /dev/null
+++ b/configs/ls1043ardb_sdcard_defconfig
@@ -0,0 +1,4 @@
+CONFIG_SPL=y
+CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT,SYS_FSL_DDR4"
+CONFIG_ARM=y
+CONFIG_TARGET_LS1043ARDB=y
diff --git a/configs/ls2085a_simu_defconfig b/configs/ls2085a_simu_defconfig
index de9776d7edec70bda475fe143ae32b9d0f493394..9d04218fa98adc86e9214ceb59cf4d3f553e9dfe 100644
--- a/configs/ls2085a_simu_defconfig
+++ b/configs/ls2085a_simu_defconfig
@@ -12,3 +12,4 @@ CONFIG_SYS_EXTRA_OPTIONS="SIMU"
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NFS is not set
# CONFIG_CMD_MISC is not set
+CONFIG_NET_RANDOM_ETHADDR=y
diff --git a/configs/ls2085aqds_defconfig b/configs/ls2085aqds_defconfig
index 0c770e4ea735ac28fd37315108ec59b03f455385..78b121deaf826924fb9fdfb7ef3b8a985e261e46 100644
--- a/configs/ls2085aqds_defconfig
+++ b/configs/ls2085aqds_defconfig
@@ -7,6 +7,7 @@ CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2085a-qds"
CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4"
# CONFIG_CMD_SETEXPR is not set
CONFIG_OF_CONTROL=y
+CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
diff --git a/configs/ls2085aqds_nand_defconfig b/configs/ls2085aqds_nand_defconfig
index 10eda971ace3a1fea42c0c6e0f16d238198d6a5b..ce2a81cc34aac12638cddad585ea1d1f23d0dfe4 100644
--- a/configs/ls2085aqds_nand_defconfig
+++ b/configs/ls2085aqds_nand_defconfig
@@ -3,5 +3,6 @@ CONFIG_TARGET_LS2085AQDS=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,NAND"
# CONFIG_CMD_SETEXPR is not set
+CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
diff --git a/configs/ls2085ardb_defconfig b/configs/ls2085ardb_defconfig
index 79565330df1213a0787c258712abd74054939b9e..d0f16f2b2df19d42c2c0b33cef92c369b54abc36 100644
--- a/configs/ls2085ardb_defconfig
+++ b/configs/ls2085ardb_defconfig
@@ -7,6 +7,7 @@ CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2085a-rdb"
CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4"
# CONFIG_CMD_SETEXPR is not set
CONFIG_OF_CONTROL=y
+CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
diff --git a/configs/ls2085ardb_nand_defconfig b/configs/ls2085ardb_nand_defconfig
index 96a0dfdc9ca558f64a69921411651b9a5428df70..25a6f71c0164c440d1cfb5afec86214add006573 100644
--- a/configs/ls2085ardb_nand_defconfig
+++ b/configs/ls2085ardb_nand_defconfig
@@ -3,5 +3,6 @@ CONFIG_TARGET_LS2085ARDB=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,NAND"
# CONFIG_CMD_SETEXPR is not set
+CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
diff --git a/doc/README.fsl-clk b/doc/README.fsl-clk
new file mode 100644
index 0000000000000000000000000000000000000000..9e83c24f23a92b28e54f0d5d45e21a7e32633da6
--- /dev/null
+++ b/doc/README.fsl-clk
@@ -0,0 +1,6 @@
+Freescale system clock options
+
+ - CONFIG_SYS_FSL_CLK
+ Enable to call get_clocks() in board_init_f() for
+ non-PPC platforms and PCC 8xx platforms such as
+ TQM866M and TQM885D.
diff --git a/doc/README.fsl-dpaa b/doc/README.fsl-dpaa
index 0d8d4f6efcbcfcec26d21d644bcf2ffbffd137bb..3ef5eeb32e1174c277e45589e649d980b597e36c 100644
--- a/doc/README.fsl-dpaa
+++ b/doc/README.fsl-dpaa
@@ -2,9 +2,9 @@ This file documents Freescale DPAA-specific options.
FMan (Frame Manager)
- CONFIG_FSL_FM_10GEC_REGULAR_NOTATION
- on SoCs earlier(e.g. T4240, T2080), the notation between 10GEC and MAC as below:
+ on SoCs T4240, T2080, LS1043A, etc, the notation between 10GEC and MAC as below:
10GEC1->MAC9, 10GEC2->MAC10, 10GEC3->MAC1, 10GEC4->MAC2
- on SoCs later(e.g. T1024, etc), the notation between 10GEC and MAC as below:
+ on SoCs T1024, etc, the notation between 10GEC and MAC as below:
10GEC1->MAC1, 10GEC2->MAC2
so we introduce CONFIG_FSL_FM_10GEC_REGULAR_NOTATION to identify the new SoCs on
which 10GEC enumeration is consistent with MAC enumeration.
diff --git a/drivers/crypto/fsl/desc_constr.h b/drivers/crypto/fsl/desc_constr.h
index f9cae9144acd17e1fca6e7533c9f794c8b3700fe..2559ccda8c28ecfe80df26cc3c05034cae14d331 100644
--- a/drivers/crypto/fsl/desc_constr.h
+++ b/drivers/crypto/fsl/desc_constr.h
@@ -36,6 +36,23 @@
LDST_SRCDST_WORD_DECOCTRL | \
(LDOFF_ENABLE_AUTO_NFIFO << LDST_OFFSET_SHIFT))
+#ifdef CONFIG_PHYS_64BIT
+union ptr_addr_t {
+ u64 m_whole;
+ struct {
+#ifdef CONFIG_SYS_FSL_SEC_LE
+ u32 low;
+ u32 high;
+#elif defined(CONFIG_SYS_FSL_SEC_BE)
+ u32 high;
+ u32 low;
+#else
+#error Neither CONFIG_SYS_FSL_SEC_LE nor CONFIG_SYS_FSL_SEC_BE is defined
+#endif
+ } m_halfs;
+};
+#endif
+
static inline int desc_len(u32 *desc)
{
return *desc & HDR_DESCLEN_MASK;
@@ -65,7 +82,16 @@ static inline void append_ptr(u32 *desc, dma_addr_t ptr)
{
dma_addr_t *offset = (dma_addr_t *)desc_end(desc);
+#ifdef CONFIG_PHYS_64BIT
+ /* The Position of low and high part of 64 bit address
+ * will depend on the endianness of CAAM Block */
+ union ptr_addr_t ptr_addr;
+ ptr_addr.m_halfs.high = (u32)(ptr >> 32);
+ ptr_addr.m_halfs.low = (u32)ptr;
+ *offset = ptr_addr.m_whole;
+#else
*offset = ptr;
+#endif
(*desc) += CAAM_PTR_SZ / CAAM_CMD_SZ;
}
diff --git a/drivers/crypto/fsl/fsl_hash.c b/drivers/crypto/fsl/fsl_hash.c
index c298404f2526a1a448f3cc4098b287ee49513506..887e88c9ca7a2eeee28e535e65533421cba8f015 100644
--- a/drivers/crypto/fsl/fsl_hash.c
+++ b/drivers/crypto/fsl/fsl_hash.c
@@ -84,7 +84,7 @@ static int caam_hash_update(void *hash_ctx, const void *buf,
enum caam_hash_algos caam_algo)
{
uint32_t final = 0;
- dma_addr_t addr = virt_to_phys((void *)buf);
+ phys_addr_t addr = virt_to_phys((void *)buf);
struct sha_ctx *ctx = hash_ctx;
if (ctx->sg_num >= MAX_SG_32) {
@@ -93,11 +93,11 @@ static int caam_hash_update(void *hash_ctx, const void *buf,
}
#ifdef CONFIG_PHYS_64BIT
- ctx->sg_tbl[ctx->sg_num].addr_hi = addr >> 32;
+ sec_out32(&ctx->sg_tbl[ctx->sg_num].addr_hi, (uint32_t)(addr >> 32));
#else
- ctx->sg_tbl[ctx->sg_num].addr_hi = 0x0;
+ sec_out32(&ctx->sg_tbl[ctx->sg_num].addr_hi, 0x0);
#endif
- ctx->sg_tbl[ctx->sg_num].addr_lo = addr;
+ sec_out32(&ctx->sg_tbl[ctx->sg_num].addr_lo, (uint32_t)addr);
sec_out32(&ctx->sg_tbl[ctx->sg_num].len_flag,
(size & SG_ENTRY_LENGTH_MASK));
diff --git a/drivers/crypto/fsl/jr.c b/drivers/crypto/fsl/jr.c
index 17392c9813fbeed71cf36404e3fa379a96669cd3..f63eacb73eb0575b52a0eacf1e44b7d62b2dacb4 100644
--- a/drivers/crypto/fsl/jr.c
+++ b/drivers/crypto/fsl/jr.c
@@ -11,6 +11,7 @@
#include "fsl_sec.h"
#include "jr.h"
#include "jobdesc.h"
+#include "desc_constr.h"
#define CIRC_CNT(head, tail, size) (((head) - (tail)) & (size - 1))
#define CIRC_SPACE(head, tail, size) CIRC_CNT((tail), (head) + 1, (size))
@@ -154,19 +155,35 @@ static int jr_hw_reset(void)
/* -1 --- error, can't enqueue -- no space available */
static int jr_enqueue(uint32_t *desc_addr,
- void (*callback)(uint32_t desc, uint32_t status, void *arg),
+ void (*callback)(uint32_t status, void *arg),
void *arg)
{
struct jr_regs *regs = (struct jr_regs *)CONFIG_SYS_FSL_JR0_ADDR;
int head = jr.head;
- dma_addr_t desc_phys_addr = virt_to_phys(desc_addr);
+ uint32_t desc_word;
+ int length = desc_len(desc_addr);
+ int i;
+#ifdef CONFIG_PHYS_64BIT
+ uint32_t *addr_hi, *addr_lo;
+#endif
+
+ /* The descriptor must be submitted to SEC block as per endianness
+ * of the SEC Block.
+ * So, if the endianness of Core and SEC block is different, each word
+ * of the descriptor will be byte-swapped.
+ */
+ for (i = 0; i < length; i++) {
+ desc_word = desc_addr[i];
+ sec_out32((uint32_t *)&desc_addr[i], desc_word);
+ }
+
+ phys_addr_t desc_phys_addr = virt_to_phys(desc_addr);
if (sec_in32(®s->irsa) == 0 ||
CIRC_SPACE(jr.head, jr.tail, jr.size) <= 0)
return -1;
jr.info[head].desc_phys_addr = desc_phys_addr;
- jr.info[head].desc_addr = (uint32_t)desc_addr;
jr.info[head].callback = (void *)callback;
jr.info[head].arg = arg;
jr.info[head].op_done = 0;
@@ -177,9 +194,29 @@ static int jr_enqueue(uint32_t *desc_addr,
ARCH_DMA_MINALIGN);
flush_dcache_range(start, end);
- jr.input_ring[head] = desc_phys_addr;
+#ifdef CONFIG_PHYS_64BIT
+ /* Write the 64 bit Descriptor address on Input Ring.
+ * The 32 bit hign and low part of the address will
+ * depend on endianness of SEC block.
+ */
+#ifdef CONFIG_SYS_FSL_SEC_LE
+ addr_lo = (uint32_t *)(&jr.input_ring[head]);
+ addr_hi = (uint32_t *)(&jr.input_ring[head]) + 1;
+#elif defined(CONFIG_SYS_FSL_SEC_BE)
+ addr_hi = (uint32_t *)(&jr.input_ring[head]);
+ addr_lo = (uint32_t *)(&jr.input_ring[head]) + 1;
+#endif /* ifdef CONFIG_SYS_FSL_SEC_LE */
+
+ sec_out32(addr_hi, (uint32_t)(desc_phys_addr >> 32));
+ sec_out32(addr_lo, (uint32_t)(desc_phys_addr));
+
+#else
+ /* Write the 32 bit Descriptor address on Input Ring. */
+ sec_out32(&jr.input_ring[head], desc_phys_addr);
+#endif /* ifdef CONFIG_PHYS_64BIT */
+
start = (unsigned long)&jr.input_ring[head] & ~(ARCH_DMA_MINALIGN - 1);
- end = ALIGN(start + sizeof(dma_addr_t), ARCH_DMA_MINALIGN);
+ end = ALIGN(start + sizeof(phys_addr_t), ARCH_DMA_MINALIGN);
flush_dcache_range(start, end);
jr.head = (head + 1) & (jr.size - 1);
@@ -195,8 +232,13 @@ static int jr_dequeue(void)
int head = jr.head;
int tail = jr.tail;
int idx, i, found;
- void (*callback)(uint32_t desc, uint32_t status, void *arg);
+ void (*callback)(uint32_t status, void *arg);
void *arg = NULL;
+#ifdef CONFIG_PHYS_64BIT
+ uint32_t *addr_hi, *addr_lo;
+#else
+ uint32_t *addr;
+#endif
while (sec_in32(®s->orsf) && CIRC_CNT(jr.head, jr.tail, jr.size)) {
unsigned long start = (unsigned long)jr.output_ring &
@@ -208,14 +250,34 @@ static int jr_dequeue(void)
found = 0;
- dma_addr_t op_desc = jr.output_ring[jr.tail].desc;
- uint32_t status = jr.output_ring[jr.tail].status;
- uint32_t desc_virt;
+ phys_addr_t op_desc;
+ #ifdef CONFIG_PHYS_64BIT
+ /* Read the 64 bit Descriptor address from Output Ring.
+ * The 32 bit hign and low part of the address will
+ * depend on endianness of SEC block.
+ */
+ #ifdef CONFIG_SYS_FSL_SEC_LE
+ addr_lo = (uint32_t *)(&jr.output_ring[jr.tail].desc);
+ addr_hi = (uint32_t *)(&jr.output_ring[jr.tail].desc) + 1;
+ #elif defined(CONFIG_SYS_FSL_SEC_BE)
+ addr_hi = (uint32_t *)(&jr.output_ring[jr.tail].desc);
+ addr_lo = (uint32_t *)(&jr.output_ring[jr.tail].desc) + 1;
+ #endif /* ifdef CONFIG_SYS_FSL_SEC_LE */
+
+ op_desc = ((u64)sec_in32(addr_hi) << 32) |
+ ((u64)sec_in32(addr_lo));
+
+ #else
+ /* Read the 32 bit Descriptor address from Output Ring. */
+ addr = (uint32_t *)&jr.output_ring[jr.tail].desc;
+ op_desc = sec_in32(addr);
+ #endif /* ifdef CONFIG_PHYS_64BIT */
+
+ uint32_t status = sec_in32(&jr.output_ring[jr.tail].status);
for (i = 0; CIRC_CNT(head, tail + i, jr.size) >= 1; i++) {
idx = (tail + i) & (jr.size - 1);
if (op_desc == jr.info[idx].desc_phys_addr) {
- desc_virt = jr.info[idx].desc_addr;
found = 1;
break;
}
@@ -244,13 +306,13 @@ static int jr_dequeue(void)
sec_out32(®s->orjr, 1);
jr.info[idx].op_done = 0;
- callback(desc_virt, status, arg);
+ callback(status, arg);
}
return 0;
}
-static void desc_done(uint32_t desc, uint32_t status, void *arg)
+static void desc_done(uint32_t status, void *arg)
{
struct result *x = arg;
x->status = status;
diff --git a/drivers/crypto/fsl/jr.h b/drivers/crypto/fsl/jr.h
index 152606008845aa2e327713c53b01d51d2587aa25..5899696e8adf8693013cf9caf3f4f55e1e27084e 100644
--- a/drivers/crypto/fsl/jr.h
+++ b/drivers/crypto/fsl/jr.h
@@ -37,14 +37,13 @@
#define JQ_ENQ_ERR -3
struct op_ring {
- dma_addr_t desc;
+ phys_addr_t desc;
uint32_t status;
} __packed;
struct jr_info {
- void (*callback)(dma_addr_t desc, uint32_t status, void *arg);
- dma_addr_t desc_phys_addr;
- uint32_t desc_addr;
+ void (*callback)(uint32_t status, void *arg);
+ phys_addr_t desc_phys_addr;
uint32_t desc_len;
uint32_t op_done;
void *arg;
diff --git a/drivers/ddr/fsl/ctrl_regs.c b/drivers/ddr/fsl/ctrl_regs.c
index 8367c95cf82ba9e9fb0d268afbb17d717c99d0ef..8543679108751b1597137ecc8e859226d71fdb9b 100644
--- a/drivers/ddr/fsl/ctrl_regs.c
+++ b/drivers/ddr/fsl/ctrl_regs.c
@@ -858,7 +858,7 @@ static void set_ddr_sdram_cfg_2(const unsigned int ctrl_num,
break;
}
}
-
+ sr_ie = popts->self_refresh_interrupt_en;
num_pr = 1; /* Make this configurable */
/*
diff --git a/drivers/i2c/mxc_i2c.c b/drivers/i2c/mxc_i2c.c
index 0f977d706d4f409f92e2b13bd8c6625d854a19f5..fa4c82f1a25b0775c7e69e97dbc178fd32f06539 100644
--- a/drivers/i2c/mxc_i2c.c
+++ b/drivers/i2c/mxc_i2c.c
@@ -523,8 +523,8 @@ static int bus_i2c_write(struct mxc_i2c_bus *i2c_bus, u8 chip, u32 addr,
#endif
static struct mxc_i2c_bus mxc_i2c_buses[] = {
-#if defined(CONFIG_LS102XA) || defined(CONFIG_FSL_LSCH3) || \
- defined(CONFIG_VF610)
+#if defined(CONFIG_LS102XA) || defined(CONFIG_VF610) || \
+ defined(CONFIG_FSL_LAYERSCAPE)
{ 0, I2C1_BASE_ADDR, I2C_QUIRK_FLAG },
{ 1, I2C2_BASE_ADDR, I2C_QUIRK_FLAG },
{ 2, I2C3_BASE_ADDR, I2C_QUIRK_FLAG },
diff --git a/drivers/misc/fsl_debug_server.c b/drivers/misc/fsl_debug_server.c
index a592891f26f0eb9799e646ad2846651166476997..98d9fbe534c3bd9511c4f2dfd4a4be3957b4241c 100644
--- a/drivers/misc/fsl_debug_server.c
+++ b/drivers/misc/fsl_debug_server.c
@@ -8,7 +8,6 @@
#include <errno.h>
#include <asm/io.h>
#include <asm/system.h>
-#include <asm/arch-fsl-lsch3/immap_lsch3.h>
#include <fsl-mc/fsl_mc.h>
#include <fsl_debug_server.h>
diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c
index 0b370026592eac36cf127b2ce6eb7c9df7b4cd2c..471d6ee4a63bc63dcc06a9515542a2e054aad90b 100644
--- a/drivers/mmc/fsl_esdhc.c
+++ b/drivers/mmc/fsl_esdhc.c
@@ -106,7 +106,7 @@ static uint esdhc_xfertyp(struct mmc_cmd *cmd, struct mmc_data *data)
xfertyp |= XFERTYP_RSPTYP_48;
#if defined(CONFIG_MX53) || defined(CONFIG_PPC_T4240) || \
- defined(CONFIG_LS102XA) || defined(CONFIG_LS2085A)
+ defined(CONFIG_LS102XA) || defined(CONFIG_FSL_LAYERSCAPE)
if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
xfertyp |= XFERTYP_CMDTYP_ABORT;
#endif
@@ -184,7 +184,7 @@ static int esdhc_setup_data(struct mmc *mmc, struct mmc_data *data)
int timeout;
struct fsl_esdhc_cfg *cfg = mmc->priv;
struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
-#ifdef CONFIG_LS2085A
+#ifdef CONFIG_FSL_LAYERSCAPE
dma_addr_t addr;
#endif
uint wml_value;
@@ -197,7 +197,7 @@ static int esdhc_setup_data(struct mmc *mmc, struct mmc_data *data)
esdhc_clrsetbits32(®s->wml, WML_RD_WML_MASK, wml_value);
#ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
-#ifdef CONFIG_LS2085A
+#ifdef CONFIG_FSL_LAYERSCAPE
addr = virt_to_phys((void *)(data->dest));
if (upper_32_bits(addr))
printf("Error found for upper 32 bits\n");
@@ -223,7 +223,7 @@ static int esdhc_setup_data(struct mmc *mmc, struct mmc_data *data)
esdhc_clrsetbits32(®s->wml, WML_WR_WML_MASK,
wml_value << 16);
#ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
-#ifdef CONFIG_LS2085A
+#ifdef CONFIG_FSL_LAYERSCAPE
addr = virt_to_phys((void *)(data->src));
if (upper_32_bits(addr))
printf("Error found for upper 32 bits\n");
@@ -277,7 +277,7 @@ static int esdhc_setup_data(struct mmc *mmc, struct mmc_data *data)
static void check_and_invalidate_dcache_range
(struct mmc_cmd *cmd,
struct mmc_data *data) {
-#ifdef CONFIG_LS2085A
+#ifdef CONFIG_FSL_LAYERSCAPE
unsigned start = 0;
#else
unsigned start = (unsigned)data->dest ;
@@ -285,7 +285,7 @@ static void check_and_invalidate_dcache_range
unsigned size = roundup(ARCH_DMA_MINALIGN,
data->blocks*data->blocksize);
unsigned end = start+size ;
-#ifdef CONFIG_LS2085A
+#ifdef CONFIG_FSL_LAYERSCAPE
dma_addr_t addr;
addr = virt_to_phys((void *)(data->dest));
diff --git a/drivers/net/fm/Makefile b/drivers/net/fm/Makefile
index d052fcb372cbf590fa7c45bc1c23ee117300f459..a3c9f9962760c23dd44c2281d7f29dc0b2f13097 100644
--- a/drivers/net/fm/Makefile
+++ b/drivers/net/fm/Makefile
@@ -37,3 +37,4 @@ obj-$(CONFIG_PPC_T4160) += t4240.o
obj-$(CONFIG_PPC_T4080) += t4240.o
obj-$(CONFIG_PPC_B4420) += b4860.o
obj-$(CONFIG_PPC_B4860) += b4860.o
+obj-$(CONFIG_LS1043A) += ls1043.o
diff --git a/drivers/net/fm/dtsec.c b/drivers/net/fm/dtsec.c
index 8d3dc0e308cefe2ca2d9f9f7f45b1d178fe4077a..b339a84e59af3efa4b6d2e90d778993058e8393e 100644
--- a/drivers/net/fm/dtsec.c
+++ b/drivers/net/fm/dtsec.c
@@ -7,7 +7,7 @@
#include <common.h>
#include <asm/types.h>
#include <asm/io.h>
-#include <asm/fsl_dtsec.h>
+#include <fsl_dtsec.h>
#include <fsl_mdio.h>
#include <phy.h>
diff --git a/drivers/net/fm/eth.c b/drivers/net/fm/eth.c
index 6702f5a5202809a56ef9c73c1c2c60fd86a78f34..eb8e93618f27614aad40287f0ad794e2273c977b 100644
--- a/drivers/net/fm/eth.c
+++ b/drivers/net/fm/eth.c
@@ -13,8 +13,8 @@
#include <fsl_mdio.h>
#include <miiphy.h>
#include <phy.h>
-#include <asm/fsl_dtsec.h>
-#include <asm/fsl_tgec.h>
+#include <fsl_dtsec.h>
+#include <fsl_tgec.h>
#include <fsl_memac.h>
#include "fm.h"
@@ -41,28 +41,35 @@ static void dtsec_configure_serdes(struct fm_eth *priv)
bus.priv = priv->mac->phyregs;
bool sgmii_2500 = (priv->enet_if ==
PHY_INTERFACE_MODE_SGMII_2500) ? true : false;
+ int i = 0;
+qsgmii_loop:
/* SGMII IF mode + AN enable only for 1G SGMII, not for 2.5G */
value = PHY_SGMII_IF_MODE_SGMII;
if (!sgmii_2500)
value |= PHY_SGMII_IF_MODE_AN;
- memac_mdio_write(&bus, 0, MDIO_DEVAD_NONE, 0x14, value);
+ memac_mdio_write(&bus, i, MDIO_DEVAD_NONE, 0x14, value);
/* Dev ability according to SGMII specification */
value = PHY_SGMII_DEV_ABILITY_SGMII;
- memac_mdio_write(&bus, 0, MDIO_DEVAD_NONE, 0x4, value);
+ memac_mdio_write(&bus, i, MDIO_DEVAD_NONE, 0x4, value);
/* Adjust link timer for SGMII -
1.6 ms in units of 8 ns = 2 * 10^5 = 0x30d40 */
- memac_mdio_write(&bus, 0, MDIO_DEVAD_NONE, 0x13, 0x3);
- memac_mdio_write(&bus, 0, MDIO_DEVAD_NONE, 0x12, 0xd40);
+ memac_mdio_write(&bus, i, MDIO_DEVAD_NONE, 0x13, 0x3);
+ memac_mdio_write(&bus, i, MDIO_DEVAD_NONE, 0x12, 0xd40);
/* Restart AN */
value = PHY_SGMII_CR_DEF_VAL;
if (!sgmii_2500)
value |= PHY_SGMII_CR_RESET_AN;
- memac_mdio_write(&bus, 0, MDIO_DEVAD_NONE, 0, value);
+ memac_mdio_write(&bus, i, MDIO_DEVAD_NONE, 0, value);
+
+ if ((priv->enet_if == PHY_INTERFACE_MODE_QSGMII) && (i < 3)) {
+ i++;
+ goto qsgmii_loop;
+ }
#else
struct dtsec *regs = priv->mac->base;
struct tsec_mii_mng *phyregs = priv->mac->phyregs;
@@ -91,10 +98,12 @@ static void dtsec_init_phy(struct eth_device *dev)
#endif
if (fm_eth->enet_if == PHY_INTERFACE_MODE_SGMII ||
+ fm_eth->enet_if == PHY_INTERFACE_MODE_QSGMII ||
fm_eth->enet_if == PHY_INTERFACE_MODE_SGMII_2500)
dtsec_configure_serdes(fm_eth);
}
+#ifdef CONFIG_PHYLIB
static int tgec_is_fibre(struct eth_device *dev)
{
struct fm_eth *fm = dev->priv;
@@ -105,15 +114,16 @@ static int tgec_is_fibre(struct eth_device *dev)
return hwconfig_arg_cmp(phyopt, "xfi");
}
#endif
+#endif
static u16 muram_readw(u16 *addr)
{
- u32 base = (u32)addr & ~0x3;
- u32 val32 = *(u32 *)base;
+ ulong base = (ulong)addr & ~0x3UL;
+ u32 val32 = in_be32((void *)base);
int byte_pos;
u16 ret;
- byte_pos = (u32)addr & 0x3;
+ byte_pos = (ulong)addr & 0x3UL;
if (byte_pos)
ret = (u16)(val32 & 0x0000ffff);
else
@@ -124,18 +134,18 @@ static u16 muram_readw(u16 *addr)
static void muram_writew(u16 *addr, u16 val)
{
- u32 base = (u32)addr & ~0x3;
- u32 org32 = *(u32 *)base;
+ ulong base = (ulong)addr & ~0x3UL;
+ u32 org32 = in_be32((void *)base);
u32 val32;
int byte_pos;
- byte_pos = (u32)addr & 0x3;
+ byte_pos = (ulong)addr & 0x3UL;
if (byte_pos)
val32 = (org32 & 0xffff0000) | val;
else
val32 = (org32 & 0x0000ffff) | ((u32)val << 16);
- *(u32 *)base = val32;
+ out_be32((void *)base, val32);
}
static void bmi_rx_port_disable(struct fm_bmi_rx_port *rx_port)
@@ -199,6 +209,8 @@ static int fm_eth_rx_port_parameter_init(struct fm_eth *fm_eth)
u32 pram_page_offset;
void *rx_bd_ring_base;
void *rx_buf_pool;
+ u32 bd_ring_base_lo, bd_ring_base_hi;
+ u32 buf_lo, buf_hi;
struct fm_port_bd *rxbd;
struct fm_port_qd *rxqd;
struct fm_bmi_rx_port *bmi_rx_port = fm_eth->rx_port;
@@ -207,16 +219,21 @@ static int fm_eth_rx_port_parameter_init(struct fm_eth *fm_eth)
/* alloc global parameter ram at MURAM */
pram = (struct fm_port_global_pram *)fm_muram_alloc(fm_eth->fm_index,
FM_PRAM_SIZE, FM_PRAM_ALIGN);
+ if (!pram) {
+ printf("%s: No muram for Rx global parameter\n", __func__);
+ return -ENOMEM;
+ }
+
fm_eth->rx_pram = pram;
/* parameter page offset to MURAM */
- pram_page_offset = (u32)pram - fm_muram_base(fm_eth->fm_index);
+ pram_page_offset = (void *)pram - fm_muram_base(fm_eth->fm_index);
/* enable global mode- snooping data buffers and BDs */
- pram->mode = PRAM_MODE_GLOBAL;
+ out_be32(&pram->mode, PRAM_MODE_GLOBAL);
/* init the Rx queue descriptor pionter */
- pram->rxqd_ptr = pram_page_offset + 0x20;
+ out_be32(&pram->rxqd_ptr, pram_page_offset + 0x20);
/* set the max receive buffer length, power of 2 */
muram_writew(&pram->mrblr, MAX_RXBUF_LOG2);
@@ -225,15 +242,18 @@ static int fm_eth_rx_port_parameter_init(struct fm_eth *fm_eth)
rx_bd_ring_base = malloc(sizeof(struct fm_port_bd)
* RX_BD_RING_SIZE);
if (!rx_bd_ring_base)
- return 0;
+ return -ENOMEM;
+
memset(rx_bd_ring_base, 0, sizeof(struct fm_port_bd)
* RX_BD_RING_SIZE);
/* alloc Rx buffer from main memory */
rx_buf_pool = malloc(MAX_RXBUF_LEN * RX_BD_RING_SIZE);
if (!rx_buf_pool)
- return 0;
+ return -ENOMEM;
+
memset(rx_buf_pool, 0, MAX_RXBUF_LEN * RX_BD_RING_SIZE);
+ debug("%s: rx_buf_pool = %p\n", __func__, rx_buf_pool);
/* save them to fm_eth */
fm_eth->rx_bd_ring = rx_bd_ring_base;
@@ -243,18 +263,24 @@ static int fm_eth_rx_port_parameter_init(struct fm_eth *fm_eth)
/* init Rx BDs ring */
rxbd = (struct fm_port_bd *)rx_bd_ring_base;
for (i = 0; i < RX_BD_RING_SIZE; i++) {
- rxbd->status = RxBD_EMPTY;
- rxbd->len = 0;
- rxbd->buf_ptr_hi = 0;
- rxbd->buf_ptr_lo = (u32)rx_buf_pool + i * MAX_RXBUF_LEN;
+ muram_writew(&rxbd->status, RxBD_EMPTY);
+ muram_writew(&rxbd->len, 0);
+ buf_hi = upper_32_bits(virt_to_phys(rx_buf_pool +
+ i * MAX_RXBUF_LEN));
+ buf_lo = lower_32_bits(virt_to_phys(rx_buf_pool +
+ i * MAX_RXBUF_LEN));
+ muram_writew(&rxbd->buf_ptr_hi, (u16)buf_hi);
+ out_be32(&rxbd->buf_ptr_lo, buf_lo);
rxbd++;
}
/* set the Rx queue descriptor */
rxqd = &pram->rxqd;
muram_writew(&rxqd->gen, 0);
- muram_writew(&rxqd->bd_ring_base_hi, 0);
- rxqd->bd_ring_base_lo = (u32)rx_bd_ring_base;
+ bd_ring_base_hi = upper_32_bits(virt_to_phys(rx_bd_ring_base));
+ bd_ring_base_lo = lower_32_bits(virt_to_phys(rx_bd_ring_base));
+ muram_writew(&rxqd->bd_ring_base_hi, (u16)bd_ring_base_hi);
+ out_be32(&rxqd->bd_ring_base_lo, bd_ring_base_lo);
muram_writew(&rxqd->bd_ring_size, sizeof(struct fm_port_bd)
* RX_BD_RING_SIZE);
muram_writew(&rxqd->offset_in, 0);
@@ -263,7 +289,7 @@ static int fm_eth_rx_port_parameter_init(struct fm_eth *fm_eth)
/* set IM parameter ram pointer to Rx Frame Queue ID */
out_be32(&bmi_rx_port->fmbm_rfqid, pram_page_offset);
- return 1;
+ return 0;
}
static int fm_eth_tx_port_parameter_init(struct fm_eth *fm_eth)
@@ -271,6 +297,7 @@ static int fm_eth_tx_port_parameter_init(struct fm_eth *fm_eth)
struct fm_port_global_pram *pram;
u32 pram_page_offset;
void *tx_bd_ring_base;
+ u32 bd_ring_base_lo, bd_ring_base_hi;
struct fm_port_bd *txbd;
struct fm_port_qd *txqd;
struct fm_bmi_tx_port *bmi_tx_port = fm_eth->tx_port;
@@ -279,22 +306,27 @@ static int fm_eth_tx_port_parameter_init(struct fm_eth *fm_eth)
/* alloc global parameter ram at MURAM */
pram = (struct fm_port_global_pram *)fm_muram_alloc(fm_eth->fm_index,
FM_PRAM_SIZE, FM_PRAM_ALIGN);
+ if (!pram) {
+ printf("%s: No muram for Tx global parameter\n", __func__);
+ return -ENOMEM;
+ }
fm_eth->tx_pram = pram;
/* parameter page offset to MURAM */
- pram_page_offset = (u32)pram - fm_muram_base(fm_eth->fm_index);
+ pram_page_offset = (void *)pram - fm_muram_base(fm_eth->fm_index);
/* enable global mode- snooping data buffers and BDs */
- pram->mode = PRAM_MODE_GLOBAL;
+ out_be32(&pram->mode, PRAM_MODE_GLOBAL);
/* init the Tx queue descriptor pionter */
- pram->txqd_ptr = pram_page_offset + 0x40;
+ out_be32(&pram->txqd_ptr, pram_page_offset + 0x40);
/* alloc Tx buffer descriptors from main memory */
tx_bd_ring_base = malloc(sizeof(struct fm_port_bd)
* TX_BD_RING_SIZE);
if (!tx_bd_ring_base)
- return 0;
+ return -ENOMEM;
+
memset(tx_bd_ring_base, 0, sizeof(struct fm_port_bd)
* TX_BD_RING_SIZE);
/* save it to fm_eth */
@@ -304,16 +336,19 @@ static int fm_eth_tx_port_parameter_init(struct fm_eth *fm_eth)
/* init Tx BDs ring */
txbd = (struct fm_port_bd *)tx_bd_ring_base;
for (i = 0; i < TX_BD_RING_SIZE; i++) {
- txbd->status = TxBD_LAST;
- txbd->len = 0;
- txbd->buf_ptr_hi = 0;
- txbd->buf_ptr_lo = 0;
+ muram_writew(&txbd->status, TxBD_LAST);
+ muram_writew(&txbd->len, 0);
+ muram_writew(&txbd->buf_ptr_hi, 0);
+ out_be32(&txbd->buf_ptr_lo, 0);
+ txbd++;
}
/* set the Tx queue decriptor */
txqd = &pram->txqd;
- muram_writew(&txqd->bd_ring_base_hi, 0);
- txqd->bd_ring_base_lo = (u32)tx_bd_ring_base;
+ bd_ring_base_hi = upper_32_bits(virt_to_phys(tx_bd_ring_base));
+ bd_ring_base_lo = lower_32_bits(virt_to_phys(tx_bd_ring_base));
+ muram_writew(&txqd->bd_ring_base_hi, (u16)bd_ring_base_hi);
+ out_be32(&txqd->bd_ring_base_lo, bd_ring_base_lo);
muram_writew(&txqd->bd_ring_size, sizeof(struct fm_port_bd)
* TX_BD_RING_SIZE);
muram_writew(&txqd->offset_in, 0);
@@ -322,29 +357,35 @@ static int fm_eth_tx_port_parameter_init(struct fm_eth *fm_eth)
/* set IM parameter ram pointer to Tx Confirmation Frame Queue ID */
out_be32(&bmi_tx_port->fmbm_tcfqid, pram_page_offset);
- return 1;
+ return 0;
}
static int fm_eth_init(struct fm_eth *fm_eth)
{
+ int ret;
- if (!fm_eth_rx_port_parameter_init(fm_eth))
- return 0;
+ ret = fm_eth_rx_port_parameter_init(fm_eth);
+ if (ret)
+ return ret;
- if (!fm_eth_tx_port_parameter_init(fm_eth))
- return 0;
+ ret = fm_eth_tx_port_parameter_init(fm_eth);
+ if (ret)
+ return ret;
- return 1;
+ return 0;
}
static int fm_eth_startup(struct fm_eth *fm_eth)
{
struct fsl_enet_mac *mac;
+ int ret;
+
mac = fm_eth->mac;
/* Rx/TxBDs, Rx/TxQDs, Rx buff and parameter ram init */
- if (!fm_eth_init(fm_eth))
- return 0;
+ ret = fm_eth_init(fm_eth);
+ if (ret)
+ return ret;
/* setup the MAC controller */
mac->init_mac(mac);
@@ -359,7 +400,7 @@ static int fm_eth_startup(struct fm_eth *fm_eth)
/* init bmi tx port, IM mode and disable */
bmi_tx_port_init(fm_eth->tx_port);
- return 1;
+ return 0;
}
static void fmc_tx_port_graceful_stop_enable(struct fm_eth *fm_eth)
@@ -368,7 +409,7 @@ static void fmc_tx_port_graceful_stop_enable(struct fm_eth *fm_eth)
pram = fm_eth->tx_pram;
/* graceful stop transmission of frames */
- pram->mode |= PRAM_MODE_GRACEFUL_STOP;
+ setbits_be32(&pram->mode, PRAM_MODE_GRACEFUL_STOP);
sync();
}
@@ -378,7 +419,7 @@ static void fmc_tx_port_graceful_stop_disable(struct fm_eth *fm_eth)
pram = fm_eth->tx_pram;
/* re-enable transmission of frames */
- pram->mode &= ~PRAM_MODE_GRACEFUL_STOP;
+ clrbits_be32(&pram->mode, PRAM_MODE_GRACEFUL_STOP);
sync();
}
@@ -452,8 +493,10 @@ static void fm_eth_halt(struct eth_device *dev)
/* disable bmi Rx port */
bmi_rx_port_disable(fm_eth->rx_port);
+#ifdef CONFIG_PHYLIB
if (fm_eth->phydev)
phy_shutdown(fm_eth->phydev);
+#endif
}
static int fm_eth_send(struct eth_device *dev, void *buf, int len)
@@ -469,19 +512,20 @@ static int fm_eth_send(struct eth_device *dev, void *buf, int len)
txbd = fm_eth->cur_txbd;
/* find one empty TxBD */
- for (i = 0; txbd->status & TxBD_READY; i++) {
+ for (i = 0; muram_readw(&txbd->status) & TxBD_READY; i++) {
udelay(100);
if (i > 0x1000) {
- printf("%s: Tx buffer not ready\n", dev->name);
+ printf("%s: Tx buffer not ready, txbd->status = 0x%x\n",
+ dev->name, muram_readw(&txbd->status));
return 0;
}
}
/* setup TxBD */
- txbd->buf_ptr_hi = 0;
- txbd->buf_ptr_lo = (u32)buf;
- txbd->len = len;
+ muram_writew(&txbd->buf_ptr_hi, (u16)upper_32_bits(virt_to_phys(buf)));
+ out_be32(&txbd->buf_ptr_lo, lower_32_bits(virt_to_phys(buf)));
+ muram_writew(&txbd->len, len);
sync();
- txbd->status = TxBD_READY | TxBD_LAST;
+ muram_writew(&txbd->status, TxBD_READY | TxBD_LAST);
sync();
/* update TxQD, let RISC to send the packet */
@@ -493,10 +537,11 @@ static int fm_eth_send(struct eth_device *dev, void *buf, int len)
sync();
/* wait for buffer to be transmitted */
- for (i = 0; txbd->status & TxBD_READY; i++) {
+ for (i = 0; muram_readw(&txbd->status) & TxBD_READY; i++) {
udelay(100);
if (i > 0x10000) {
- printf("%s: Tx error\n", dev->name);
+ printf("%s: Tx error, txbd->status = 0x%x\n",
+ dev->name, muram_readw(&txbd->status));
return 0;
}
}
@@ -518,6 +563,7 @@ static int fm_eth_recv(struct eth_device *dev)
struct fm_port_global_pram *pram;
struct fm_port_bd *rxbd, *rxbd_base;
u16 status, len;
+ u32 buf_lo, buf_hi;
u8 *data;
u16 offset_out;
int ret = 1;
@@ -525,12 +571,14 @@ static int fm_eth_recv(struct eth_device *dev)
fm_eth = (struct fm_eth *)dev->priv;
pram = fm_eth->rx_pram;
rxbd = fm_eth->cur_rxbd;
- status = rxbd->status;
+ status = muram_readw(&rxbd->status);
while (!(status & RxBD_EMPTY)) {
if (!(status & RxBD_ERROR)) {
- data = (u8 *)rxbd->buf_ptr_lo;
- len = rxbd->len;
+ buf_hi = muram_readw(&rxbd->buf_ptr_hi);
+ buf_lo = in_be32(&rxbd->buf_ptr_lo);
+ data = (u8 *)((ulong)(buf_hi << 16) << 16 | buf_lo);
+ len = muram_readw(&rxbd->len);
net_process_received_packet(data, len);
} else {
printf("%s: Rx error\n", dev->name);
@@ -538,8 +586,8 @@ static int fm_eth_recv(struct eth_device *dev)
}
/* clear the RxBDs */
- rxbd->status = RxBD_EMPTY;
- rxbd->len = 0;
+ muram_writew(&rxbd->status, RxBD_EMPTY);
+ muram_writew(&rxbd->len, 0);
sync();
/* advance RxBD */
@@ -548,7 +596,7 @@ static int fm_eth_recv(struct eth_device *dev)
if (rxbd >= (rxbd_base + RX_BD_RING_SIZE))
rxbd = rxbd_base;
/* read next status */
- status = rxbd->status;
+ status = muram_readw(&rxbd->status);
/* update RxQD */
offset_out = muram_readw(&pram->rxqd.offset_out);
@@ -601,7 +649,7 @@ static int fm_eth_init_mac(struct fm_eth *fm_eth, struct ccsr_fman *reg)
/* alloc mac controller */
mac = malloc(sizeof(struct fsl_enet_mac));
if (!mac)
- return 0;
+ return -ENOMEM;
memset(mac, 0, sizeof(struct fsl_enet_mac));
/* save the mac to fm_eth struct */
@@ -616,19 +664,21 @@ static int fm_eth_init_mac(struct fm_eth *fm_eth, struct ccsr_fman *reg)
init_tgec(mac, base, phyregs, MAX_RXBUF_LEN);
#endif
- return 1;
+ return 0;
}
static int init_phy(struct eth_device *dev)
{
struct fm_eth *fm_eth = dev->priv;
+#ifdef CONFIG_PHYLIB
struct phy_device *phydev = NULL;
u32 supported;
+#endif
-#ifdef CONFIG_PHYLIB
if (fm_eth->type == FM_ETH_1G_E)
dtsec_init_phy(dev);
+#ifdef CONFIG_PHYLIB
if (fm_eth->bus) {
phydev = phy_connect(fm_eth->bus, fm_eth->phyaddr, dev,
fm_eth->enet_if);
@@ -669,17 +719,18 @@ int fm_eth_initialize(struct ccsr_fman *reg, struct fm_eth_info *info)
struct eth_device *dev;
struct fm_eth *fm_eth;
int i, num = info->num;
+ int ret;
/* alloc eth device */
dev = (struct eth_device *)malloc(sizeof(struct eth_device));
if (!dev)
- return 0;
+ return -ENOMEM;
memset(dev, 0, sizeof(struct eth_device));
/* alloc the FMan ethernet private struct */
fm_eth = (struct fm_eth *)malloc(sizeof(struct fm_eth));
if (!fm_eth)
- return 0;
+ return -ENOMEM;
memset(fm_eth, 0, sizeof(struct fm_eth));
/* save off some things we need from the info struct */
@@ -694,8 +745,9 @@ int fm_eth_initialize(struct ccsr_fman *reg, struct fm_eth_info *info)
fm_eth->max_rx_len = MAX_RXBUF_LEN;
/* init global mac structure */
- if (!fm_eth_init_mac(fm_eth, reg))
- return 0;
+ ret = fm_eth_init_mac(fm_eth, reg);
+ if (ret)
+ return ret;
/* keep same as the manual, we call FMAN1, FMAN2, DTSEC1, DTSEC2, etc */
if (fm_eth->type == FM_ETH_1G_E)
@@ -716,8 +768,9 @@ int fm_eth_initialize(struct ccsr_fman *reg, struct fm_eth_info *info)
fm_eth->enet_if = info->enet_if;
/* startup the FM im */
- if (!fm_eth_startup(fm_eth))
- return 0;
+ ret = fm_eth_startup(fm_eth);
+ if (ret)
+ return ret;
init_phy(dev);
@@ -726,5 +779,5 @@ int fm_eth_initialize(struct ccsr_fman *reg, struct fm_eth_info *info)
dev->enetaddr[i] = 0;
eth_register(dev);
- return 1;
+ return 0;
}
diff --git a/drivers/net/fm/fm.c b/drivers/net/fm/fm.c
index 400e9dd5e24902bc8ce8bdf2cdecbd9fc8dcc855..df5db723ba23ad47a5820858e7367fff91979c07 100644
--- a/drivers/net/fm/fm.c
+++ b/drivers/net/fm/fm.c
@@ -22,21 +22,22 @@
struct fm_muram muram[CONFIG_SYS_NUM_FMAN];
-u32 fm_muram_base(int fm_idx)
+void *fm_muram_base(int fm_idx)
{
return muram[fm_idx].base;
}
-u32 fm_muram_alloc(int fm_idx, u32 size, u32 align)
+void *fm_muram_alloc(int fm_idx, size_t size, ulong align)
{
- u32 ret;
- u32 align_mask, off;
- u32 save;
+ void *ret;
+ ulong align_mask;
+ size_t off;
+ void *save;
align_mask = align - 1;
save = muram[fm_idx].alloc;
- off = save & align_mask;
+ off = (ulong)save & align_mask;
if (off != 0)
muram[fm_idx].alloc += (align - off);
off = size & align_mask;
@@ -45,6 +46,7 @@ u32 fm_muram_alloc(int fm_idx, u32 size, u32 align)
if ((muram[fm_idx].alloc + size) >= muram[fm_idx].top) {
muram[fm_idx].alloc = save;
printf("%s: run out of ram.\n", __func__);
+ return NULL;
}
ret = muram[fm_idx].alloc;
@@ -56,7 +58,7 @@ u32 fm_muram_alloc(int fm_idx, u32 size, u32 align)
static void fm_init_muram(int fm_idx, void *reg)
{
- u32 base = (u32)reg;
+ void *base = reg;
muram[fm_idx].base = base;
muram[fm_idx].size = CONFIG_SYS_FM_MURAM_SIZE;
@@ -80,11 +82,11 @@ static void fm_upload_ucode(int fm_idx, struct fm_imem *imem,
out_be32(&imem->iadd, IRAM_IADD_AIE);
/* write microcode to IRAM */
for (i = 0; i < size / 4; i++)
- out_be32(&imem->idata, ucode[i]);
+ out_be32(&imem->idata, (be32_to_cpu(ucode[i])));
/* verify if the writing is over */
out_be32(&imem->iadd, 0);
- while ((in_be32(&imem->idata) != ucode[0]) && --timeout)
+ while ((in_be32(&imem->idata) != be32_to_cpu(ucode[0])) && --timeout)
;
if (!timeout)
printf("Fman%u: microcode upload timeout\n", fm_idx + 1);
@@ -177,14 +179,15 @@ static int fman_upload_firmware(int fm_idx,
const struct qe_microcode *ucode = &firmware->microcode[i];
/* Upload a microcode if it's present */
- if (ucode->code_offset) {
+ if (be32_to_cpu(ucode->code_offset)) {
u32 ucode_size;
u32 *code;
printf("Fman%u: Uploading microcode version %u.%u.%u\n",
fm_idx + 1, ucode->major, ucode->minor,
ucode->revision);
- code = (void *)firmware + ucode->code_offset;
- ucode_size = sizeof(u32) * ucode->count;
+ code = (void *)firmware +
+ be32_to_cpu(ucode->code_offset);
+ ucode_size = sizeof(u32) * be32_to_cpu(ucode->count);
fm_upload_ucode(fm_idx, fm_imem, code, ucode_size);
}
}
@@ -255,7 +258,9 @@ static void fm_init_fpm(struct fm_fpm *fpm)
static int fm_init_bmi(int fm_idx, struct fm_bmi_common *bmi)
{
int blk, i, port_id;
- u32 val, offset, base;
+ u32 val;
+ size_t offset;
+ void *base;
/* alloc free buffer pool in MURAM */
base = fm_muram_alloc(fm_idx, FM_FREE_POOL_SIZE, FM_FREE_POOL_ALIGN);
diff --git a/drivers/net/fm/fm.h b/drivers/net/fm/fm.h
index a9691c635aefe00b4b91fbeb961ce18dc6315da6..fa9bc9f42dbcfbb424a8a7be7dc371fbd5527073 100644
--- a/drivers/net/fm/fm.h
+++ b/drivers/net/fm/fm.h
@@ -10,7 +10,7 @@
#include <common.h>
#include <phy.h>
#include <fm_eth.h>
-#include <asm/fsl_fman.h>
+#include <fsl_fman.h>
/* Port ID */
#define OH_PORT_ID_BASE 0x01
@@ -26,10 +26,10 @@
#define MIIM_TIMEOUT 0xFFFF
struct fm_muram {
- u32 base;
- u32 top;
- u32 size;
- u32 alloc;
+ void *base;
+ void *top;
+ size_t size;
+ void *alloc;
};
#define FM_MURAM_RES_SIZE 0x01000
@@ -95,8 +95,8 @@ struct fm_port_global_pram {
#endif
#define FM_FREE_POOL_ALIGN 256
-u32 fm_muram_alloc(int fm_idx, u32 size, u32 align);
-u32 fm_muram_base(int fm_idx);
+void *fm_muram_alloc(int fm_idx, size_t size, ulong align);
+void *fm_muram_base(int fm_idx);
int fm_init_common(int index, struct ccsr_fman *reg);
int fm_eth_initialize(struct ccsr_fman *reg, struct fm_eth_info *info);
phy_interface_t fman_port_enet_if(enum fm_port port);
diff --git a/drivers/net/fm/init.c b/drivers/net/fm/init.c
index b3ff4c50dbe7c17098ba7d65c76d6389eccc7082..3a1de59fd8f5fc21ff30d921bd93c03fa944ae3f 100644
--- a/drivers/net/fm/init.c
+++ b/drivers/net/fm/init.c
@@ -1,13 +1,17 @@
/*
- * Copyright 2011 Freescale Semiconductor, Inc.
+ * Copyright 2011-2015 Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <errno.h>
#include <common.h>
#include <asm/io.h>
-#include <asm/fsl_serdes.h>
#include <fsl_mdio.h>
+#ifdef CONFIG_FSL_LAYERSCAPE
+#include <asm/arch/fsl_serdes.h>
+#else
+#include <asm/fsl_serdes.h>
+#endif
#include "fm.h"
@@ -153,7 +157,9 @@ void fm_disable_port(enum fm_port port)
return;
fm_info[i].enabled = 0;
+#ifndef CONFIG_SYS_FMAN_V3
fman_disable_port(port);
+#endif
}
void fm_enable_port(enum fm_port port)
diff --git a/drivers/net/fm/ls1043.c b/drivers/net/fm/ls1043.c
new file mode 100644
index 0000000000000000000000000000000000000000..cf2cc95a3a4c80196043ca3571f8a9897ca1e2cb
--- /dev/null
+++ b/drivers/net/fm/ls1043.c
@@ -0,0 +1,119 @@
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#include <common.h>
+#include <phy.h>
+#include <fm_eth.h>
+#include <asm/io.h>
+#include <asm/arch/fsl_serdes.h>
+
+#define FSL_CHASSIS2_RCWSR13_EC1 0xe0000000 /* bits 416..418 */
+#define FSL_CHASSIS2_RCWSR13_EC1_DTSEC3_RGMII 0x00000000
+#define FSL_CHASSIS2_RCWSR13_EC1_GPIO 0x20000000
+#define FSL_CHASSIS2_RCWSR13_EC1_FTM 0xa0000000
+#define FSL_CHASSIS2_RCWSR13_EC2 0x1c000000 /* bits 419..421 */
+#define FSL_CHASSIS2_RCWSR13_EC2_DTSEC4_RGMII 0x00000000
+#define FSL_CHASSIS2_RCWSR13_EC2_GPIO 0x04000000
+#define FSL_CHASSIS2_RCWSR13_EC2_1588 0x08000000
+#define FSL_CHASSIS2_RCWSR13_EC2_FTM 0x14000000
+
+u32 port_to_devdisr[] = {
+ [FM1_DTSEC1] = FSL_CHASSIS2_DEVDISR2_DTSEC1_1,
+ [FM1_DTSEC2] = FSL_CHASSIS2_DEVDISR2_DTSEC1_2,
+ [FM1_DTSEC3] = FSL_CHASSIS2_DEVDISR2_DTSEC1_3,
+ [FM1_DTSEC4] = FSL_CHASSIS2_DEVDISR2_DTSEC1_4,
+ [FM1_DTSEC5] = FSL_CHASSIS2_DEVDISR2_DTSEC1_5,
+ [FM1_DTSEC6] = FSL_CHASSIS2_DEVDISR2_DTSEC1_6,
+ [FM1_DTSEC9] = FSL_CHASSIS2_DEVDISR2_DTSEC1_9,
+ [FM1_DTSEC10] = FSL_CHASSIS2_DEVDISR2_DTSEC1_10,
+ [FM1_10GEC1] = FSL_CHASSIS2_DEVDISR2_10GEC1_1,
+ [FM1_10GEC2] = FSL_CHASSIS2_DEVDISR2_10GEC1_2,
+ [FM1_10GEC3] = FSL_CHASSIS2_DEVDISR2_10GEC1_3,
+ [FM1_10GEC4] = FSL_CHASSIS2_DEVDISR2_10GEC1_4,
+};
+
+static int is_device_disabled(enum fm_port port)
+{
+ struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ u32 devdisr2 = in_be32(&gur->devdisr2);
+
+ return port_to_devdisr[port] & devdisr2;
+}
+
+void fman_disable_port(enum fm_port port)
+{
+ struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+
+ setbits_be32(&gur->devdisr2, port_to_devdisr[port]);
+}
+
+phy_interface_t fman_port_enet_if(enum fm_port port)
+{
+ struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ u32 rcwsr13 = in_be32(&gur->rcwsr[13]);
+
+ if (is_device_disabled(port)) {
+ printf("%s:%d: port(%d) is disabled\n", __func__,
+ __LINE__, port);
+ return PHY_INTERFACE_MODE_NONE;
+ }
+
+ if ((port == FM1_10GEC1) && (is_serdes_configured(XFI_FM1_MAC9)))
+ return PHY_INTERFACE_MODE_XGMII;
+
+ if ((port == FM1_DTSEC9) && (is_serdes_configured(XFI_FM1_MAC9)))
+ return PHY_INTERFACE_MODE_NONE;
+
+ if (port == FM1_DTSEC3)
+ if ((rcwsr13 & FSL_CHASSIS2_RCWSR13_EC1) ==
+ FSL_CHASSIS2_RCWSR13_EC1_DTSEC3_RGMII) {
+ printf("%s:%d: port(FM1_DTSEC3) is OK\n",
+ __func__, __LINE__);
+ return PHY_INTERFACE_MODE_RGMII;
+ }
+ if (port == FM1_DTSEC4)
+ if ((rcwsr13 & FSL_CHASSIS2_RCWSR13_EC2) ==
+ FSL_CHASSIS2_RCWSR13_EC2_DTSEC4_RGMII) {
+ printf("%s:%d: port(FM1_DTSEC4) is OK\n",
+ __func__, __LINE__);
+ return PHY_INTERFACE_MODE_RGMII;
+ }
+
+ /* handle SGMII */
+ switch (port) {
+ case FM1_DTSEC1:
+ case FM1_DTSEC2:
+ if ((port == FM1_DTSEC2) &&
+ is_serdes_configured(SGMII_2500_FM1_DTSEC2))
+ return PHY_INTERFACE_MODE_SGMII_2500;
+ case FM1_DTSEC5:
+ case FM1_DTSEC6:
+ case FM1_DTSEC9:
+ if (is_serdes_configured(SGMII_FM1_DTSEC1 + port - FM1_DTSEC1))
+ return PHY_INTERFACE_MODE_SGMII;
+ else if ((port == FM1_DTSEC9) &&
+ is_serdes_configured(SGMII_2500_FM1_DTSEC9))
+ return PHY_INTERFACE_MODE_SGMII_2500;
+ break;
+ default:
+ break;
+ }
+
+ /* handle QSGMII */
+ switch (port) {
+ case FM1_DTSEC1:
+ case FM1_DTSEC2:
+ case FM1_DTSEC5:
+ case FM1_DTSEC6:
+ /* only MAC 1,2,5,6 available for QSGMII */
+ if (is_serdes_configured(QSGMII_FM1_A))
+ return PHY_INTERFACE_MODE_QSGMII;
+ break;
+ default:
+ break;
+ }
+
+ return PHY_INTERFACE_MODE_NONE;
+}
diff --git a/drivers/net/fm/tgec.c b/drivers/net/fm/tgec.c
index 50171230ea8fc99d196888310d3771e9efd06815..8d4622ff38ba43d975025b68b95ab87fa2be1555 100644
--- a/drivers/net/fm/tgec.c
+++ b/drivers/net/fm/tgec.c
@@ -12,7 +12,7 @@
#include <phy.h>
#include <asm/types.h>
#include <asm/io.h>
-#include <asm/fsl_tgec.h>
+#include <fsl_tgec.h>
#include "fm.h"
diff --git a/drivers/net/fm/tgec_phy.c b/drivers/net/fm/tgec_phy.c
index 095f00cf976858bb79012c87491ee97846c37173..24cb17b6edde1790fe0954e873e70cc8b2413d8e 100644
--- a/drivers/net/fm/tgec_phy.c
+++ b/drivers/net/fm/tgec_phy.c
@@ -9,7 +9,7 @@
#include <miiphy.h>
#include <phy.h>
#include <asm/io.h>
-#include <asm/fsl_tgec.h>
+#include <fsl_tgec.h>
#include <fm_eth.h>
/*
diff --git a/drivers/net/ldpaa_eth/ldpaa_eth.c b/drivers/net/ldpaa_eth/ldpaa_eth.c
index 4de7586408e48171ab030e5bad711c3d15c93a90..99acb7a0c972420d8b50928d6a565a6c79a6bf12 100644
--- a/drivers/net/ldpaa_eth/ldpaa_eth.c
+++ b/drivers/net/ldpaa_eth/ldpaa_eth.c
@@ -220,7 +220,6 @@ static int ldpaa_eth_open(struct eth_device *net_dev, bd_t *bd)
{
struct ldpaa_eth_priv *priv = (struct ldpaa_eth_priv *)net_dev->priv;
struct dpni_queue_attr rx_queue_attr;
- uint8_t mac_addr[6];
int err;
if (net_dev->state == ETH_STATE_ACTIVE)
@@ -240,21 +239,13 @@ static int ldpaa_eth_open(struct eth_device *net_dev, bd_t *bd)
if (err)
goto err_bind;
- err = dpni_get_primary_mac_addr(dflt_mc_io, MC_CMD_NO_FLAGS,
- priv->dpni_handle, mac_addr);
+ err = dpni_add_mac_addr(dflt_mc_io, MC_CMD_NO_FLAGS,
+ priv->dpni_handle, net_dev->enetaddr);
if (err) {
- printf("dpni_get_primary_mac_addr() failed\n");
+ printf("dpni_add_mac_addr() failed\n");
return err;
}
- memcpy(net_dev->enetaddr, mac_addr, 0x6);
-
- /* setup the MAC address */
- if (net_dev->enetaddr[0] & 0x01) {
- printf("%s: MacAddress is multcast address\n", __func__);
- return 1;
- }
-
#ifdef CONFIG_PHYLIB
/* TODO Check this path */
err = phy_startup(priv->phydev);
diff --git a/drivers/net/ldpaa_eth/ls2085a.c b/drivers/net/ldpaa_eth/ls2085a.c
index 6b7960a00002c467832f57a6f097060d931d27c6..93ed4f18fe989cad37e8a85b24245faa4352b2ee 100644
--- a/drivers/net/ldpaa_eth/ls2085a.c
+++ b/drivers/net/ldpaa_eth/ls2085a.c
@@ -7,9 +7,7 @@
#include <phy.h>
#include <fsl-mc/ldpaa_wriop.h>
#include <asm/io.h>
-#include <asm/arch-fsl-lsch3/immap_lsch3.h>
#include <asm/arch/fsl_serdes.h>
-#include <fsl-mc/ldpaa_wriop.h>
u32 dpmac_to_devdisr[] = {
[WRIOP1_DPMAC1] = FSL_CHASSIS3_DEVDISR2_DPMAC1,
diff --git a/drivers/pci/pcie_layerscape.c b/drivers/pci/pcie_layerscape.c
index 2f24a6a39bf6d2b767898b6428cb4838ca70ac03..4cee038ede5d13c318871e50dfc4293f6c5d8e3d 100644
--- a/drivers/pci/pcie_layerscape.c
+++ b/drivers/pci/pcie_layerscape.c
@@ -11,7 +11,9 @@
#include <asm/io.h>
#include <errno.h>
#include <malloc.h>
-#include <asm/arch-fsl-lsch3/fdt.h>
+#ifdef CONFIG_FSL_LAYERSCAPE
+#include <asm/arch/fdt.h>
+#endif
#ifndef CONFIG_SYS_PCI_MEMORY_BUS
#define CONFIG_SYS_PCI_MEMORY_BUS CONFIG_SYS_SDRAM_BASE
diff --git a/include/common.h b/include/common.h
index ecb1f0682ed0ebd7242d969496455e3c8f8ef57a..09a131da0b967b5d56dae953f0e1a543b39cea82 100644
--- a/include/common.h
+++ b/include/common.h
@@ -76,6 +76,12 @@ typedef volatile unsigned char vu_char;
#ifdef CONFIG_SOC_DA8XX
#include <asm/arch/hardware.h>
#endif
+#ifdef CONFIG_FSL_LSCH3
+#include <asm/arch/immap_lsch3.h>
+#endif
+#ifdef CONFIG_FSL_LSCH2
+#include <asm/arch/immap_lsch2.h>
+#endif
#include <part.h>
#include <flash.h>
diff --git a/include/configs/BSC9132QDS.h b/include/configs/BSC9132QDS.h
index a006dcebaaa83985079d04ab1ad87b64cf9312b4..54dcf3b9548de2086ef5aa597218ce313b0e587c 100644
--- a/include/configs/BSC9132QDS.h
+++ b/include/configs/BSC9132QDS.h
@@ -17,7 +17,6 @@
#define CONFIG_BSC9132
#endif
-#define CONFIG_FSL_CLK
#define CONFIG_MISC_INIT_R
#ifdef CONFIG_SDCARD
diff --git a/include/configs/MPC8308RDB.h b/include/configs/MPC8308RDB.h
index cfa59313111a98368f18cedd8120810c734725e8..551b72d15309cff788da6bfeb19d3776209f9ce5 100644
--- a/include/configs/MPC8308RDB.h
+++ b/include/configs/MPC8308RDB.h
@@ -10,7 +10,6 @@
#define __CONFIG_H
#define CONFIG_DISPLAY_BOARDINFO
-#define CONFIG_FSL_CLK
/*
* High Level Configuration Options
diff --git a/include/configs/MPC837XEMDS.h b/include/configs/MPC837XEMDS.h
index 990fc04e870a613ecc57746e7e4f084f4111edb4..7d1262d510c1f8672c6ab527674df002a21f1006 100644
--- a/include/configs/MPC837XEMDS.h
+++ b/include/configs/MPC837XEMDS.h
@@ -9,7 +9,6 @@
#define __CONFIG_H
#define CONFIG_DISPLAY_BOARDINFO
-#define CONFIG_FSL_CLK
/*
* High Level Configuration Options
diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h
index fcc531b600108cc05477110fa42c5f74a8582224..ab68e63881badbcb1f48ba9de7233f84cb9ec4be 100644
--- a/include/configs/MPC837XERDB.h
+++ b/include/configs/MPC837XERDB.h
@@ -16,7 +16,6 @@
#define CONFIG_MPC837x 1 /* MPC837x CPU specific */
#define CONFIG_MPC837XERDB 1
#define CONFIG_DISPLAY_BOARDINFO
-#define CONFIG_FSL_CLK
#define CONFIG_SYS_TEXT_BASE 0xFE000000
diff --git a/include/configs/MPC8536DS.h b/include/configs/MPC8536DS.h
index af8eb8c0d2e1436e57e25c96db90088c04a017cc..29c27fa9a75f2a8ca214fa4282b570a7e18c4226 100644
--- a/include/configs/MPC8536DS.h
+++ b/include/configs/MPC8536DS.h
@@ -12,7 +12,6 @@
#define __CONFIG_H
#define CONFIG_DISPLAY_BOARDINFO
-#define CONFIG_FSL_CLK
#include "../board/freescale/common/ics307_clk.h"
#ifdef CONFIG_36BIT
diff --git a/include/configs/MPC8569MDS.h b/include/configs/MPC8569MDS.h
index 9f784e0adb93054ba8cb7f977fdaf3c6bbd8bdf0..6f614b0cbe3d66975bcdedc762c1b2d6d179d8b0 100644
--- a/include/configs/MPC8569MDS.h
+++ b/include/configs/MPC8569MDS.h
@@ -12,7 +12,6 @@
#define CONFIG_DISPLAY_BOARDINFO
-#define CONFIG_FSL_CLK
/* High Level Configuration Options */
#define CONFIG_BOOKE 1 /* BOOKE */
#define CONFIG_E500 1 /* BOOKE e500 family */
diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h
index 9e407303954451f17d8b6de6a3d1122c37efa033..81b085572dc9639a2f7abf98e22c0ea03b70feb2 100644
--- a/include/configs/P1010RDB.h
+++ b/include/configs/P1010RDB.h
@@ -15,7 +15,6 @@
#define CONFIG_PHYS_64BIT
#endif
#define CONFIG_DISPLAY_BOARDINFO
-#define CONFIG_FSL_CLK
#define CONFIG_P1010
#define CONFIG_E500 /* BOOKE e500 family */
diff --git a/include/configs/P1022DS.h b/include/configs/P1022DS.h
index c571fac666e29a51d2ae1448270aef6da8eec821..a9d825baf5dd76845d761b5643400c5c36420e41 100644
--- a/include/configs/P1022DS.h
+++ b/include/configs/P1022DS.h
@@ -12,7 +12,6 @@
#include "../board/freescale/common/ics307_clk.h"
#define CONFIG_DISPLAY_BOARDINFO
-#define CONFIG_FSL_CLK
#ifdef CONFIG_36BIT
#define CONFIG_PHYS_64BIT
diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h
index 0cd990477b15631aaa97c56a75ecf880de8db242..2c4c8b5a026991125077c1787c5c0bf68d2cb17a 100644
--- a/include/configs/P2041RDB.h
+++ b/include/configs/P2041RDB.h
@@ -15,7 +15,6 @@
#define CONFIG_PHYS_64BIT
#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_PPC_P2041
-#define CONFIG_FSL_CLK
#ifdef CONFIG_RAMBOOT_PBL
#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
diff --git a/include/configs/T102xQDS.h b/include/configs/T102xQDS.h
index 4f22657703ddd66af42abb961b6c22c478042d35..52942edbd416986c3a37072a7a283668af5b546f 100644
--- a/include/configs/T102xQDS.h
+++ b/include/configs/T102xQDS.h
@@ -20,7 +20,6 @@
#define CONFIG_MP /* support multiple processors */
#define CONFIG_PHYS_64BIT
#define CONFIG_ENABLE_36BIT_PHYS
-#define CONFIG_FSL_CLK
#ifdef CONFIG_PHYS_64BIT
#define CONFIG_ADDR_MAP 1
diff --git a/include/configs/T102xRDB.h b/include/configs/T102xRDB.h
index d412d0b2b7e799747047b699bdfc3c60f29a22ce..39fa5e2b1898493730c6398d3cbc7592efc2e27a 100644
--- a/include/configs/T102xRDB.h
+++ b/include/configs/T102xRDB.h
@@ -20,7 +20,6 @@
#define CONFIG_MP /* support multiple processors */
#define CONFIG_PHYS_64BIT
#define CONFIG_ENABLE_36BIT_PHYS
-#define CONFIG_FSL_CLK
#ifdef CONFIG_PHYS_64BIT
#define CONFIG_ADDR_MAP 1
diff --git a/include/configs/T1040QDS.h b/include/configs/T1040QDS.h
index 18df2372a485a9e16ff87038d3a3e4c8c8e0555c..d8b86e6c5e6c9954a101b1fc148a658ce846e63c 100644
--- a/include/configs/T1040QDS.h
+++ b/include/configs/T1040QDS.h
@@ -29,7 +29,6 @@
#define CONFIG_T1040QDS
#define CONFIG_PHYS_64BIT
#define CONFIG_DISPLAY_BOARDINFO
-#define CONFIG_FSL_CLK
#ifdef CONFIG_RAMBOOT_PBL
#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h
index 20910156386040a5667a387688af804792916bd7..da2ccb831838deac3962a6915d47d379793a02c2 100644
--- a/include/configs/T104xRDB.h
+++ b/include/configs/T104xRDB.h
@@ -13,7 +13,6 @@
#define CONFIG_T104xRDB
#define CONFIG_PHYS_64BIT
#define CONFIG_DISPLAY_BOARDINFO
-#define CONFIG_FSL_CLK
#define CONFIG_E500 /* BOOKE e500 family */
#include <asm/config_mpc85xx.h>
diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h
index d35b9d2d90169b175dbec5100cefff50d7f109de..a81f1e66f3fc95ff2bf1b53fcf413126824b9688 100644
--- a/include/configs/T208xQDS.h
+++ b/include/configs/T208xQDS.h
@@ -13,7 +13,6 @@
#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */
-#define CONFIG_FSL_CLK
#define CONFIG_MMC
#define CONFIG_USB_EHCI
#if defined(CONFIG_PPC_T2080)
diff --git a/include/configs/T208xRDB.h b/include/configs/T208xRDB.h
index c632b8e328fd0c312fdd023a3dc3f98778573c63..8b762346ac2679ae7001f593f3830ffb26bbffa0 100644
--- a/include/configs/T208xRDB.h
+++ b/include/configs/T208xRDB.h
@@ -14,7 +14,6 @@
#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_T2080RDB
#define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */
-#define CONFIG_FSL_CLK
#define CONFIG_MMC
#define CONFIG_USB_EHCI
#define CONFIG_FSL_SATA_V2
diff --git a/include/configs/T4240QDS.h b/include/configs/T4240QDS.h
index dd8dd73f9867fc5c8eb680933a37dbabae9bc39b..4edb3cb91f35ddfaa08d5912259e4e402104693c 100644
--- a/include/configs/T4240QDS.h
+++ b/include/configs/T4240QDS.h
@@ -12,7 +12,6 @@
#define CONFIG_T4240QDS
#define CONFIG_PHYS_64BIT
-#define CONFIG_FSL_CLK
#define CONFIG_FSL_SATA_V2
#define CONFIG_PCIE4
diff --git a/include/configs/T4240RDB.h b/include/configs/T4240RDB.h
index 2c5f800cbd2d3a9579d46cbdf1b572ed2c792039..2e875d2fc1284d116756adf9632c8c1f826da742 100644
--- a/include/configs/T4240RDB.h
+++ b/include/configs/T4240RDB.h
@@ -13,7 +13,6 @@
#define CONFIG_T4240RDB
#define CONFIG_PHYS_64BIT
#define CONFIG_DISPLAY_BOARDINFO
-#define CONFIG_FSL_CLK
#define CONFIG_FSL_SATA_V2
#define CONFIG_PCIE4
diff --git a/include/configs/UCP1020.h b/include/configs/UCP1020.h
index 0b609af2c90768ea6a6293c9ccf0d2308ab63639..861147377309b3215a9c67e2ac6657ed377db1bf 100644
--- a/include/configs/UCP1020.h
+++ b/include/configs/UCP1020.h
@@ -15,7 +15,6 @@
#define __CONFIG_H
#define CONFIG_DISPLAY_BOARDINFO
-#define CONFIG_FSL_CLK
#define CONFIG_FSL_ELBC
#define CONFIG_PCI
diff --git a/include/configs/colibri_vf.h b/include/configs/colibri_vf.h
index 9fa8f817f29b294edaa8eceb91e990fdef136401..7658e6136787c57dd73fe5a43f47037103ca2e36 100644
--- a/include/configs/colibri_vf.h
+++ b/include/configs/colibri_vf.h
@@ -18,7 +18,7 @@
#define CONFIG_SYS_THUMB_BUILD
#define CONFIG_USE_ARCH_MEMCPY
#define CONFIG_USE_ARCH_MEMSET
-#define CONFIG_FSL_CLK
+#define CONFIG_SYS_FSL_CLK
#define CONFIG_ARCH_MISC_INIT
#define CONFIG_DISPLAY_CPUINFO
diff --git a/include/configs/controlcenterd.h b/include/configs/controlcenterd.h
index 77c2edcbb3c6d8862869a0477aabb130bb3ca0c6..600bb835cefca51fcaa26b2bfba3c1f2fbef58a3 100644
--- a/include/configs/controlcenterd.h
+++ b/include/configs/controlcenterd.h
@@ -44,7 +44,6 @@
#define CONFIG_P1022
#define CONFIG_CONTROLCENTERD
#define CONFIG_MP /* support multiple processors */
-#define CONFIG_FSL_CLK
#define CONFIG_SYS_NO_FLASH
diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h
index 3c9a5291622c82296cf354bdabb12ee4bf7752e7..921021634df7347892a67cf8dfb53c4f353e3940 100644
--- a/include/configs/corenet_ds.h
+++ b/include/configs/corenet_ds.h
@@ -11,7 +11,6 @@
#define __CONFIG_H
#define CONFIG_DISPLAY_BOARDINFO
-#define CONFIG_FSL_CLK
#include "../board/freescale/common/ics307_clk.h"
diff --git a/include/configs/hrcon.h b/include/configs/hrcon.h
index e2b9deba9e1e4f9564dc39a3eac8ade4b9cd2124..3cb279a9127f48b26a778ed89b9efcc8e456044f 100644
--- a/include/configs/hrcon.h
+++ b/include/configs/hrcon.h
@@ -23,7 +23,6 @@
#define CONFIG_IDENT_STRING " hrcon 0.01"
-#define CONFIG_FSL_CLK
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_BOARD_EARLY_INIT_R
#define CONFIG_LAST_STAGE_INIT
diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h
index b8477e89d27cc8d2837c38711c6161c3a52e9183..562e78f0a575a32f93f02f46c2f156e29bd20d57 100644
--- a/include/configs/ls1021aqds.h
+++ b/include/configs/ls1021aqds.h
@@ -11,7 +11,7 @@
#define CONFIG_ARMV7_PSCI
-#define CONFIG_FSL_CLK
+#define CONFIG_SYS_FSL_CLK
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO
@@ -69,7 +69,7 @@ unsigned long get_board_ddr_clk(void);
#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
#define CONFIG_SPL_MMC_SUPPORT
#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0xe8
-#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x400
+#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x600
#define CONFIG_SPL_TEXT_BASE 0x10000000
#define CONFIG_SPL_MAX_SIZE 0x1a000
@@ -82,7 +82,7 @@ unsigned long get_board_ddr_clk(void);
#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
#define CONFIG_SPL_BSS_START_ADDR 0x80100000
#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
-#define CONFIG_SYS_MONITOR_LEN 0x80000
+#define CONFIG_SYS_MONITOR_LEN 0xc0000
#endif
#ifdef CONFIG_QSPI_BOOT
@@ -563,7 +563,7 @@ unsigned long get_board_ddr_clk(void);
#define CONFIG_ARMV7_NONSEC
#define CONFIG_ARMV7_VIRT
#define CONFIG_PEN_ADDR_BIG_ENDIAN
-#define CONFIG_LS102XA_NS_ACCESS
+#define CONFIG_LAYERSCAPE_NS_ACCESS
#define CONFIG_SMP_PEN_ADDR 0x01ee0200
#define CONFIG_TIMER_CLK_FREQ 12500000
@@ -574,7 +574,7 @@ unsigned long get_board_ddr_clk(void);
#define CONFIG_BOOTDELAY 3
-#define CONFIG_SYS_QE_FW_ADDR 0x67f40000
+#define CONFIG_SYS_QE_FW_ADDR 0x600c0000
#ifdef CONFIG_LPUART
#define CONFIG_EXTRA_ENV_SETTINGS \
@@ -658,6 +658,7 @@ unsigned long get_board_ddr_clk(void);
#define CONFIG_OF_LIBFDT
#define CONFIG_OF_BOARD_SETUP
+#define CONFIG_OF_STDOUT_VIA_ALIAS
#define CONFIG_CMD_BOOTZ
#define CONFIG_MISC_INIT_R
diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h
index 784331ff8e3ecbb73cbe43e2a6a5fc9c3e95e471..fdbbfc119617e8951d51f3ba5ec94b15c178e230 100644
--- a/include/configs/ls1021atwr.h
+++ b/include/configs/ls1021atwr.h
@@ -11,7 +11,7 @@
#define CONFIG_ARMV7_PSCI
-#define CONFIG_FSL_CLK
+#define CONFIG_SYS_FSL_CLK
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO
@@ -109,7 +109,13 @@
#endif
#ifdef CONFIG_SD_BOOT
-#define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1021atwr/ls102xa_rcw_sd.cfg
+#ifdef CONFIG_SD_BOOT_QSPI
+#define CONFIG_SYS_FSL_PBL_RCW \
+ board/freescale/ls1021atwr/ls102xa_rcw_sd_qspi.cfg
+#else
+#define CONFIG_SYS_FSL_PBL_RCW \
+ board/freescale/ls1021atwr/ls102xa_rcw_sd_ifc.cfg
+#endif
#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_LDSCRIPT "arch/$(ARCH)/cpu/u-boot-spl.lds"
#define CONFIG_SPL_LIBCOMMON_SUPPORT
@@ -139,6 +145,9 @@
#ifdef CONFIG_QSPI_BOOT
#define CONFIG_SYS_TEXT_BASE 0x40010000
+#endif
+
+#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
#define CONFIG_SYS_NO_FLASH
#endif
@@ -165,7 +174,7 @@
/*
* IFC Definitions
*/
-#ifndef CONFIG_QSPI_BOOT
+#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
#define CONFIG_FSL_IFC
#define CONFIG_SYS_FLASH_BASE 0x60000000
#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
@@ -280,7 +289,6 @@
#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
/* EEPROM */
-#ifndef CONFIG_SD_BOOT
#define CONFIG_ID_EEPROM
#define CONFIG_SYS_I2C_EEPROM_NXID
#define CONFIG_SYS_EEPROM_BUS_NUM 1
@@ -288,7 +296,6 @@
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
-#endif
/*
* MMC
@@ -302,7 +309,7 @@
#define CONFIG_DOS_PARTITION
/* SPI */
-#ifdef CONFIG_QSPI_BOOT
+#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
/* QSPI */
#define CONFIG_FSL_QSPI
#define QSPI0_AMBA_BASE 0x40000000
@@ -412,10 +419,14 @@
#define CONFIG_CMDLINE_TAG
#define CONFIG_CMDLINE_EDITING
+#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
+#undef CONFIG_CMD_IMLS
+#endif
+
#define CONFIG_ARMV7_NONSEC
#define CONFIG_ARMV7_VIRT
#define CONFIG_PEN_ADDR_BIG_ENDIAN
-#define CONFIG_LS102XA_NS_ACCESS
+#define CONFIG_LAYERSCAPE_NS_ACCESS
#define CONFIG_SMP_PEN_ADDR 0x01ee0200
#define CONFIG_TIMER_CLK_FREQ 12500000
@@ -429,13 +440,13 @@
#ifdef CONFIG_LPUART
#define CONFIG_EXTRA_ENV_SETTINGS \
"bootargs=root=/dev/ram0 rw console=ttyLP0,115200\0" \
- "initrd_high=0xcfffffff\0" \
- "fdt_high=0xcfffffff\0"
+ "initrd_high=0xffffffff\0" \
+ "fdt_high=0xffffffff\0"
#else
#define CONFIG_EXTRA_ENV_SETTINGS \
"bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \
- "initrd_high=0xcfffffff\0" \
- "fdt_high=0xcfffffff\0"
+ "initrd_high=0xffffffff\0" \
+ "fdt_high=0xffffffff\0"
#endif
/*
@@ -478,7 +489,7 @@
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
#endif
-#define CONFIG_SYS_QE_FW_ADDR 0x67f40000
+#define CONFIG_SYS_QE_FW_ADDR 0x600c0000
/*
* Environment
@@ -504,6 +515,7 @@
#define CONFIG_OF_LIBFDT
#define CONFIG_OF_BOARD_SETUP
+#define CONFIG_OF_STDOUT_VIA_ALIAS
#define CONFIG_CMD_BOOTZ
#define CONFIG_MISC_INIT_R
diff --git a/include/configs/ls1043a_common.h b/include/configs/ls1043a_common.h
new file mode 100644
index 0000000000000000000000000000000000000000..1f22dd34df4f18d6f7668423b4635868baf05239
--- /dev/null
+++ b/include/configs/ls1043a_common.h
@@ -0,0 +1,255 @@
+/*
+ * Copyright (C) 2015 Freescale Semiconductor
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __LS1043A_COMMON_H
+#define __LS1043A_COMMON_H
+
+#define CONFIG_REMAKE_ELF
+#define CONFIG_FSL_LAYERSCAPE
+#define CONFIG_FSL_LSCH2
+#define CONFIG_LS1043A
+#define CONFIG_MP
+#define CONFIG_SYS_FSL_CLK
+#define CONFIG_GICV2
+
+#include <asm/arch/config.h>
+#ifdef CONFIG_SYS_FSL_SRDS_1
+#define CONFIG_SYS_HAS_SERDES
+#endif
+
+/* Link Definitions */
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0)
+
+#define CONFIG_SUPPORT_RAW_INITRD
+
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_BOARD_EARLY_INIT_F 1
+
+/* Flat Device Tree Definitions */
+#define CONFIG_OF_LIBFDT
+#define CONFIG_OF_BOARD_SETUP
+
+/* new uImage format support */
+#define CONFIG_FIT
+#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
+
+#ifndef CONFIG_SYS_FSL_DDR4
+#define CONFIG_SYS_FSL_DDR3 /* Use DDR3 memory */
+#endif
+
+#define CONFIG_VERY_BIG_RAM
+#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000
+#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
+#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
+
+#define CPU_RELEASE_ADDR secondary_boot_func
+
+/* Generic Timer Definitions */
+#define COUNTER_FREQUENCY 25000000 /* 25MHz */
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 1024 * 1024)
+
+/* Serial Port */
+#define CONFIG_CONS_INDEX 1
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE 1
+#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0))
+
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+
+/* SD boot SPL */
+#ifdef CONFIG_SD_BOOT
+#define CONFIG_SPL_FRAMEWORK
+#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds"
+#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_ENV_SUPPORT
+#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
+#define CONFIG_SPL_WATCHDOG_SUPPORT
+#define CONFIG_SPL_I2C_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
+#define CONFIG_SPL_MMC_SUPPORT
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0xf0
+#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x500
+
+#define CONFIG_SPL_TEXT_BASE 0x10000000
+#define CONFIG_SPL_MAX_SIZE 0x1d000
+#define CONFIG_SPL_STACK 0x1001e000
+#define CONFIG_SPL_PAD_TO 0x1d000
+
+#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE + \
+ CONFIG_SYS_MONITOR_LEN)
+#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
+#define CONFIG_SPL_BSS_START_ADDR 0x80100000
+#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
+#define CONFIG_SYS_MONITOR_LEN 0xa0000
+#endif
+
+/* NAND SPL */
+#ifdef CONFIG_NAND_BOOT
+#define CONFIG_SPL_PBL_PAD
+#define CONFIG_SPL_FRAMEWORK
+#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds"
+#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_ENV_SUPPORT
+#define CONFIG_SPL_WATCHDOG_SUPPORT
+#define CONFIG_SPL_I2C_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
+#define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
+#define CONFIG_SPL_TEXT_BASE 0x10000000
+#define CONFIG_SPL_MAX_SIZE 0x1a000
+#define CONFIG_SPL_STACK 0x1001d000
+#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_SPL_MALLOC_START 0x80200000
+#define CONFIG_SPL_BSS_START_ADDR 0x80100000
+#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
+#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
+#define CONFIG_SYS_MONITOR_LEN 0xa0000
+#endif
+
+/* IFC */
+#define CONFIG_FSL_IFC
+/*
+ * CONFIG_SYS_FLASH_BASE has the final address (core view)
+ * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view)
+ * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address
+ * CONFIG_SYS_TEXT_BASE is linked to 0x60000000 for booting
+ */
+#define CONFIG_SYS_FLASH_BASE 0x60000000
+#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_FLASH_BASE_PHYS_EARLY 0x00000000
+
+#ifndef CONFIG_SYS_NO_FLASH
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+#define CONFIG_SYS_FLASH_QUIET_TEST
+#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
+#endif
+
+/* I2C */
+#define CONFIG_CMD_I2C
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C1
+#define CONFIG_SYS_I2C_MXC_I2C2
+#define CONFIG_SYS_I2C_MXC_I2C3
+#define CONFIG_SYS_I2C_MXC_I2C4
+
+/* PCIe */
+#define CONFIG_PCI /* Enable PCI/PCIE */
+#define CONFIG_PCIE1 /* PCIE controller 1 */
+#define CONFIG_PCIE2 /* PCIE controller 2 */
+#define CONFIG_PCIE3 /* PCIE controller 3 */
+#define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */
+#define FSL_PCIE_COMPAT "fsl,ls1043a-pcie"
+
+#define CONFIG_SYS_PCI_64BIT
+
+#define CONFIG_SYS_PCIE_CFG0_PHYS_OFF 0x00000000
+#define CONFIG_SYS_PCIE_CFG0_SIZE 0x00001000 /* 4k */
+#define CONFIG_SYS_PCIE_CFG1_PHYS_OFF 0x00001000
+#define CONFIG_SYS_PCIE_CFG1_SIZE 0x00001000 /* 4k */
+
+#define CONFIG_SYS_PCIE_IO_BUS 0x00000000
+#define CONFIG_SYS_PCIE_IO_PHYS_OFF 0x00010000
+#define CONFIG_SYS_PCIE_IO_SIZE 0x00010000 /* 64k */
+
+#define CONFIG_SYS_PCIE_MEM_BUS 0x40000000
+#define CONFIG_SYS_PCIE_MEM_PHYS_OFF 0x40000000
+#define CONFIG_SYS_PCIE_MEM_SIZE 0x40000000 /* 1G */
+
+#ifdef CONFIG_PCI
+#define CONFIG_NET_MULTI
+#define CONFIG_PCI_PNP
+#define CONFIG_E1000
+#define CONFIG_PCI_SCAN_SHOW
+#define CONFIG_CMD_PCI
+#endif
+
+/* Command line configuration */
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_ENV
+#define CONFIG_CMD_PING
+
+/* MMC */
+#define CONFIG_MMC
+#ifdef CONFIG_MMC
+#define CONFIG_CMD_MMC
+#define CONFIG_CMD_FAT
+#define CONFIG_FSL_ESDHC
+#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
+#define CONFIG_GENERIC_MMC
+#define CONFIG_DOS_PARTITION
+#endif
+
+/* FMan ucode */
+#define CONFIG_SYS_DPAA_FMAN
+#ifdef CONFIG_SYS_DPAA_FMAN
+#define CONFIG_SYS_FM_MURAM_SIZE 0x60000
+
+#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
+/* FMan fireware Pre-load address */
+#define CONFIG_SYS_FMAN_FW_ADDR 0x60300000
+#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
+#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
+#endif
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000)
+#define CONFIG_ARCH_EARLY_INIT_R
+#define CONFIG_BOARD_LATE_INIT
+
+#define CONFIG_HWCONFIG
+#define HWCONFIG_BUFFER_SIZE 128
+
+/* Initial environment variables */
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "hwconfig=fsl_ddr:bank_intlv=auto\0" \
+ "loadaddr=0x80100000\0" \
+ "kernel_addr=0x100000\0" \
+ "ramdisk_addr=0x800000\0" \
+ "ramdisk_size=0x2000000\0" \
+ "fdt_high=0xffffffffffffffff\0" \
+ "initrd_high=0xffffffffffffffff\0" \
+ "kernel_start=0x61200000\0" \
+ "kernel_load=0x807f0000\0" \
+ "kernel_size=0x1000000\0" \
+ "console=ttyAMA0,38400n8\0"
+
+#define CONFIG_BOOTARGS "console=ttyS0,115200 root=/dev/ram0 " \
+ "earlycon=uart8250,0x21c0500,115200"
+#define CONFIG_BOOTCOMMAND "cp.b $kernel_start $kernel_load " \
+ "$kernel_size && bootm $kernel_load"
+#define CONFIG_BOOTDELAY 10
+
+/* Monitor Command Prompt */
+#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
+#define CONFIG_SYS_PROMPT "=> "
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
+ sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot args buffer */
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_CMDLINE_EDITING 1
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_SYS_MAXARGS 64 /* max command args */
+
+#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
+
+#endif /* __LS1043A_COMMON_H */
diff --git a/include/configs/ls1043ardb.h b/include/configs/ls1043ardb.h
new file mode 100644
index 0000000000000000000000000000000000000000..307d947405ce673a8fe8b29748bfbf1019000066
--- /dev/null
+++ b/include/configs/ls1043ardb.h
@@ -0,0 +1,271 @@
+/*
+ * Copyright 2015 Freescale Semiconductor
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __LS1043ARDB_H__
+#define __LS1043ARDB_H__
+
+#include "ls1043a_common.h"
+
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+
+#if defined(CONFIG_NAND_BOOT) || defined(CONFIG_SD_BOOT)
+#define CONFIG_SYS_TEXT_BASE 0x82000000
+#else
+#define CONFIG_SYS_TEXT_BASE 0x60100000
+#endif
+
+#define CONFIG_SYS_CLK_FREQ 100000000
+#define CONFIG_DDR_CLK_FREQ 100000000
+
+#define CONFIG_LAYERSCAPE_NS_ACCESS
+#define CONFIG_MISC_INIT_R
+
+#define CONFIG_DIMM_SLOTS_PER_CTLR 1
+/* Physical Memory Map */
+#define CONFIG_CHIP_SELECTS_PER_CTRL 4
+#define CONFIG_NR_DRAM_BANKS 1
+
+#define CONFIG_SYS_SPD_BUS_NUM 0
+
+#define CONFIG_FSL_DDR_BIST
+#define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */
+#define CONFIG_SYS_DDR_RAW_TIMING
+#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
+#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
+
+#ifdef CONFIG_RAMBOOT_PBL
+#define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1043ardb/ls1043ardb_pbi.cfg
+#endif
+
+#ifdef CONFIG_NAND_BOOT
+#define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1043ardb/ls1043ardb_rcw_nand.cfg
+#endif
+
+#ifdef CONFIG_SD_BOOT
+#define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1043ardb/ls1043ardb_rcw_sd.cfg
+#endif
+
+/*
+ * NOR Flash Definitions
+ */
+#define CONFIG_SYS_NOR_CSPR_EXT (0x0)
+#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
+#define CONFIG_SYS_NOR_CSPR \
+ (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
+ CSPR_PORT_SIZE_16 | \
+ CSPR_MSEL_NOR | \
+ CSPR_V)
+
+/* NOR Flash Timing Params */
+#define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
+ CSOR_NOR_TRHZ_80)
+#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x1) | \
+ FTIM0_NOR_TEADC(0x1) | \
+ FTIM0_NOR_TAVDS(0x0) | \
+ FTIM0_NOR_TEAHC(0xc))
+#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x1c) | \
+ FTIM1_NOR_TRAD_NOR(0xb) | \
+ FTIM1_NOR_TSEQRAD_NOR(0x9))
+#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x1) | \
+ FTIM2_NOR_TCH(0x4) | \
+ FTIM2_NOR_TWPH(0x8) | \
+ FTIM2_NOR_TWP(0x10))
+#define CONFIG_SYS_NOR_FTIM3 0
+#define CONFIG_SYS_IFC_CCR 0x01000000
+
+#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
+#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
+
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS }
+
+#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
+#define CONFIG_SYS_WRITE_SWAPPED_DATA
+
+/*
+ * NAND Flash Definitions
+ */
+#define CONFIG_NAND_FSL_IFC
+
+#define CONFIG_SYS_NAND_BASE 0x7e800000
+#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
+
+#define CONFIG_SYS_NAND_CSPR_EXT (0x0)
+#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
+ | CSPR_PORT_SIZE_8 \
+ | CSPR_MSEL_NAND \
+ | CSPR_V)
+#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
+#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
+ | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
+ | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
+ | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \
+ | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
+ | CSOR_NAND_SPRZ_64 /* Spare size = 64 */ \
+ | CSOR_NAND_PB(64)) /* 64 Pages Per Block */
+
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+
+#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \
+ FTIM0_NAND_TWP(0x18) | \
+ FTIM0_NAND_TWCHT(0x7) | \
+ FTIM0_NAND_TWH(0xa))
+#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
+ FTIM1_NAND_TWBE(0x39) | \
+ FTIM1_NAND_TRR(0xe) | \
+ FTIM1_NAND_TRP(0x18))
+#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \
+ FTIM2_NAND_TREH(0xa) | \
+ FTIM2_NAND_TWHRE(0x1e))
+#define CONFIG_SYS_NAND_FTIM3 0x0
+
+#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+#define CONFIG_MTD_NAND_VERIFY_WRITE
+#define CONFIG_CMD_NAND
+
+#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
+
+#ifdef CONFIG_NAND_BOOT
+#define CONFIG_SPL_PAD_TO 0x20000 /* block aligned */
+#define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO
+#define CONFIG_SYS_NAND_U_BOOT_SIZE (640 << 10)
+#endif
+
+/*
+ * CPLD
+ */
+#define CONFIG_SYS_CPLD_BASE 0x7fb00000
+#define CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE
+
+#define CONFIG_SYS_CPLD_CSPR_EXT (0x0)
+#define CONFIG_SYS_CPLD_CSPR (CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \
+ CSPR_PORT_SIZE_8 | \
+ CSPR_MSEL_GPCM | \
+ CSPR_V)
+#define CONFIG_SYS_CPLD_AMASK IFC_AMASK(64 * 1024)
+#define CONFIG_SYS_CPLD_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
+ CSOR_NOR_NOR_MODE_AVD_NOR | \
+ CSOR_NOR_TRHZ_80)
+
+/* CPLD Timing parameters for IFC GPCM */
+#define CONFIG_SYS_CPLD_FTIM0 (FTIM0_GPCM_TACSE(0xf) | \
+ FTIM0_GPCM_TEADC(0xf) | \
+ FTIM0_GPCM_TEAHC(0xf))
+#define CONFIG_SYS_CPLD_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
+ FTIM1_GPCM_TRAD(0x3f))
+#define CONFIG_SYS_CPLD_FTIM2 (FTIM2_GPCM_TCS(0xf) | \
+ FTIM2_GPCM_TCH(0xf) | \
+ FTIM2_GPCM_TWP(0xff))
+#define CONFIG_SYS_CPLD_FTIM3 0x0
+
+/* IFC Timing Params */
+#ifdef CONFIG_NAND_BOOT
+#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
+
+#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR_CSPR_EXT
+#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR
+#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
+#else
+#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR_CSPR_EXT
+#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR
+#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
+
+#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
+#endif
+
+#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_CPLD_CSPR_EXT
+#define CONFIG_SYS_CSPR2 CONFIG_SYS_CPLD_CSPR
+#define CONFIG_SYS_AMASK2 CONFIG_SYS_CPLD_AMASK
+#define CONFIG_SYS_CSOR2 CONFIG_SYS_CPLD_CSOR
+#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_CPLD_FTIM0
+#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_CPLD_FTIM1
+#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_CPLD_FTIM2
+#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_CPLD_FTIM3
+
+/* EEPROM */
+#define CONFIG_ID_EEPROM
+#define CONFIG_SYS_I2C_EEPROM_NXID
+#define CONFIG_SYS_EEPROM_BUS_NUM 0
+#define CONFIG_SYS_I2C_EEPROM_ADDR 0x53
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
+
+/*
+ * Environment
+ */
+#define CONFIG_ENV_OVERWRITE
+
+#if defined(CONFIG_NAND_BOOT)
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_SIZE 0x2000
+#define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE)
+#elif defined(CONFIG_SD_BOOT)
+#define CONFIG_ENV_OFFSET (1024 * 1024)
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_SYS_MMC_ENV_DEV 0
+#define CONFIG_ENV_SIZE 0x2000
+#else
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x200000)
+#define CONFIG_ENV_SECT_SIZE 0x20000
+#define CONFIG_ENV_SIZE 0x20000
+#endif
+
+/* FMan */
+#ifdef CONFIG_SYS_DPAA_FMAN
+#define CONFIG_FMAN_ENET
+#define CONFIG_CMD_MII
+#define CONFIG_PHYLIB
+#define CONFIG_PHYLIB_10G
+#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
+
+#define CONFIG_PHY_VITESSE
+#define CONFIG_PHY_REALTEK
+#define CONFIG_PHY_AQUANTIA
+
+#define RGMII_PHY1_ADDR 0x1
+#define RGMII_PHY2_ADDR 0x2
+
+#define QSGMII_PORT1_PHY_ADDR 0x4
+#define QSGMII_PORT2_PHY_ADDR 0x5
+#define QSGMII_PORT3_PHY_ADDR 0x6
+#define QSGMII_PORT4_PHY_ADDR 0x7
+
+#define FM1_10GEC1_PHY_ADDR 0x1
+
+#define CONFIG_ETHPRIME "FM1@DTSEC3"
+#endif
+
+#endif /* __LS1043ARDB_H__ */
diff --git a/include/configs/ls2085a_common.h b/include/configs/ls2085a_common.h
index 9c8a8642e509854cdb97a29f40d41911168f0845..0011e720eaa459d9fb7db93a457203ab80e35be6 100644
--- a/include/configs/ls2085a_common.h
+++ b/include/configs/ls2085a_common.h
@@ -9,8 +9,10 @@
#define CONFIG_REMAKE_ELF
+#define CONFIG_FSL_LAYERSCAPE
#define CONFIG_FSL_LSCH3
#define CONFIG_LS2085A
+#define CONFIG_MP
#define CONFIG_GICV3
#define CONFIG_FSL_TZPC_BP147
@@ -18,12 +20,15 @@
#define CONFIG_ARM_ERRATA_828024
#define CONFIG_ARM_ERRATA_826974
-#include <asm/arch-fsl-lsch3/ls2085a_stream_id.h>
-#include <asm/arch-fsl-lsch3/config.h>
+#include <asm/arch/ls2085a_stream_id.h>
+#include <asm/arch/config.h>
#if (defined(CONFIG_SYS_FSL_SRDS_1) || defined(CONFIG_SYS_FSL_SRDS_2))
#define CONFIG_SYS_HAS_SERDES
#endif
+/* Link Definitions */
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0)
+
/* We need architecture specific misc initializations */
#define CONFIG_ARCH_MISC_INIT
@@ -46,6 +51,7 @@
/* Flat Device Tree Definitions */
#define CONFIG_OF_LIBFDT
#define CONFIG_OF_BOARD_SETUP
+#define CONFIG_OF_STDOUT_VIA_ALIAS
/* new uImage format support */
#define CONFIG_FIT
@@ -61,6 +67,7 @@
#define CONFIG_SYS_FSL_DDR_INTLV_256B /* force 256 byte interleaving */
+#define CONFIG_VERY_BIG_RAM
#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
diff --git a/include/configs/ls2085aqds.h b/include/configs/ls2085aqds.h
index 4cfcf980941de22c28be165665f9bf7e4a652fef..406d0e6d47e5c018872bbdf38a721fbf9843427e 100644
--- a/include/configs/ls2085aqds.h
+++ b/include/configs/ls2085aqds.h
@@ -16,7 +16,7 @@ unsigned long get_board_sys_clk(void);
unsigned long get_board_ddr_clk(void);
#endif
-#define CONFIG_FSL_CLK
+#define CONFIG_SYS_FSL_CLK
#define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
#define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ/4)
diff --git a/include/configs/ls2085ardb.h b/include/configs/ls2085ardb.h
index 583fed574ad8b87de543b179f0f4a422097e7b40..f95d7b27320f329ef908eae30ee9a6b78ce529f2 100644
--- a/include/configs/ls2085ardb.h
+++ b/include/configs/ls2085ardb.h
@@ -18,7 +18,7 @@
unsigned long get_board_sys_clk(void);
#endif
-#define CONFIG_FSL_CLK
+#define CONFIG_SYS_FSL_CLK
#define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
#define CONFIG_DDR_CLK_FREQ 133333333
#define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ/4)
@@ -331,6 +331,7 @@ unsigned long get_board_sys_clk(void);
/* MAC/PHY configuration */
#ifdef CONFIG_FSL_MC_ENET
#define CONFIG_PHYLIB_10G
+#define CONFIG_PHY_AQUANTIA
#define CONFIG_PHY_CORTINA
#define CONFIG_PHYLIB
#define CONFIG_SYS_CORTINA_FW_IN_NOR
diff --git a/include/configs/m53evk.h b/include/configs/m53evk.h
index 152e295778aee1a75a889301d5ed7d65098d4e8f..fbaa6000bc860686789ed17098d3f26bf2e35fc6 100644
--- a/include/configs/m53evk.h
+++ b/include/configs/m53evk.h
@@ -17,7 +17,7 @@
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_REVISION_TAG
#define CONFIG_SYS_NO_FLASH
-#define CONFIG_FSL_CLK
+#define CONFIG_SYS_FSL_CLK
#define CONFIG_FIT
diff --git a/include/configs/mx25pdk.h b/include/configs/mx25pdk.h
index 0ee8e0d97cb95f96a5b6411ba5de641d8a4b4911..f1133026952b7ee685f7c297770e65e9343c5a0c 100644
--- a/include/configs/mx25pdk.h
+++ b/include/configs/mx25pdk.h
@@ -14,7 +14,7 @@
#define CONFIG_MX25
#define CONFIG_SYS_TEXT_BASE 0x81200000
#define CONFIG_MXC_GPIO
-#define CONFIG_FSL_CLK
+#define CONFIG_SYS_FSL_CLK
#define CONFIG_SYS_TIMER_RATE 32768
#define CONFIG_SYS_TIMER_COUNTER \
diff --git a/include/configs/mx35pdk.h b/include/configs/mx35pdk.h
index 41f518e49b0e33e85930ac631f23bb1fadef4faf..1b2f9529753e352cb73a6bc18d45876a844f0f95 100644
--- a/include/configs/mx35pdk.h
+++ b/include/configs/mx35pdk.h
@@ -19,7 +19,7 @@
#define CONFIG_MX35
#define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_FSL_CLK
+#define CONFIG_SYS_FSL_CLK
/* Set TEXT at the beginning of the NOR flash */
#define CONFIG_SYS_TEXT_BASE 0xA0000000
diff --git a/include/configs/mx51evk.h b/include/configs/mx51evk.h
index 35c9346638f693b57a58bf14b347fa770ae81fd8..32cd58ef442c07c296cd2aea4ec9ec939fc9bf67 100644
--- a/include/configs/mx51evk.h
+++ b/include/configs/mx51evk.h
@@ -18,7 +18,7 @@
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO
-#define CONFIG_FSL_CLK
+#define CONFIG_SYS_FSL_CLK
#define CONFIG_SYS_TEXT_BASE 0x97800000
#include <asm/arch/imx-regs.h>
diff --git a/include/configs/mx53ard.h b/include/configs/mx53ard.h
index be37ce5342196e0595b88bd50412e4d3037d6f90..fdb4134b132f11147337e7aa1c7e10151b3f1ecc 100644
--- a/include/configs/mx53ard.h
+++ b/include/configs/mx53ard.h
@@ -23,7 +23,7 @@
#define CONFIG_INITRD_TAG
#define CONFIG_REVISION_TAG
-#define CONFIG_FSL_CLK
+#define CONFIG_SYS_FSL_CLK
/* Size of malloc() pool */
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024)
diff --git a/include/configs/mx53evk.h b/include/configs/mx53evk.h
index 81af2486968fb3c0daf82f742e1e3f3715562986..37430f0a2a0d5ca087c43fa58e211473026c5693 100644
--- a/include/configs/mx53evk.h
+++ b/include/configs/mx53evk.h
@@ -23,7 +23,7 @@
#define CONFIG_INITRD_TAG
#define CONFIG_REVISION_TAG
-#define CONFIG_FSL_CLK
+#define CONFIG_SYS_FSL_CLK
#define CONFIG_OF_LIBFDT
diff --git a/include/configs/mx53loco.h b/include/configs/mx53loco.h
index 53fb4f79ef17f8f583af9278b249e3adbb358e34..54d3e3edd52d12c77095839ca37b6968aa22f6f7 100644
--- a/include/configs/mx53loco.h
+++ b/include/configs/mx53loco.h
@@ -22,7 +22,7 @@
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_INITRD_TAG
-#define CONFIG_FSL_CLK
+#define CONFIG_SYS_FSL_CLK
/* Size of malloc() pool */
#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
diff --git a/include/configs/mx53smd.h b/include/configs/mx53smd.h
index f5fcd838edda210b75f277c5956a9b7909b9584a..d915b883ce2b42a0a58aadb7a4883945bc64e7f9 100644
--- a/include/configs/mx53smd.h
+++ b/include/configs/mx53smd.h
@@ -23,7 +23,7 @@
#define CONFIG_INITRD_TAG
#define CONFIG_REVISION_TAG
-#define CONFIG_FSL_CLK
+#define CONFIG_SYS_FSL_CLK
/* Size of malloc() pool */
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024)
diff --git a/include/configs/mx6_common.h b/include/configs/mx6_common.h
index ba1317838421ed1047c0d0e9a4f904c5df609423..29bfbde3c5c9bd64c830e874b13721ead0122ae9 100644
--- a/include/configs/mx6_common.h
+++ b/include/configs/mx6_common.h
@@ -45,7 +45,7 @@
#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_FSL_CLK
+#define CONFIG_SYS_FSL_CLK
/* ATAGs */
#define CONFIG_CMDLINE_TAG
diff --git a/include/configs/mx7_common.h b/include/configs/mx7_common.h
index 04468b94eefdc1e2b56435d243362e9de9d62a24..1b6edeeae5d88dd9935d57687d81f036fa33f4d6 100644
--- a/include/configs/mx7_common.h
+++ b/include/configs/mx7_common.h
@@ -21,6 +21,7 @@
#define CONFIG_MXC_GPT_HCLK
#define CONFIG_SYSCOUNTER_TIMER
#define CONFIG_SC_TIMER_CLK 8000000 /* 8Mhz */
+#define CONFIG_SYS_FSL_CLK
/* Enable iomux-lpsr support */
#define CONFIG_IOMUX_LPSR
diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h
index 03eb185e16a57290bfe3738c4219e5e4bcca0741..433c4093361fa6a463410010dbf72ef484279b0f 100644
--- a/include/configs/p1_p2_rdb_pc.h
+++ b/include/configs/p1_p2_rdb_pc.h
@@ -11,7 +11,6 @@
#define __CONFIG_H
#define CONFIG_DISPLAY_BOARDINFO
-#define CONFIG_FSL_CLK
#ifdef CONFIG_36BIT
#define CONFIG_PHYS_64BIT
diff --git a/include/configs/p1_twr.h b/include/configs/p1_twr.h
index 46f5f0f70e5a5a4af0fc43841292bd659afbc0bf..d83daa02556700072051ece407bf22c2a4a77927 100644
--- a/include/configs/p1_twr.h
+++ b/include/configs/p1_twr.h
@@ -11,7 +11,6 @@
#define __CONFIG_H
#define CONFIG_DISPLAY_BOARDINFO
-#define CONFIG_FSL_CLK
#if defined(CONFIG_TWR_P1025)
#define CONFIG_BOARDNAME "TWR-P1025"
#define CONFIG_P1025
diff --git a/include/configs/usbarmory.h b/include/configs/usbarmory.h
index 6735055a616fca6e62f24ae4e726bad9a1226c82..6f6666281abb6eea67081827fdd12ee6fff1071a 100644
--- a/include/configs/usbarmory.h
+++ b/include/configs/usbarmory.h
@@ -14,7 +14,7 @@
#define CONFIG_MX53
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO
-#define CONFIG_FSL_CLK
+#define CONFIG_SYS_FSL_CLK
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_OF_LIBFDT
#define CONFIG_MXC_GPIO
diff --git a/include/configs/vf610twr.h b/include/configs/vf610twr.h
index abd1e98d9bebd281273076a666dbde91c611d027..a3ea2e0a1fabe01e779ebb5eca9f1f1e05d28580 100644
--- a/include/configs/vf610twr.h
+++ b/include/configs/vf610twr.h
@@ -15,7 +15,7 @@
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO
-#define CONFIG_FSL_CLK
+#define CONFIG_SYS_FSL_CLK
#define CONFIG_MACH_TYPE 4146
diff --git a/include/configs/woodburn_common.h b/include/configs/woodburn_common.h
index e6f3e28fe1dae6c22dba57e18850644a6b79669a..2acebf1a56d8ff3f6a9477c154d5bce47f3fb162 100644
--- a/include/configs/woodburn_common.h
+++ b/include/configs/woodburn_common.h
@@ -16,7 +16,7 @@
/* High Level Configuration Options */
#define CONFIG_MX35
#define CONFIG_MX35_HCLK_FREQ 24000000
-#define CONFIG_FSL_CLK
+#define CONFIG_SYS_FSL_CLK
#define CONFIG_SYS_DCACHE_OFF
#define CONFIG_SYS_CACHELINE_SIZE 32
diff --git a/include/fm_eth.h b/include/fm_eth.h
index 3e1b9f4281ada37d9604e376fcc83c236d181bb9..d43f801fdc953185267092b6e757c511a7b0c371 100644
--- a/include/fm_eth.h
+++ b/include/fm_eth.h
@@ -45,8 +45,10 @@ enum fm_eth_type {
#ifdef CONFIG_SYS_FMAN_V3
#define CONFIG_SYS_FM1_DTSEC_MDIO_ADDR (CONFIG_SYS_FSL_FM1_ADDR + 0xfc000)
#define CONFIG_SYS_FM1_TGEC_MDIO_ADDR (CONFIG_SYS_FSL_FM1_ADDR + 0xfd000)
+#if (CONFIG_SYS_NUM_FMAN == 2)
#define CONFIG_SYS_FM2_DTSEC_MDIO_ADDR (CONFIG_SYS_FSL_FM2_ADDR + 0xfc000)
#define CONFIG_SYS_FM2_TGEC_MDIO_ADDR (CONFIG_SYS_FSL_FM2_ADDR + 0xfd000)
+#endif
#else
#define CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR (CONFIG_SYS_FSL_FM1_ADDR + 0xe1120)
#define CONFIG_SYS_FM1_TGEC_MDIO_ADDR (CONFIG_SYS_FSL_FM1_ADDR + 0xf1000)
@@ -89,6 +91,7 @@ enum fm_eth_type {
offsetof(struct ccsr_fman, memac[n-1]),\
}
#else
+#if (CONFIG_SYS_NUM_FMAN == 2)
#define FM_TGEC_INFO_INITIALIZER(idx, n) \
{ \
FM_ETH_INFO_INITIALIZER(idx, CONFIG_SYS_FM2_TGEC_MDIO_ADDR) \
@@ -101,6 +104,20 @@ enum fm_eth_type {
.compat_offset = CONFIG_SYS_FSL_FM##idx##_OFFSET + \
offsetof(struct ccsr_fman, memac[n-1+8]),\
}
+#else
+#define FM_TGEC_INFO_INITIALIZER(idx, n) \
+{ \
+ FM_ETH_INFO_INITIALIZER(idx, CONFIG_SYS_FM1_TGEC_MDIO_ADDR) \
+ .index = idx, \
+ .num = n - 1, \
+ .type = FM_ETH_10G_E, \
+ .port = FM##idx##_10GEC##n, \
+ .rx_port_id = RX_PORT_10G_BASE + n - 1, \
+ .tx_port_id = TX_PORT_10G_BASE + n - 1, \
+ .compat_offset = CONFIG_SYS_FSL_FM##idx##_OFFSET + \
+ offsetof(struct ccsr_fman, memac[n-1+8]),\
+}
+#endif
#endif
#if (CONFIG_SYS_NUM_FM1_10GEC >= 3)
diff --git a/include/fsl_csu.h b/include/fsl_csu.h
new file mode 100644
index 0000000000000000000000000000000000000000..f4d97fb6054e08a872ec30b3df02d3b8d6cd2c60
--- /dev/null
+++ b/include/fsl_csu.h
@@ -0,0 +1,34 @@
+/*
+ * Copyright 2015 Freescale Semiconductor
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ */
+
+#ifndef __FSL_CSU_H__
+#define __FSL_CSU_H__
+
+enum csu_cslx_access {
+ CSU_NS_SUP_R = 0x08,
+ CSU_NS_SUP_W = 0x80,
+ CSU_NS_SUP_RW = 0x88,
+ CSU_NS_USER_R = 0x04,
+ CSU_NS_USER_W = 0x40,
+ CSU_NS_USER_RW = 0x44,
+ CSU_S_SUP_R = 0x02,
+ CSU_S_SUP_W = 0x20,
+ CSU_S_SUP_RW = 0x22,
+ CSU_S_USER_R = 0x01,
+ CSU_S_USER_W = 0x10,
+ CSU_S_USER_RW = 0x11,
+ CSU_ALL_RW = 0xff,
+};
+
+struct csu_ns_dev {
+ unsigned long ind;
+ uint32_t val;
+};
+
+void enable_layerscape_ns_access(void);
+
+#endif
diff --git a/include/fsl_ddr_sdram.h b/include/fsl_ddr_sdram.h
index e5b6e03c8fd7a569d07045270f32adef4528e0f1..c79fce089826f65cc6a5aa7ceddc3d6ab63e30d4 100644
--- a/include/fsl_ddr_sdram.h
+++ b/include/fsl_ddr_sdram.h
@@ -324,6 +324,8 @@ typedef struct memctl_options_s {
unsigned int dqs_config; /* Use DQS? maybe only with DDR2? */
/* SREN - self-refresh during sleep */
unsigned int self_refresh_in_sleep;
+ /* SR_IE - Self-refresh interrupt enable */
+ unsigned int self_refresh_interrupt_en;
unsigned int dynamic_power; /* DYN_PWR */
/* memory data width to use (16-bit, 32-bit, 64-bit) */
unsigned int data_bus_width;
diff --git a/arch/powerpc/include/asm/fsl_dtsec.h b/include/fsl_dtsec.h
similarity index 100%
rename from arch/powerpc/include/asm/fsl_dtsec.h
rename to include/fsl_dtsec.h
diff --git a/include/fsl_esdhc.h b/include/fsl_esdhc.h
index 0d00b7dfdbc5969bfd047cbacca57451a7756060..aa1b4cf1e4b9175b1fbbd55f552c09d3fdc9114c 100644
--- a/include/fsl_esdhc.h
+++ b/include/fsl_esdhc.h
@@ -166,7 +166,7 @@
#define ESDHC_VENDORSPEC_VSELECT 0x00000002 /* Use 1.8V */
struct fsl_esdhc_cfg {
-#ifdef CONFIG_LS2085A
+#ifdef CONFIG_FSL_LAYERSCAPE
u64 esdhc_base;
#else
u32 esdhc_base;
diff --git a/arch/powerpc/include/asm/fsl_fman.h b/include/fsl_fman.h
similarity index 100%
rename from arch/powerpc/include/asm/fsl_fman.h
rename to include/fsl_fman.h
diff --git a/include/fsl_sec.h b/include/fsl_sec.h
index abc62da9928b1befb95e59d497b815ca1c0ec74b..2ddced34ab742de4c47b54217b99f56a3f486ab3 100644
--- a/include/fsl_sec.h
+++ b/include/fsl_sec.h
@@ -194,11 +194,9 @@ struct jr_regs {
struct sg_entry {
#if defined(CONFIG_SYS_FSL_SEC_LE) && !defined(CONFIG_MX6)
uint32_t addr_lo; /* Memory Address - lo */
- uint16_t addr_hi; /* Memory Address of start of buffer - hi */
- uint16_t reserved_zero;
+ uint32_t addr_hi; /* Memory Address of start of buffer - hi */
#else
- uint16_t reserved_zero;
- uint16_t addr_hi; /* Memory Address of start of buffer - hi */
+ uint32_t addr_hi; /* Memory Address of start of buffer - hi */
uint32_t addr_lo; /* Memory Address - lo */
#endif
diff --git a/arch/powerpc/include/asm/fsl_tgec.h b/include/fsl_tgec.h
similarity index 100%
rename from arch/powerpc/include/asm/fsl_tgec.h
rename to include/fsl_tgec.h
diff --git a/include/fsl_validate.h b/include/fsl_validate.h
index c4605349a67170e939441784882536e33b9799f1..92dd98bb6156d0586cdd676d8c2b42146d6cd8f7 100644
--- a/include/fsl_validate.h
+++ b/include/fsl_validate.h
@@ -82,14 +82,14 @@ struct fsl_secboot_img_hdr {
u32 psign; /* signature offset */
u32 sign_len; /* length of the signature in bytes */
union {
- struct fsl_secboot_sg_table *psgtable; /* ptr to SG table */
- u8 *pimg; /* ptr to ESBC client image */
+ u32 psgtable; /* ptr to SG table */
+ u32 pimg; /* ptr to ESBC client image */
};
union {
u32 sg_entries; /* no of entries in SG table */
u32 img_size; /* ESBC client image size in bytes */
};
- ulong img_start; /* ESBC client entry point */
+ u32 img_start; /* ESBC client entry point */
u32 sg_flag; /* Scatter gather flag */
u32 uid_flag;
u32 fsl_uid_0;
@@ -133,7 +133,7 @@ struct srk_table {
*/
struct fsl_secboot_sg_table {
u32 len; /* length of the segment in bytes */
- ulong src_addr; /* ptr to the data segment */
+ u32 src_addr; /* ptr to the data segment */
};
#else
/*
@@ -146,8 +146,8 @@ struct fsl_secboot_sg_table {
struct fsl_secboot_sg_table {
u32 len;
u32 trgt_id;
- ulong src_addr;
- ulong dst_addr;
+ u32 src_addr;
+ u32 dst_addr;
};
#endif
@@ -162,7 +162,7 @@ struct fsl_secboot_sg_table {
*/
struct fsl_secboot_img_priv {
uint32_t hdr_location;
- ulong ie_addr;
+ u32 ie_addr;
u32 key_len;
struct fsl_secboot_img_hdr hdr;