From 586d92ced577b218c436b158ebffba07a6f5b050 Mon Sep 17 00:00:00 2001 From: Troy Kisky <troy.kisky@boundarydevices.com> Date: Tue, 1 Jan 2019 13:36:46 -0800 Subject: [PATCH] nitrogen8m: use CONFIG_IMX8M_LPDDR4 Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com> --- board/boundary/nitrogen8m/Makefile | 1 + board/boundary/nitrogen8m/ddr/ddr.h | 26 +- board/boundary/nitrogen8m/ddr/ddr_init.c | 4 +- .../boundary/nitrogen8m/ddr/ddr_memory_map.h | 1640 -------------- board/boundary/nitrogen8m/ddr/ddrphy_train.c | 2018 +++++++++-------- board/boundary/nitrogen8m/ddr/helper.c | 2 +- .../ddr/wait_ddrphy_training_complete.c | 2 +- board/boundary/nitrogen8m/lpddr4_timing.c | 1 + board/boundary/nitrogen8m/spl.c | 8 +- configs/nitrogen8m_3g_defconfig | 1 + configs/nitrogen8m_4g_defconfig | 1 + configs/nitrogen8m_defconfig | 2 +- 12 files changed, 1027 insertions(+), 2679 deletions(-) diff --git a/board/boundary/nitrogen8m/Makefile b/board/boundary/nitrogen8m/Makefile index 7cef3e35e95..63855368716 100644 --- a/board/boundary/nitrogen8m/Makefile +++ b/board/boundary/nitrogen8m/Makefile @@ -10,6 +10,7 @@ ifdef CONFIG_SPL_BUILD obj-y += spl.o ifdef CONFIG_IMX8M_LPDDR4 obj-y += lpddr4_timing.o +obj-y += ddr/ddr_init.o ddr/ddrphy_train.o ddr/helper.o else obj-y += ddr/ddr_init.o ddr/ddrphy_train.o ddr/helper.o endif diff --git a/board/boundary/nitrogen8m/ddr/ddr.h b/board/boundary/nitrogen8m/ddr/ddr.h index a8e4ca8c617..c60f5c28cb7 100644 --- a/board/boundary/nitrogen8m/ddr/ddr.h +++ b/board/boundary/nitrogen8m/ddr/ddr.h @@ -4,36 +4,16 @@ * SPDX-License-Identifier: GPL-2.0+ */ -enum fw_type { - FW_1D_IMAGE, - FW_2D_IMAGE, -}; - -void ddr_init(void); +void ddr_init1(void); void ddr_load_train_code(enum fw_type type); void lpddr4_800M_cfg_phy(void); -static inline void reg32_write(unsigned long addr, u32 val) -{ - writel(val, addr); -} - static inline void reg32_writep(u32 *addr, u32 val) { writel(val, addr); } -static inline uint32_t reg32_read(unsigned long addr) -{ - return readl(addr); -} - -static void inline dwc_ddrphy_apb_wr(unsigned long addr, u32 val) -{ - writel(val, addr); -} - -static inline void reg32setbit(unsigned long addr, u32 bit) +static void inline dwc_ddrphy_apb_wr0(unsigned long addr, u32 val) { - setbits_le32(addr, (1 << bit)); + writel(val, IP2APB_DDRPHY_IPS_BASE_ADDR(0) + addr); } diff --git a/board/boundary/nitrogen8m/ddr/ddr_init.c b/board/boundary/nitrogen8m/ddr/ddr_init.c index a1ed2a3b836..e12331e07e9 100644 --- a/board/boundary/nitrogen8m/ddr/ddr_init.c +++ b/board/boundary/nitrogen8m/ddr/ddr_init.c @@ -8,6 +8,8 @@ #include <errno.h> #include <asm/io.h> #include <asm/arch/clock.h> +#include <asm/arch/ddr.h> +#include <asm/arch/imx8m_ddr.h> #include "ddr.h" #include "ddr_memory_map.h" @@ -212,7 +214,7 @@ void lpddr4_800MHz_cfg_umctl2(void) reg32_write(DDRC_PCFGWQOS1_0(0), 0x0000ffff); } -void ddr_init(void) +void ddr_init1(void) { struct ccm_reg *ccm_reg = (struct ccm_reg *)CCM_BASE_ADDR; diff --git a/board/boundary/nitrogen8m/ddr/ddr_memory_map.h b/board/boundary/nitrogen8m/ddr/ddr_memory_map.h index 7386dbb0f10..7b4b6ebd3e5 100644 --- a/board/boundary/nitrogen8m/ddr/ddr_memory_map.h +++ b/board/boundary/nitrogen8m/ddr/ddr_memory_map.h @@ -496,1644 +496,4 @@ #define DDRC_DFITMG3_SHADOW(X) (DDRC_IPS_BASE_ADDR(X) + 0x21b8) #define DDRC_ODTCFG_SHADOW(X) (DDRC_IPS_BASE_ADDR(X) + 0x2240) -//#define IP2APB_DDRPHY_IPS_BASE_ADDR(X) DDRPHY1_IPS_BASE_ADDR - X*0x00030000 -//#define IP2APB_DDRPHY_IPS_BASE_ADDR(X) 0xbc000000 + (X * 0x2000000) -//#define DDRPHY_MEM(X) 0xbc000000 + (X * 0x2000000) + 0x50000 -#define IP2APB_DDRPHY_IPS_BASE_ADDR(X) (0x3c000000 + (X * 0x2000000)) #define DDRPHY_MEM(X) (0x3c000000 + (X * 0x2000000) + 0x50000) -//#define IP2APB_DDRPHY_IPS_BASE_ADDR(X) 0x3c000000 + (X * 0x2000000) - -#if 0 -/* todo: fix*/ -#define DDRPHY_AcsmSeq0x0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x040000) -#define DDRPHY_AcsmSeq0x1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x040001) -#define DDRPHY_AcsmSeq0x2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x040002) -#define DDRPHY_AcsmSeq0x3(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x040003) -#define DDRPHY_AcsmSeq0x4(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x040004) -#define DDRPHY_AcsmSeq0x5(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x040005) -#define DDRPHY_AcsmSeq0x6(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x040006) -#define DDRPHY_AcsmSeq0x7(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x040007) -#define DDRPHY_AcsmSeq0x8(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x040008) -#define DDRPHY_AcsmSeq0x9(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x040009) -#define DDRPHY_AcsmSeq0x10(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x04000A) -#define DDRPHY_AcsmSeq0x11(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x04000B) -#define DDRPHY_AcsmSeq0x12(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x04000C) -#define DDRPHY_AcsmSeq0x13(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x04000D) -#define DDRPHY_AcsmSeq0x14(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x04000E) -#define DDRPHY_AcsmSeq0x15(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x04000F) -#define DDRPHY_AcsmSeq0x16(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x040010) -#define DDRPHY_AcsmSeq0x17(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x040011) -#define DDRPHY_AcsmSeq0x18(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x040012) -#define DDRPHY_AcsmSeq0x19(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x040013) -#define DDRPHY_AcsmSeq0x20(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x040014) -#define DDRPHY_AcsmSeq0x21(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x040015) -#define DDRPHY_AcsmSeq0x22(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x040016) -#define DDRPHY_AcsmSeq0x23(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x040017) -#define DDRPHY_AcsmSeq0x24(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x040018) -#define DDRPHY_AcsmSeq0x25(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x040019) -#define DDRPHY_AcsmSeq0x26(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x04001A) -#define DDRPHY_AcsmSeq0x27(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x04001B) -#define DDRPHY_AcsmSeq0x28(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x04001C) -#define DDRPHY_AcsmSeq0x29(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x04001D) -#define DDRPHY_AcsmSeq0x30(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x04001E) -#define DDRPHY_AcsmSeq0x31(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x04001F) - -#define DDRPHY_AcsmSeq1x0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x040020) -#define DDRPHY_AcsmSeq1x1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x040021) -#define DDRPHY_AcsmSeq1x2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x040022) -#define DDRPHY_AcsmSeq1x3(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x040023) -#define DDRPHY_AcsmSeq1x4(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x040024) -#define DDRPHY_AcsmSeq1x5(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x040025) -#define DDRPHY_AcsmSeq1x6(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x040026) -#define DDRPHY_AcsmSeq1x7(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x040027) -#define DDRPHY_AcsmSeq1x8(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x040028) -#define DDRPHY_AcsmSeq1x9(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x040029) -#define DDRPHY_AcsmSeq1x10(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x04002A) -#define DDRPHY_AcsmSeq1x11(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x04002B) -#define DDRPHY_AcsmSeq1x12(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x04002C) -#define DDRPHY_AcsmSeq1x13(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x04002D) -#define DDRPHY_AcsmSeq1x14(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x04002E) -#define DDRPHY_AcsmSeq1x15(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x04002F) -#define DDRPHY_AcsmSeq1x16(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x040030) -#define DDRPHY_AcsmSeq1x17(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x040031) -#define DDRPHY_AcsmSeq1x18(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x040032) -#define DDRPHY_AcsmSeq1x19(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x040033) -#define DDRPHY_AcsmSeq1x20(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x040034) -#define DDRPHY_AcsmSeq1x21(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x040035) -#define DDRPHY_AcsmSeq1x22(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x040036) -#define DDRPHY_AcsmSeq1x23(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x040037) -#define DDRPHY_AcsmSeq1x24(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x040038) -#define DDRPHY_AcsmSeq1x25(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x040039) -#define DDRPHY_AcsmSeq1x26(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x04003A) -#define DDRPHY_AcsmSeq1x27(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x04003B) -#define DDRPHY_AcsmSeq1x28(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x04003C) -#define DDRPHY_AcsmSeq1x29(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x04003D) -#define DDRPHY_AcsmSeq1x30(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x04003E) -#define DDRPHY_AcsmSeq1x31(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x04003F) - -#define DDRPHY_AcsmSeq2x0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x040040) -#define DDRPHY_AcsmSeq2x1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x040041) -#define DDRPHY_AcsmSeq2x2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x040042) -#define DDRPHY_AcsmSeq2x3(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x040043) -#define DDRPHY_AcsmSeq2x4(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x040044) -#define DDRPHY_AcsmSeq2x5(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x040045) -#define DDRPHY_AcsmSeq2x6(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x040046) -#define DDRPHY_AcsmSeq2x7(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x040047) -#define DDRPHY_AcsmSeq2x8(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x040048) -#define DDRPHY_AcsmSeq2x9(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x040049) -#define DDRPHY_AcsmSeq2x10(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x04004A) -#define DDRPHY_AcsmSeq2x11(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x04004B) -#define DDRPHY_AcsmSeq2x12(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x04004C) -#define DDRPHY_AcsmSeq2x13(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x04004D) -#define DDRPHY_AcsmSeq2x14(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x04004E) -#define DDRPHY_AcsmSeq2x15(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x04004F) -#define DDRPHY_AcsmSeq2x16(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x040050) -#define DDRPHY_AcsmSeq2x17(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x040051) -#define DDRPHY_AcsmSeq2x18(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x040052) -#define DDRPHY_AcsmSeq2x19(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x040053) -#define DDRPHY_AcsmSeq2x20(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x040054) -#define DDRPHY_AcsmSeq2x21(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x040055) -#define DDRPHY_AcsmSeq2x22(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x040056) -#define DDRPHY_AcsmSeq2x23(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x040057) -#define DDRPHY_AcsmSeq2x24(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x040058) -#define DDRPHY_AcsmSeq2x25(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x040059) -#define DDRPHY_AcsmSeq2x26(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x04005A) -#define DDRPHY_AcsmSeq2x27(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x04005B) -#define DDRPHY_AcsmSeq2x28(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x04005C) -#define DDRPHY_AcsmSeq2x29(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x04005D) -#define DDRPHY_AcsmSeq2x30(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x04005E) -#define DDRPHY_AcsmSeq2x31(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x04005F) - -#define DDRPHY_AcsmSeq3x0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x040060) -#define DDRPHY_AcsmSeq3x1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x040061) -#define DDRPHY_AcsmSeq3x2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x040062) -#define DDRPHY_AcsmSeq3x3(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x040063) -#define DDRPHY_AcsmSeq3x4(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x040064) -#define DDRPHY_AcsmSeq3x5(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x040065) -#define DDRPHY_AcsmSeq3x6(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x040066) -#define DDRPHY_AcsmSeq3x7(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x040067) -#define DDRPHY_AcsmSeq3x8(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x040068) -#define DDRPHY_AcsmSeq3x9(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x040069) -#define DDRPHY_AcsmSeq3x10(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x04006A) -#define DDRPHY_AcsmSeq3x11(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x04006B) -#define DDRPHY_AcsmSeq3x12(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x04006C) -#define DDRPHY_AcsmSeq3x13(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x04006D) -#define DDRPHY_AcsmSeq3x14(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x04006E) -#define DDRPHY_AcsmSeq3x15(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x04006F) -#define DDRPHY_AcsmSeq3x16(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x040070) -#define DDRPHY_AcsmSeq3x17(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x040071) -#define DDRPHY_AcsmSeq3x18(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x040072) -#define DDRPHY_AcsmSeq3x19(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x040073) -#define DDRPHY_AcsmSeq3x20(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x040074) -#define DDRPHY_AcsmSeq3x21(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x040075) -#define DDRPHY_AcsmSeq3x22(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x040076) -#define DDRPHY_AcsmSeq3x23(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x040077) -#define DDRPHY_AcsmSeq3x24(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x040078) -#define DDRPHY_AcsmSeq3x25(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x040079) -#define DDRPHY_AcsmSeq3x26(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x04007A) -#define DDRPHY_AcsmSeq3x27(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x04007B) -#define DDRPHY_AcsmSeq3x28(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x04007C) -#define DDRPHY_AcsmSeq3x29(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x04007D) -#define DDRPHY_AcsmSeq3x30(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x04007E) -#define DDRPHY_AcsmSeq3x31(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x04007F) - -#define DDRPHY_AcsmPlayback0x0_0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x040080) -#define DDRPHY_AcsmPlayback0x0_1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x140080) -#define DDRPHY_AcsmPlayback0x0_2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x240080) -#define DDRPHY_AcsmPlayback0x0_3(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x340080) - -#define DDRPHY_AcsmPlayback1x0_0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x040081) -#define DDRPHY_AcsmPlayback1x0_1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x140081) -#define DDRPHY_AcsmPlayback1x0_2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x240081) -#define DDRPHY_AcsmPlayback1x0_3(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x340081) - -#define DDRPHY_AcsmPlayback0x1_0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x040082) -#define DDRPHY_AcsmPlayback0x1_1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x140082) -#define DDRPHY_AcsmPlayback0x1_2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x240082) -#define DDRPHY_AcsmPlayback0x1_3(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x340082) - -#define DDRPHY_AcsmPlayback1x1_0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x040083) -#define DDRPHY_AcsmPlayback1x1_1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x140083) -#define DDRPHY_AcsmPlayback1x1_2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x240083) -#define DDRPHY_AcsmPlayback1x1_3(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x340083) - -#define DDRPHY_AcsmPlayback0x2_0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x040084) -#define DDRPHY_AcsmPlayback0x2_1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x140084) -#define DDRPHY_AcsmPlayback0x2_2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x240084) -#define DDRPHY_AcsmPlayback0x2_3(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x340084) - -#define DDRPHY_AcsmPlayback1x2_0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x040085) -#define DDRPHY_AcsmPlayback1x2_1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x140085) -#define DDRPHY_AcsmPlayback1x2_2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x240085) -#define DDRPHY_AcsmPlayback1x2_3(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x340085) - -#define DDRPHY_AcsmPlayback0x3_0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x040086) -#define DDRPHY_AcsmPlayback0x3_1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x140086) -#define DDRPHY_AcsmPlayback0x3_2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x240086) -#define DDRPHY_AcsmPlayback0x3_3(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x340086) - -#define DDRPHY_AcsmPlayback1x3_0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x040087) -#define DDRPHY_AcsmPlayback1x3_1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x140087) -#define DDRPHY_AcsmPlayback1x3_2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x240087) -#define DDRPHY_AcsmPlayback1x3_3(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x340087) - -#define DDRPHY_AcsmPlayback0x4_0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x040088) -#define DDRPHY_AcsmPlayback0x4_1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x140088) -#define DDRPHY_AcsmPlayback0x4_2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x240088) -#define DDRPHY_AcsmPlayback0x4_3(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x340088) - -#define DDRPHY_AcsmPlayback1x4_0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x040089) -#define DDRPHY_AcsmPlayback1x4_1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x140089) -#define DDRPHY_AcsmPlayback1x4_2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x240089) -#define DDRPHY_AcsmPlayback1x4_3(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x340089) - -#define DDRPHY_AcsmPlayback0x5_0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x04008A) -#define DDRPHY_AcsmPlayback0x5_1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x14008A) -#define DDRPHY_AcsmPlayback0x5_2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x24008A) -#define DDRPHY_AcsmPlayback0x5_3(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x34008A) - -#define DDRPHY_AcsmPlayback1x5_0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x04008B) -#define DDRPHY_AcsmPlayback1x5_1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x14008B) -#define DDRPHY_AcsmPlayback1x5_2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x24008B) -#define DDRPHY_AcsmPlayback1x5_3(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x34008B) - -#define DDRPHY_AcsmPlayback0x6_0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x04008C) -#define DDRPHY_AcsmPlayback0x6_1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x14008C) -#define DDRPHY_AcsmPlayback0x6_2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x24008C) -#define DDRPHY_AcsmPlayback0x6_3(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x34008C) - -#define DDRPHY_AcsmPlayback1x6_0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x04008D) -#define DDRPHY_AcsmPlayback1x6_1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x14008D) -#define DDRPHY_AcsmPlayback1x6_2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x24008D) -#define DDRPHY_AcsmPlayback1x6_3(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x34008D) - -#define DDRPHY_AcsmPlayback0x7_0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x04008E) -#define DDRPHY_AcsmPlayback0x7_1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x14008E) -#define DDRPHY_AcsmPlayback0x7_2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x24008E) -#define DDRPHY_AcsmPlayback0x7_3(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x34008E) - -#define DDRPHY_AcsmPlayback1x7_0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x04008F) -#define DDRPHY_AcsmPlayback1x7_1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x14008F) -#define DDRPHY_AcsmPlayback1x7_2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x24008F) -#define DDRPHY_AcsmPlayback1x7_3(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x34008F) - -#define DDRPHY_AcsmCtrl23(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0400C0) -#define DDRPHY_AcsmCkeVal(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0400C2) -#define DDRPHY_LowSpeedClockDivider(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0400C8) -#define DDRPHY_AcsmCsMapCtrl0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0400D0) -#define DDRPHY_AcsmCsMapCtrl1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0400D1) -#define DDRPHY_AcsmCsMapCtrl2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0400D2) -#define DDRPHY_AcsmCsMapCtrl3(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0400D3) -#define DDRPHY_AcsmCsMapCtrl4(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0400D4) -#define DDRPHY_AcsmCsMapCtrl5(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0400D5) -#define DDRPHY_AcsmCsMapCtrl6(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0400D6) -#define DDRPHY_AcsmCsMapCtrl7(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0400D7) -#define DDRPHY_AcsmCsMapCtrl8(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0400D8) -#define DDRPHY_AcsmCsMapCtrl9(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0400D9) -#define DDRPHY_AcsmCsMapCtrl10(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0400DA) -#define DDRPHY_AcsmCsMapCtrl11(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0400DB) -#define DDRPHY_AcsmCsMapCtrl12(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0400DC) -#define DDRPHY_AcsmCsMapCtrl13(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0400DD) -#define DDRPHY_AcsmCsMapCtrl14(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0400DE) -#define DDRPHY_AcsmCsMapCtrl15(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0400DF) - -#define DDRPHY_AcsmOdtCtrl0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0400E0) -#define DDRPHY_AcsmOdtCtrl1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0400E1) -#define DDRPHY_AcsmOdtCtrl2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0400E2) -#define DDRPHY_AcsmOdtCtrl3(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0400E3) -#define DDRPHY_AcsmOdtCtrl4(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0400E4) -#define DDRPHY_AcsmOdtCtrl5(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0400E5) -#define DDRPHY_AcsmOdtCtrl6(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0400E6) -#define DDRPHY_AcsmOdtCtrl7(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0400E7) -#define DDRPHY_AcsmOdtCtrl8(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0400E8) -#define DDRPHY_AcsmCtrl16(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0400E9) -#define DDRPHY_AcsmCtrl18(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0400EB) -#define DDRPHY_AcsmCtrl19(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0400EC) -#define DDRPHY_AcsmCtrl20(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0400ED) -#define DDRPHY_AcsmCtrl21(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0400EE) -#define DDRPHY_AcsmCtrl22(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0400EF) -#define DDRPHY_AcsmCtrl0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0400F0) -#define DDRPHY_AcsmCtrl1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0400F1) -#define DDRPHY_AcsmCtrl2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0400F2) -#define DDRPHY_AcsmCtrl3(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0400F3) -#define DDRPHY_AcsmCtrl4(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0400F4) -#define DDRPHY_AcsmCtrl5(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0400F5) -#define DDRPHY_AcsmCtrl6(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0400F6) -#define DDRPHY_AcsmCtrl7(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0400F7) -#define DDRPHY_AcsmCtrl8(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0400F8) -#define DDRPHY_AcsmCtrl9(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0400F9) -#define DDRPHY_AcsmCtrl10(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0400FA) -#define DDRPHY_AcsmCtrl11(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0400FB) -#define DDRPHY_AcsmCtrl12(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0400FC) -#define DDRPHY_AcsmCtrl13(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0400FD) -#define DDRPHY_AcsmCtrl14(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0400FE) -#define DDRPHY_AcsmCtrl15(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0400FF) - -#define DDRPHY_MtestMuxSel(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x00001A) -#define DDRPHY_AForceTriCont(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x000028) -#define DDRPHY_ATxImpedance(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x000043) -#define DDRPHY_ATestPrbsErr(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x000053) -#define DDRPHY_ATxSlewRate(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x000055) -#define DDRPHY_ATestPrbsErrCnt(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x000056) -#define DDRPHY_ATxDly_0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x000080) -#define DDRPHY_ATxDly_1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x100080) -#define DDRPHY_ATxDly_2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x200080) -#define DDRPHY_ATxDly_3(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x300080) - -#define DDRPHY_MicroContMuxSel(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0D0000) -#define DDRPHY_UctShadowRegs(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0D0004) -#define DDRPHY_DctWriteOnly(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0D0030) -#define DDRPHY_DctWriteProt(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0D0031) -#define DDRPHY_UctWriteOnlyShadow(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0D0032) -#define DDRPHY_UctDatWriteOnlyShadow(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0D0034) -#define DDRPHY_NeverGateCsrClock(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0D0035) -#define DDRPHY_DfiCfgRdDataValidTicks(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0D0037) -#define DDRPHY_MicroReset(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0D0099) -#define DDRPHY_SequencerOverride(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0D00E7) -#define DDRPHY_DfiInitCompleteShadow(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0D00FA) - -#define DDRPHY_DbyteMiscMode(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x010000) -#define DDRPHY_TsmByte0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x010001) -#define DDRPHY_TrainingParam(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x010002) -#define DDRPHY_RxTrainPatternEnable(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x010010) -#define DDRPHY_TsmByte1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x010011) -#define DDRPHY_TsmByte2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x010012) -#define DDRPHY_TsmByte3(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x010013) -#define DDRPHY_TsmByte4(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x010014) -#define DDRPHY_TestModeConfig(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x010017) -#define DDRPHY_TsmByte5(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x010018) -#define DDRPHY_MtestMuxSel(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x01001A) -#define DDRPHY_DtsmTrainModeCtrl(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x01001F) -#define DDRPHY_DFIMRL_0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x010020) -#define DDRPHY_DFIMRL_1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x110020) -#define DDRPHY_DFIMRL_2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x210020) -#define DDRPHY_DFIMRL_3(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x310020) -#define DDRPHY_TrainingCntrFineMax_0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x010022) -#define DDRPHY_TrainingCntrFineMax_1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x010122) -#define DDRPHY_TrainingCntrFineMax_2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x010222) -#define DDRPHY_TrainingCntrFineMax_3(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x010322) -#define DDRPHY_TrainingCntrFineMax_4(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x010422) -#define DDRPHY_TrainingCntrFineMax_5(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x010522) -#define DDRPHY_TrainingCntrFineMax_6(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x010622) -#define DDRPHY_TrainingCntrFineMax_7(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x010722) -#define DDRPHY_TrainingCntrFineMax_8(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x010822) -#define DDRPHY_TrainingCntrFineMaxRxEn_0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x010023) -#define DDRPHY_TrainingCntrFineMaxRxEn_1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x010123) - -#define DDRPHY_AsyncDbyteMode(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x010024) -#define DDRPHY_AsyncDbyteTxEn(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x010026) -#define DDRPHY_AsyncDbyteTxData(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x010028) -#define DDRPHY_AsyncDbyteRxData(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x01002A) -#define DDRPHY_VrefDAC1_0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x010030) -#define DDRPHY_VrefDAC1_1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x010130) -#define DDRPHY_VrefDAC1_2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x010230) -#define DDRPHY_VrefDAC1_3(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x010330) -#define DDRPHY_VrefDAC1_4(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x010430) -#define DDRPHY_VrefDAC1_5(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x010530) -#define DDRPHY_VrefDAC1_6(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x010630) -#define DDRPHY_VrefDAC1_7(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x010730) -#define DDRPHY_VrefDAC1_8(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x010830) - -#define DDRPHY_TrainingCntr_0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x010032) -#define DDRPHY_TrainingCntr_1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x010132) -#define DDRPHY_TrainingCntr_2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x010232) -#define DDRPHY_TrainingCntr_3(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x010332) -#define DDRPHY_TrainingCntr_4(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x010432) -#define DDRPHY_TrainingCntr_5(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x010532) -#define DDRPHY_TrainingCntr_6(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x010632) -#define DDRPHY_TrainingCntr_7(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x010732) -#define DDRPHY_TrainingCntr_8(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x010832) - -#define DDRPHY_VrefDAC0_0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x010040) -#define DDRPHY_VrefDAC0_1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x010140) -#define DDRPHY_VrefDAC0_2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x010240) -#define DDRPHY_VrefDAC0_3(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x010340) -#define DDRPHY_VrefDAC0_4(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x010440) -#define DDRPHY_VrefDAC0_5(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x010540) -#define DDRPHY_VrefDAC0_6(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x010640) -#define DDRPHY_VrefDAC0_7(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x010740) -#define DDRPHY_VrefDAC0_8(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x010840) - -#define DDRPHY_TxImpedanceDq_0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x010041) -#define DDRPHY_TxImpedanceDq_1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x010141) -#define DDRPHY_TxImpedanceDq_2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x110041) -#define DDRPHY_TxImpedanceDq_3(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x110141) -#define DDRPHY_TxImpedanceDq_4(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x210041) -#define DDRPHY_TxImpedanceDq_5(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x210141) -#define DDRPHY_TxImpedanceDq_6(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x310041) -#define DDRPHY_TxImpedanceDq_7(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x310141) - -#define DDRPHY_DqDqsRcvCntrl_0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x010043) -#define DDRPHY_DqDqsRcvCntrl_1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x010143) -#define DDRPHY_DqDqsRcvCntrl_2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x110043) -#define DDRPHY_DqDqsRcvCntrl_3(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x110143) -#define DDRPHY_DqDqsRcvCntrl_4(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x210043) -#define DDRPHY_DqDqsRcvCntrl_5(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x210143) -#define DDRPHY_DqDqsRcvCntrl_6(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x310043) -#define DDRPHY_DqDqsRcvCntrl_7(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x310143) - -#define DDRPHY_TxEqualizationMode_0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x010048) -#define DDRPHY_TxEqualizationMode_1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x110048) -#define DDRPHY_TxEqualizationMode_2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x210048) -#define DDRPHY_TxEqualizationMode_3(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x310048) - -#define DDRPHY_TxEqImpedanceDq_0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x010049) -#define DDRPHY_TxEqImpedanceDq_1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x010149) -#define DDRPHY_TxEqImpedanceDq_2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x110049) -#define DDRPHY_TxEqImpedanceDq_3(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x110149) -#define DDRPHY_TxEqImpedanceDq_4(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x210049) -#define DDRPHY_TxEqImpedanceDq_5(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x210149) -#define DDRPHY_TxEqImpedanceDq_6(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x310049) -#define DDRPHY_TxEqImpedanceDq_7(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x310149) - -#define DDRPHY_DqDqsRcvCntrl1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x01004A) - -#define DDRPHY_TxEqHiImpedanceDq_0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x01004B) -#define DDRPHY_TxEqHiImpedanceDq_1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x01014B) -#define DDRPHY_TxEqHiImpedanceDq_2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x11004B) -#define DDRPHY_TxEqHiImpedanceDq_3(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x11014B) -#define DDRPHY_TxEqHiImpedanceDq_4(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x21004B) -#define DDRPHY_TxEqHiImpedanceDq_5(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x21014B) -#define DDRPHY_TxEqHiImpedanceDq_6(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x31004B) -#define DDRPHY_TxEqHiImpedanceDq_7(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x31014B) - -#define DDRPHY_DqDqsRcvCntrl2_0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x01004C) -#define DDRPHY_DqDqsRcvCntrl2_1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x11004C) -#define DDRPHY_DqDqsRcvCntrl2_2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x21004C) -#define DDRPHY_DqDqsRcvCntrl2_3(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x31004C) - -#define DDRPHY_TxOdtDrvStren_0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x01004D) -#define DDRPHY_TxOdtDrvStren_1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x01014D) -#define DDRPHY_TxOdtDrvStren_2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x11004D) -#define DDRPHY_TxOdtDrvStren_3(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x11014D) -#define DDRPHY_TxOdtDrvStren_4(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x21004D) -#define DDRPHY_TxOdtDrvStren_5(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x21014D) -#define DDRPHY_TxOdtDrvStren_6(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x31004D) -#define DDRPHY_TxOdtDrvStren_7(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x31014D) - -#define DDRPHY_RxFifoInfo(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x010058) -#define DDRPHY_RxFifoVisibility(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x010059) -#define DDRPHY_RxFifoContentsDQ3210(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x01005A) -#define DDRPHY_RxFifoContentsDQ7654(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x01005B) -#define DDRPHY_RxFifoContentsDBI(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x01005C) - -#define DDRPHY_TxSlewRate_0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x01005F) -#define DDRPHY_TxSlewRate_1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x01015F) -#define DDRPHY_TxSlewRate_2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x11005F) -#define DDRPHY_TxSlewRate_3(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x11015F) -#define DDRPHY_TxSlewRate_4(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x21005F) -#define DDRPHY_TxSlewRate_5(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x21015F) -#define DDRPHY_TxSlewRate_6(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x31005F) -#define DDRPHY_TxSlewRate_7(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x31015F) - -#define DDRPHY_TrainingIncDecDtsmEn_0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x010062) -#define DDRPHY_TrainingIncDecDtsmEn_1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x010162) -#define DDRPHY_TrainingIncDecDtsmEn_2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x010262) -#define DDRPHY_TrainingIncDecDtsmEn_3(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x010362) -#define DDRPHY_TrainingIncDecDtsmEn_4(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x010462) -#define DDRPHY_TrainingIncDecDtsmEn_5(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x010562) -#define DDRPHY_TrainingIncDecDtsmEn_6(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x010662) -#define DDRPHY_TrainingIncDecDtsmEn_7(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x010762) -#define DDRPHY_TrainingIncDecDtsmEn_8(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x010862) - -#define DDRPHY_RxPBDlyTg0_0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x010068) -#define DDRPHY_RxPBDlyTg0_1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x010168) -#define DDRPHY_RxPBDlyTg0_2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x010268) -#define DDRPHY_RxPBDlyTg0_3(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x010368) -#define DDRPHY_RxPBDlyTg0_4(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x010468) -#define DDRPHY_RxPBDlyTg0_5(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x010568) -#define DDRPHY_RxPBDlyTg0_6(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x010668) -#define DDRPHY_RxPBDlyTg0_7(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x010768) -#define DDRPHY_RxPBDlyTg0_8(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x010868) - -#define DDRPHY_RxPBDlyTg1_0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x010069) -#define DDRPHY_RxPBDlyTg1_1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x010169) -#define DDRPHY_RxPBDlyTg1_2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x010269) -#define DDRPHY_RxPBDlyTg1_3(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x010369) -#define DDRPHY_RxPBDlyTg1_4(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x010469) -#define DDRPHY_RxPBDlyTg1_5(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x010569) -#define DDRPHY_RxPBDlyTg1_6(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x010669) -#define DDRPHY_RxPBDlyTg1_7(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x010769) -#define DDRPHY_RxPBDlyTg1_8(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x010869) - -#define DDRPHY_RxPBDlyTg2_0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x01006A) -#define DDRPHY_RxPBDlyTg2_1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x01016A) -#define DDRPHY_RxPBDlyTg2_2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x01026A) -#define DDRPHY_RxPBDlyTg2_3(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x01036A) -#define DDRPHY_RxPBDlyTg2_4(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x01046A) -#define DDRPHY_RxPBDlyTg2_5(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x01056A) -#define DDRPHY_RxPBDlyTg2_6(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x01066A) -#define DDRPHY_RxPBDlyTg2_7(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x01076A) -#define DDRPHY_RxPBDlyTg2_8(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x01086A) - -#define DDRPHY_RxPBDlyTg3_0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x01006B) -#define DDRPHY_RxPBDlyTg3_1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x01016B) -#define DDRPHY_RxPBDlyTg3_2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x01026B) -#define DDRPHY_RxPBDlyTg3_3(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x01036B) -#define DDRPHY_RxPBDlyTg3_4(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x01046B) -#define DDRPHY_RxPBDlyTg3_5(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x01056B) -#define DDRPHY_RxPBDlyTg3_6(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x01066B) -#define DDRPHY_RxPBDlyTg3_7(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x01076B) -#define DDRPHY_RxPBDlyTg3_8(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x01086B) - -#define DDRPHY_RxEnDlyTg0_0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x010080) -#define DDRPHY_RxEnDlyTg0_1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x010180) -#define DDRPHY_RxEnDlyTg0_2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x110080) -#define DDRPHY_RxEnDlyTg0_3(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x110180) -#define DDRPHY_RxEnDlyTg0_4(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x210080) -#define DDRPHY_RxEnDlyTg0_5(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x210180) -#define DDRPHY_RxEnDlyTg0_6(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x310080) -#define DDRPHY_RxEnDlyTg0_7(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x310180) - -#define DDRPHY_RxEnDlyTg1_0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x010081) -#define DDRPHY_RxEnDlyTg1_1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x010181) -#define DDRPHY_RxEnDlyTg1_2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x110081) -#define DDRPHY_RxEnDlyTg1_3(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x110181) -#define DDRPHY_RxEnDlyTg1_4(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x210081) -#define DDRPHY_RxEnDlyTg1_5(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x210181) -#define DDRPHY_RxEnDlyTg1_6(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x310081) -#define DDRPHY_RxEnDlyTg1_7(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x310181) - -#define DDRPHY_RxEnDlyTg2_0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x010082) -#define DDRPHY_RxEnDlyTg2_1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x010182) -#define DDRPHY_RxEnDlyTg2_2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x110082) -#define DDRPHY_RxEnDlyTg2_3(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x110182) -#define DDRPHY_RxEnDlyTg2_4(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x210082) -#define DDRPHY_RxEnDlyTg2_5(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x210182) -#define DDRPHY_RxEnDlyTg2_6(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x310082) -#define DDRPHY_RxEnDlyTg2_7(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x310182) - -#define DDRPHY_RxEnDlyTg3_0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x010083) -#define DDRPHY_RxEnDlyTg3_1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x010183) -#define DDRPHY_RxEnDlyTg3_2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x110083) -#define DDRPHY_RxEnDlyTg3_3(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x110183) -#define DDRPHY_RxEnDlyTg3_4(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x210083) -#define DDRPHY_RxEnDlyTg3_5(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x210183) -#define DDRPHY_RxEnDlyTg3_6(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x310083) -#define DDRPHY_RxEnDlyTg3_7(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x310183) - -#define DDRPHY_RxClkDlyTg0_0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x01008C) -#define DDRPHY_RxClkDlyTg0_1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x01018C) -#define DDRPHY_RxClkDlyTg0_2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x11008C) -#define DDRPHY_RxClkDlyTg0_3(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x11018C) -#define DDRPHY_RxClkDlyTg0_4(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x21008C) -#define DDRPHY_RxClkDlyTg0_5(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x21018C) -#define DDRPHY_RxClkDlyTg0_6(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x31008C) -#define DDRPHY_RxClkDlyTg0_7(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x31018C) - -#define DDRPHY_RxClkDlyTg1_0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x01008D) -#define DDRPHY_RxClkDlyTg1_1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x01018D) -#define DDRPHY_RxClkDlyTg1_2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x11008D) -#define DDRPHY_RxClkDlyTg1_3(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x11018D) -#define DDRPHY_RxClkDlyTg1_4(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x21008D) -#define DDRPHY_RxClkDlyTg1_5(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x21018D) -#define DDRPHY_RxClkDlyTg1_6(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x31008D) -#define DDRPHY_RxClkDlyTg1_7(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x31018D) - -#define DDRPHY_RxClkDlyTg2_0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x01008E) -#define DDRPHY_RxClkDlyTg2_1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x01018E) -#define DDRPHY_RxClkDlyTg2_2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x11008E) -#define DDRPHY_RxClkDlyTg2_3(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x11018E) -#define DDRPHY_RxClkDlyTg2_4(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x21008E) -#define DDRPHY_RxClkDlyTg2_5(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x21018E) -#define DDRPHY_RxClkDlyTg2_6(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x31008E) -#define DDRPHY_RxClkDlyTg2_7(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x31018E) - -#define DDRPHY_RxClkDlyTg3_0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x01008F) -#define DDRPHY_RxClkDlyTg3_1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x01018F) -#define DDRPHY_RxClkDlyTg3_2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x11008F) -#define DDRPHY_RxClkDlyTg3_3(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x11018F) -#define DDRPHY_RxClkDlyTg3_4(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x21008F) -#define DDRPHY_RxClkDlyTg3_5(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x21018F) -#define DDRPHY_RxClkDlyTg3_6(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x31008F) -#define DDRPHY_RxClkDlyTg3_7(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x31018F) - -#define DDRPHY_Dq0LnSel(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0100A0) -#define DDRPHY_Dq1LnSel(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0100A1) -#define DDRPHY_Dq2LnSel(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0100A2) -#define DDRPHY_Dq3LnSel(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0100A3) -#define DDRPHY_Dq4LnSel(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0100A4) -#define DDRPHY_Dq5LnSel(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0100A5) -#define DDRPHY_Dq6LnSel(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0100A6) -#define DDRPHY_Dq7LnSel(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0100A7) -#define DDRPHY_PptCtlStatic(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0100AA) -#define DDRPHY_PptCtlDyn(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0100AB) -#define DDRPHY_PptInfo(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0100AC) -#define DDRPHY_PptRxEnEvnt(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0100AD) -#define DDRPHY_PptDqsCntInvTrnTg0_0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0100AE) -#define DDRPHY_PptDqsCntInvTrnTg0_1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x1100AE) -#define DDRPHY_PptDqsCntInvTrnTg0_2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x2100AE) -#define DDRPHY_PptDqsCntInvTrnTg0_3(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x3100AE) - -#define DDRPHY_PptDqsCntInvTrnTg1_0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0100AF) -#define DDRPHY_PptDqsCntInvTrnTg1_1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x1100AF) -#define DDRPHY_PptDqsCntInvTrnTg1_2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x2100AF) -#define DDRPHY_PptDqsCntInvTrnTg1_3(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x3100AF) - -#define DDRPHY_DtsmBlankingCtrl_0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0100B1) - -#define DDRPHY_Tsm0_0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0100B2) -#define DDRPHY_Tsm0_1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0101B2) -#define DDRPHY_Tsm0_2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0102B2) -#define DDRPHY_Tsm0_3(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0103B2) -#define DDRPHY_Tsm0_4(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0104B2) -#define DDRPHY_Tsm0_5(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0105B2) -#define DDRPHY_Tsm0_6(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0106B2) -#define DDRPHY_Tsm0_7(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0107B2) -#define DDRPHY_Tsm0_8(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0108B2) - -#define DDRPHY_Tsm1_0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0100B3) -#define DDRPHY_Tsm1_1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0101B3) -#define DDRPHY_Tsm1_2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0102B3) -#define DDRPHY_Tsm1_3(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0103B3) -#define DDRPHY_Tsm1_4(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0104B3) -#define DDRPHY_Tsm1_5(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0105B3) -#define DDRPHY_Tsm1_6(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0106B3) -#define DDRPHY_Tsm1_7(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0107B3) -#define DDRPHY_Tsm1_8(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0108B3) - -#define DDRPHY_Tsm2_0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0100B4) -#define DDRPHY_Tsm2_1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0101B4) -#define DDRPHY_Tsm2_2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0102B4) -#define DDRPHY_Tsm2_3(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0103B4) -#define DDRPHY_Tsm2_4(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0104B4) -#define DDRPHY_Tsm2_5(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0105B4) -#define DDRPHY_Tsm2_6(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0106B4) -#define DDRPHY_Tsm2_7(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0107B4) -#define DDRPHY_Tsm2_8(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0108B4) - -#define DDRPHY_Tsm3_0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0100B5) -#define DDRPHY_TxChkDataSelects_0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0100B6) -#define DDRPHY_DtsmUpThldXingInd_0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0100B7) -#define DDRPHY_DtsmLoThldXingInd_0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0100B8) -#define DDRPHY_DbyteAllDtsmCtrl0_0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0100B9) -#define DDRPHY_DbyteAllDtsmCtrl1_0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0100BA) -#define DDRPHY_DbyteAllDtsmCtrl2_0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0100BB) - -#define DDRPHY_TxDqDlyTg0_00(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0100C0) -#define DDRPHY_TxDqDlyTg0_01(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0101C0) -#define DDRPHY_TxDqDlyTg0_02(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0102C0) -#define DDRPHY_TxDqDlyTg0_03(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0103C0) -#define DDRPHY_TxDqDlyTg0_04(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0104C0) -#define DDRPHY_TxDqDlyTg0_05(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0105C0) -#define DDRPHY_TxDqDlyTg0_06(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0106C0) -#define DDRPHY_TxDqDlyTg0_07(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0107C0) -#define DDRPHY_TxDqDlyTg0_08(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0108C0) -#define DDRPHY_TxDqDlyTg0_10(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x1100C0) -#define DDRPHY_TxDqDlyTg0_11(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x1101C0) -#define DDRPHY_TxDqDlyTg0_12(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x1102C0) -#define DDRPHY_TxDqDlyTg0_13(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x1103C0) -#define DDRPHY_TxDqDlyTg0_14(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x1104C0) -#define DDRPHY_TxDqDlyTg0_15(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x1105C0) -#define DDRPHY_TxDqDlyTg0_16(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x1106C0) -#define DDRPHY_TxDqDlyTg0_17(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x1107C0) -#define DDRPHY_TxDqDlyTg0_18(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x1108C0) -#define DDRPHY_TxDqDlyTg0_20(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x2100C0) -#define DDRPHY_TxDqDlyTg0_21(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x2101C0) -#define DDRPHY_TxDqDlyTg0_22(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x2102C0) -#define DDRPHY_TxDqDlyTg0_23(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x2103C0) -#define DDRPHY_TxDqDlyTg0_24(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x2104C0) -#define DDRPHY_TxDqDlyTg0_25(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x2105C0) -#define DDRPHY_TxDqDlyTg0_26(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x2106C0) -#define DDRPHY_TxDqDlyTg0_27(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x2107C0) -#define DDRPHY_TxDqDlyTg0_28(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x2108C0) -#define DDRPHY_TxDqDlyTg0_30(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x3100C0) -#define DDRPHY_TxDqDlyTg0_31(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x3101C0) -#define DDRPHY_TxDqDlyTg0_32(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x3102C0) -#define DDRPHY_TxDqDlyTg0_33(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x3103C0) -#define DDRPHY_TxDqDlyTg0_34(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x3104C0) -#define DDRPHY_TxDqDlyTg0_35(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x3105C0) -#define DDRPHY_TxDqDlyTg0_36(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x3106C0) -#define DDRPHY_TxDqDlyTg0_37(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x3107C0) -#define DDRPHY_TxDqDlyTg0_38(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x3108C0) - -#define DDRPHY_TxDqDlyTg1_00(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0100C1) -#define DDRPHY_TxDqDlyTg1_01(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0101C1) -#define DDRPHY_TxDqDlyTg1_02(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0102C1) -#define DDRPHY_TxDqDlyTg1_03(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0103C1) -#define DDRPHY_TxDqDlyTg1_04(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0104C1) -#define DDRPHY_TxDqDlyTg1_05(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0105C1) -#define DDRPHY_TxDqDlyTg1_06(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0106C1) -#define DDRPHY_TxDqDlyTg1_07(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0107C1) -#define DDRPHY_TxDqDlyTg1_08(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0108C1) -#define DDRPHY_TxDqDlyTg1_10(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x1100C1) -#define DDRPHY_TxDqDlyTg1_11(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x1101C1) -#define DDRPHY_TxDqDlyTg1_12(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x1102C1) -#define DDRPHY_TxDqDlyTg1_13(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x1103C1) -#define DDRPHY_TxDqDlyTg1_14(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x1104C1) -#define DDRPHY_TxDqDlyTg1_15(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x1105C1) -#define DDRPHY_TxDqDlyTg1_16(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x1106C1) -#define DDRPHY_TxDqDlyTg1_17(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x1107C1) -#define DDRPHY_TxDqDlyTg1_18(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x1108C1) -#define DDRPHY_TxDqDlyTg1_20(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x2100C1) -#define DDRPHY_TxDqDlyTg1_21(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x2101C1) -#define DDRPHY_TxDqDlyTg1_22(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x2102C1) -#define DDRPHY_TxDqDlyTg1_23(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x2103C1) -#define DDRPHY_TxDqDlyTg1_24(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x2104C1) -#define DDRPHY_TxDqDlyTg1_25(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x2105C1) -#define DDRPHY_TxDqDlyTg1_26(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x2106C1) -#define DDRPHY_TxDqDlyTg1_27(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x2107C1) -#define DDRPHY_TxDqDlyTg1_28(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x2108C1) -#define DDRPHY_TxDqDlyTg1_30(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x3100C1) -#define DDRPHY_TxDqDlyTg1_31(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x3101C1) -#define DDRPHY_TxDqDlyTg1_32(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x3102C1) -#define DDRPHY_TxDqDlyTg1_33(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x3103C1) -#define DDRPHY_TxDqDlyTg1_34(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x3104C1) -#define DDRPHY_TxDqDlyTg1_35(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x3105C1) -#define DDRPHY_TxDqDlyTg1_36(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x3106C1) -#define DDRPHY_TxDqDlyTg1_37(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x3107C1) -#define DDRPHY_TxDqDlyTg1_38(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x3108C1) - -#define DDRPHY_TxDqDlyTg2_00(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0100C2) -#define DDRPHY_TxDqDlyTg2_01(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0101C2) -#define DDRPHY_TxDqDlyTg2_02(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0102C2) -#define DDRPHY_TxDqDlyTg2_03(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0103C2) -#define DDRPHY_TxDqDlyTg2_04(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0104C2) -#define DDRPHY_TxDqDlyTg2_05(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0105C2) -#define DDRPHY_TxDqDlyTg2_06(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0106C2) -#define DDRPHY_TxDqDlyTg2_07(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0107C2) -#define DDRPHY_TxDqDlyTg2_08(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0108C2) -#define DDRPHY_TxDqDlyTg2_10(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x1100C2) -#define DDRPHY_TxDqDlyTg2_11(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x1101C2) -#define DDRPHY_TxDqDlyTg2_12(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x1102C2) -#define DDRPHY_TxDqDlyTg2_13(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x1103C2) -#define DDRPHY_TxDqDlyTg2_14(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x1104C2) -#define DDRPHY_TxDqDlyTg2_15(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x1105C2) -#define DDRPHY_TxDqDlyTg2_16(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x1106C2) -#define DDRPHY_TxDqDlyTg2_17(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x1107C2) -#define DDRPHY_TxDqDlyTg2_18(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x1108C2) -#define DDRPHY_TxDqDlyTg2_20(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x2100C2) -#define DDRPHY_TxDqDlyTg2_21(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x2101C2) -#define DDRPHY_TxDqDlyTg2_22(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x2102C2) -#define DDRPHY_TxDqDlyTg2_23(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x2103C2) -#define DDRPHY_TxDqDlyTg2_24(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x2104C2) -#define DDRPHY_TxDqDlyTg2_25(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x2105C2) -#define DDRPHY_TxDqDlyTg2_26(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x2106C2) -#define DDRPHY_TxDqDlyTg2_27(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x2107C2) -#define DDRPHY_TxDqDlyTg2_28(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x2108C2) -#define DDRPHY_TxDqDlyTg2_30(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x3100C2) -#define DDRPHY_TxDqDlyTg2_31(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x3101C2) -#define DDRPHY_TxDqDlyTg2_32(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x3102C2) -#define DDRPHY_TxDqDlyTg2_33(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x3103C2) -#define DDRPHY_TxDqDlyTg2_34(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x3104C2) -#define DDRPHY_TxDqDlyTg2_35(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x3105C2) -#define DDRPHY_TxDqDlyTg2_36(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x3106C2) -#define DDRPHY_TxDqDlyTg2_37(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x3107C2) -#define DDRPHY_TxDqDlyTg2_38(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x3108C2) - -#define DDRPHY_TxDqDlyTg3_00(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0100C3) -#define DDRPHY_TxDqDlyTg3_01(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0101C3) -#define DDRPHY_TxDqDlyTg3_02(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0102C3) -#define DDRPHY_TxDqDlyTg3_03(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0103C3) -#define DDRPHY_TxDqDlyTg3_04(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0104C3) -#define DDRPHY_TxDqDlyTg3_05(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0105C3) -#define DDRPHY_TxDqDlyTg3_06(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0106C3) -#define DDRPHY_TxDqDlyTg3_07(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0107C3) -#define DDRPHY_TxDqDlyTg3_08(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0108C3) -#define DDRPHY_TxDqDlyTg3_10(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x1100C3) -#define DDRPHY_TxDqDlyTg3_11(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x1101C3) -#define DDRPHY_TxDqDlyTg3_12(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x1102C3) -#define DDRPHY_TxDqDlyTg3_13(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x1103C3) -#define DDRPHY_TxDqDlyTg3_14(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x1104C3) -#define DDRPHY_TxDqDlyTg3_15(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x1105C3) -#define DDRPHY_TxDqDlyTg3_16(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x1106C3) -#define DDRPHY_TxDqDlyTg3_17(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x1107C3) -#define DDRPHY_TxDqDlyTg3_18(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x1108C3) -#define DDRPHY_TxDqDlyTg3_20(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x2100C3) -#define DDRPHY_TxDqDlyTg3_21(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x2101C3) -#define DDRPHY_TxDqDlyTg3_22(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x2102C3) -#define DDRPHY_TxDqDlyTg3_23(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x2103C3) -#define DDRPHY_TxDqDlyTg3_24(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x2104C3) -#define DDRPHY_TxDqDlyTg3_25(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x2105C3) -#define DDRPHY_TxDqDlyTg3_26(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x2106C3) -#define DDRPHY_TxDqDlyTg3_27(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x2107C3) -#define DDRPHY_TxDqDlyTg3_28(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x2108C3) -#define DDRPHY_TxDqDlyTg3_30(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x3100C3) -#define DDRPHY_TxDqDlyTg3_31(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x3101C3) -#define DDRPHY_TxDqDlyTg3_32(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x3102C3) -#define DDRPHY_TxDqDlyTg3_33(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x3103C3) -#define DDRPHY_TxDqDlyTg3_34(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x3104C3) -#define DDRPHY_TxDqDlyTg3_35(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x3105C3) -#define DDRPHY_TxDqDlyTg3_36(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x3106C3) -#define DDRPHY_TxDqDlyTg3_37(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x3107C3) -#define DDRPHY_TxDqDlyTg3_38(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x3108C3) - -#define DDRPHY_TxDqsDlyTg0_0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0100D0) -#define DDRPHY_TxDqsDlyTg0_1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0101D0) -#define DDRPHY_TxDqsDlyTg0_2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x1100D0) -#define DDRPHY_TxDqsDlyTg0_3(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x1101D0) -#define DDRPHY_TxDqsDlyTg0_4(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x2100D0) -#define DDRPHY_TxDqsDlyTg0_5(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x2101D0) -#define DDRPHY_TxDqsDlyTg0_6(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x3100D0) -#define DDRPHY_TxDqsDlyTg0_7(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x3101D0) - -#define DDRPHY_TxDqsDlyTg1_0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0100D1) -#define DDRPHY_TxDqsDlyTg1_1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0101D1) -#define DDRPHY_TxDqsDlyTg1_2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x1100D1) -#define DDRPHY_TxDqsDlyTg1_3(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x1101D1) -#define DDRPHY_TxDqsDlyTg1_4(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x2100D1) -#define DDRPHY_TxDqsDlyTg1_5(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x2101D1) -#define DDRPHY_TxDqsDlyTg1_6(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x3100D1) -#define DDRPHY_TxDqsDlyTg1_7(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x3101D1) - -#define DDRPHY_TxDqsDlyTg2_0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0100D2) -#define DDRPHY_TxDqsDlyTg2_1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0101D2) -#define DDRPHY_TxDqsDlyTg2_2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x1100D2) -#define DDRPHY_TxDqsDlyTg2_3(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x1101D2) -#define DDRPHY_TxDqsDlyTg2_4(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x2100D2) -#define DDRPHY_TxDqsDlyTg2_5(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x2101D2) -#define DDRPHY_TxDqsDlyTg2_6(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x3100D2) -#define DDRPHY_TxDqsDlyTg2_7(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x3101D2) - -#define DDRPHY_TxDqsDlyTg3_0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0100D3) -#define DDRPHY_TxDqsDlyTg3_1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0101D3) -#define DDRPHY_TxDqsDlyTg3_2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x1100D3) -#define DDRPHY_TxDqsDlyTg3_3(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x1101D3) -#define DDRPHY_TxDqsDlyTg3_4(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x2100D3) -#define DDRPHY_TxDqsDlyTg3_5(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x2101D3) -#define DDRPHY_TxDqsDlyTg3_6(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x3100D3) -#define DDRPHY_TxDqsDlyTg3_7(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x3101D3) - -#define DDRPHY_DctShadowRegs(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0C0004) -#define DDRPHY_DctWriteOnlyShadow(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0C0030) -#define DDRPHY_UctWriteOnly(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0C0032) -#define DDRPHY_UctWriteProt(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0C0033) -#define DDRPHY_UctDatWriteOnly(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0C0034) -#define DDRPHY_UctDatWriteProt(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0C0035) -#define DDRPHY_UctlErr(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0C0036) -#define DDRPHY_UcclkHclkEnables(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0C0080) -#define DDRPHY_CurPstate0b(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0C0081) -#define DDRPHY_ClrWakeupSticky(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0C0095) -#define DDRPHY_WakeupMask(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0C0096) -#define DDRPHY_CUSTPUBREV(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0C00ED) -#define DDRPHY_PUBREV(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0C00EE) - -#define DDRPHY_PreSequenceReg0b0s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090000) -#define DDRPHY_SequenceReg0b71s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090100) -#define DDRPHY_PreSequenceReg0b0s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090001) - -#define DDRPHY_Seq0BGPR1_0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090201) -#define DDRPHY_Seq0BGPR1_1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x190201) -#define DDRPHY_Seq0BGPR1_2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x290201) -#define DDRPHY_Seq0BGPR1_3(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x390201) - -#define DDRPHY_SequenceReg0b72s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090101) -#define DDRPHY_PreSequenceReg0b0s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090002) - -#define DDRPHY_Seq0BGPR2_0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090202) -#define DDRPHY_Seq0BGPR2_1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x190202) -#define DDRPHY_Seq0BGPR2_2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x290202) -#define DDRPHY_Seq0BGPR2_3(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x390202) - -#define DDRPHY_SequenceReg0b72s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090102) -#define DDRPHY_PreSequenceReg0b1s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090003) - -#define DDRPHY_Seq0BGPR3_0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090203) -#define DDRPHY_Seq0BGPR3_1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x190203) -#define DDRPHY_Seq0BGPR3_2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x290203) -#define DDRPHY_Seq0BGPR3_3(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x390203) - -#define DDRPHY_SequenceReg0b72s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090103) -#define DDRPHY_PreSequenceReg0b1s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090004) - -#define DDRPHY_Seq0BGPR4_0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090204) -#define DDRPHY_Seq0BGPR4_1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x190204) -#define DDRPHY_Seq0BGPR4_2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x290204) -#define DDRPHY_Seq0BGPR4_3(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x390204) - -#define DDRPHY_SequenceReg0b73s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090104) -#define DDRPHY_PreSequenceReg0b1s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090005) - -#define DDRPHY_Seq0BGPR5_0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090205) -#define DDRPHY_Seq0BGPR5_1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x190205) -#define DDRPHY_Seq0BGPR5_2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x290205) -#define DDRPHY_Seq0BGPR5_3(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x390205) - -#define DDRPHY_SequenceReg0b73s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090105) -#define DDRPHY_PostSequenceReg0b0s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090006) - -#define DDRPHY_Seq0BGPR6_0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090206) -#define DDRPHY_Seq0BGPR6_1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x190206) -#define DDRPHY_Seq0BGPR6_2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x290206) -#define DDRPHY_Seq0BGPR6_3(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x390206) - -#define DDRPHY_SequenceReg0b73s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090106) -#define DDRPHY_PostSequenceReg0b0s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090007) - -#define DDRPHY_Seq0BGPR7_0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090207) -#define DDRPHY_Seq0BGPR7_1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x190207) -#define DDRPHY_Seq0BGPR7_2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x290207) -#define DDRPHY_Seq0BGPR7_3(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x390207) - -#define DDRPHY_SequenceReg0b74s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090107) -#define DDRPHY_PostSequenceReg0b0s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090008) - -#define DDRPHY_Seq0BGPR8_0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090208) -#define DDRPHY_Seq0BGPR8_1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x190208) -#define DDRPHY_Seq0BGPR8_2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x290208) -#define DDRPHY_Seq0BGPR8_3(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x390208) - -#define DDRPHY_SequenceReg0b74s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090108) -#define DDRPHY_PostSequenceReg0b1s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090009) -#define DDRPHY_SequenceReg0b74s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090109) -#define DDRPHY_PostSequenceReg0b1s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x09000A) -#define DDRPHY_SequenceReg0b75s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x09010A) -#define DDRPHY_PostSequenceReg0b1s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x09000B) -#define DDRPHY_SequenceReg0b75s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x09010B) - -#define DDRPHY_Seq0BDisableFlag0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x09000C) -#define DDRPHY_SequenceReg0b75s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x09010C) -#define DDRPHY_Seq0BDisableFlag1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x09000D) -#define DDRPHY_SequenceReg0b76s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x09010D) -#define DDRPHY_Seq0BDisableFlag2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x09000E) -#define DDRPHY_SequenceReg0b76s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x09010E) -#define DDRPHY_Seq0BDisableFlag3(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x09000F) -#define DDRPHY_SequenceReg0b76s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x09010F) -#define DDRPHY_Seq0BDisableFlag4(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090010) -#define DDRPHY_SequenceReg0b77s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090110) -#define DDRPHY_Seq0BDisableFlag5(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090011) -#define DDRPHY_SequenceReg0b77s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090111) -#define DDRPHY_Seq0BDisableFlag6(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090012) -#define DDRPHY_SequenceReg0b77s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090112) -#define DDRPHY_Seq0BDisableFlag7(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090013) -#define DDRPHY_SequenceReg0b78s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090113) -#define DDRPHY_SequenceReg0b78s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090114) -#define DDRPHY_SequenceReg0b78s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090115) -#define DDRPHY_SequenceReg0b79s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090116) -#define DDRPHY_StartVector0b0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090017) -#define DDRPHY_SequenceReg0b79s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090117) -#define DDRPHY_StartVector0b1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090018) -#define DDRPHY_SequenceReg0b79s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090118) - -#define DDRPHY_StartVector0b2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090019) -#define DDRPHY_SequenceReg0b80s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090119) -#define DDRPHY_StartVector0b3(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x09001A) -#define DDRPHY_SequenceReg0b80s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x09011A) -#define DDRPHY_StartVector0b4(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x09001B) -#define DDRPHY_SequenceReg0b80s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x09011B) -#define DDRPHY_StartVector0b5(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x09001C) -#define DDRPHY_SequenceReg0b81s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x09011C) -#define DDRPHY_StartVector0b6(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x09001D) -#define DDRPHY_SequenceReg0b81s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x09011D) -#define DDRPHY_StartVector0b7(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x09001E) -#define DDRPHY_SequenceReg0b81s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x09011E) -#define DDRPHY_StartVector0b8(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x09001F) -#define DDRPHY_SequenceReg0b82s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x09011F) -#define DDRPHY_StartVector0b9(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090020) -#define DDRPHY_SequenceReg0b82s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090120) -#define DDRPHY_StartVector0b10(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090021) -#define DDRPHY_SequenceReg0b82s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090121) -#define DDRPHY_StartVector0b11(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090022) -#define DDRPHY_SequenceReg0b83s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090122) -#define DDRPHY_StartVector0b12(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090023) -#define DDRPHY_SequenceReg0b83s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090123) -#define DDRPHY_StartVector0b13(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090024) -#define DDRPHY_SequenceReg0b83s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090124) -#define DDRPHY_StartVector0b14(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090025) -#define DDRPHY_SequenceReg0b84s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090125) -#define DDRPHY_StartVector0b15(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090026) -#define DDRPHY_SequenceReg0b84s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090126) - -#define DDRPHY_Seq0bWaitCondSel(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090027) -#define DDRPHY_SequenceReg0b84s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090127) -#define DDRPHY_PhyInLP3(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090028) - -#define DDRPHY_SequenceReg0b85s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090128) -#define DDRPHY_SequenceReg0b0s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090029) -#define DDRPHY_SequenceReg0b85s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090129) -#define DDRPHY_SequenceReg0b0s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x09002a) -#define DDRPHY_SequenceReg0b85s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x09012a) -#define DDRPHY_SequenceReg0b0s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x09002b) -#define DDRPHY_SequenceReg0b86s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x09012b) -#define DDRPHY_SequenceReg0b1s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x09002c) -#define DDRPHY_SequenceReg0b86s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x09012c) -#define DDRPHY_SequenceReg0b1s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x09002d) -#define DDRPHY_SequenceReg0b86s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x09012d) -#define DDRPHY_SequenceReg0b1s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x09002e) -#define DDRPHY_SequenceReg0b87s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x09012e) -#define DDRPHY_SequenceReg0b2s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x09002f) -#define DDRPHY_SequenceReg0b87s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x09012f) -#define DDRPHY_SequenceReg0b2s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090030) -#define DDRPHY_SequenceReg0b87s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090130) -#define DDRPHY_SequenceReg0b2s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090031) -#define DDRPHY_SequenceReg0b88s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090131) -#define DDRPHY_SequenceReg0b3s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090032) -#define DDRPHY_SequenceReg0b88s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090132) -#define DDRPHY_SequenceReg0b3s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090033) -#define DDRPHY_SequenceReg0b88s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090133) -#define DDRPHY_SequenceReg0b3s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090034) -#define DDRPHY_SequenceReg0b89s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090134) -#define DDRPHY_SequenceReg0b4s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090035) -#define DDRPHY_SequenceReg0b89s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090135) -#define DDRPHY_SequenceReg0b4s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090036) -#define DDRPHY_SequenceReg0b89s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090136) -#define DDRPHY_SequenceReg0b4s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090037) -#define DDRPHY_SequenceReg0b90s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090137) -#define DDRPHY_SequenceReg0b5s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090038) -#define DDRPHY_SequenceReg0b90s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090138) -#define DDRPHY_SequenceReg0b5s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090039) -#define DDRPHY_SequenceReg0b90s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090139) -#define DDRPHY_SequenceReg0b5s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x09003a) -#define DDRPHY_SequenceReg0b91s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x09013a) -#define DDRPHY_SequenceReg0b6s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x09003b) -#define DDRPHY_SequenceReg0b91s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x09013b) -#define DDRPHY_SequenceReg0b6s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x09003c) -#define DDRPHY_SequenceReg0b91s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x09013c) -#define DDRPHY_SequenceReg0b6s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x09003d) -#define DDRPHY_SequenceReg0b92s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x09013d) -#define DDRPHY_SequenceReg0b7s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x09003e) -#define DDRPHY_SequenceReg0b92s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x09013e) -#define DDRPHY_SequenceReg0b7s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x09003f) -#define DDRPHY_SequenceReg0b92s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x09013f) -#define DDRPHY_SequenceReg0b7s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090040) -#define DDRPHY_SequenceReg0b93s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090140) -#define DDRPHY_SequenceReg0b8s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090041) -#define DDRPHY_SequenceReg0b93s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090141) -#define DDRPHY_SequenceReg0b8s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090042) -#define DDRPHY_SequenceReg0b93s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090142) -#define DDRPHY_SequenceReg0b8s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090043) -#define DDRPHY_SequenceReg0b94s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090143) -#define DDRPHY_SequenceReg0b9s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090044) -#define DDRPHY_SequenceReg0b94s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090144) -#define DDRPHY_SequenceReg0b9s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090045) -#define DDRPHY_SequenceReg0b94s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090145) -#define DDRPHY_SequenceReg0b9s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090046) -#define DDRPHY_SequenceReg0b95s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090146) -#define DDRPHY_SequenceReg0b10s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090047) -#define DDRPHY_SequenceReg0b95s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090147) -#define DDRPHY_SequenceReg0b10s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090048) -#define DDRPHY_SequenceReg0b95s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090148) -#define DDRPHY_SequenceReg0b10s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090049) -#define DDRPHY_SequenceReg0b96s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090149) -#define DDRPHY_SequenceReg0b11s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x09004a) -#define DDRPHY_SequenceReg0b96s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x09014a) -#define DDRPHY_SequenceReg0b11s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x09004b) -#define DDRPHY_SequenceReg0b96s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x09014b) -#define DDRPHY_SequenceReg0b11s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x09004c) -#define DDRPHY_SequenceReg0b97s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x09014c) -#define DDRPHY_SequenceReg0b12s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x09004d) -#define DDRPHY_SequenceReg0b97s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x09014d) -#define DDRPHY_SequenceReg0b12s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x09004e) -#define DDRPHY_SequenceReg0b97s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x09014e) -#define DDRPHY_SequenceReg0b12s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x09004f) -#define DDRPHY_SequenceReg0b98s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x09014f) -#define DDRPHY_SequenceReg0b13s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090050) -#define DDRPHY_SequenceReg0b98s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090150) -#define DDRPHY_SequenceReg0b13s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090051) -#define DDRPHY_SequenceReg0b98s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090151) -#define DDRPHY_SequenceReg0b13s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090052) -#define DDRPHY_SequenceReg0b99s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090152) -#define DDRPHY_SequenceReg0b14s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090053) -#define DDRPHY_SequenceReg0b99s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090153) -#define DDRPHY_SequenceReg0b14s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090054) -#define DDRPHY_SequenceReg0b99s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090154) -#define DDRPHY_SequenceReg0b14s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090055) -#define DDRPHY_SequenceReg0b100s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090155) -#define DDRPHY_SequenceReg0b15s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090056) -#define DDRPHY_SequenceReg0b100s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090156) -#define DDRPHY_SequenceReg0b15s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090057) -#define DDRPHY_SequenceReg0b100s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090157) -#define DDRPHY_SequenceReg0b15s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090058) -#define DDRPHY_SequenceReg0b101s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090158) -#define DDRPHY_SequenceReg0b16s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090059) -#define DDRPHY_SequenceReg0b101s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090159) -#define DDRPHY_SequenceReg0b16s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x09005a) -#define DDRPHY_SequenceReg0b101s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x09015a) -#define DDRPHY_SequenceReg0b16s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x09005b) -#define DDRPHY_SequenceReg0b102s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x09015b) -#define DDRPHY_SequenceReg0b17s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x09005c) -#define DDRPHY_SequenceReg0b102s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x09015c) -#define DDRPHY_SequenceReg0b17s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x09005d) -#define DDRPHY_SequenceReg0b102s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x09015d) -#define DDRPHY_SequenceReg0b17s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x09005e) -#define DDRPHY_SequenceReg0b103s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x09015e) -#define DDRPHY_SequenceReg0b18s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x09005f) -#define DDRPHY_SequenceReg0b103s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x09015f) -#define DDRPHY_SequenceReg0b18s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090060) -#define DDRPHY_SequenceReg0b103s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090160) -#define DDRPHY_SequenceReg0b18s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090061) -#define DDRPHY_SequenceReg0b104s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090161) -#define DDRPHY_SequenceReg0b19s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090062) -#define DDRPHY_SequenceReg0b104s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090162) -#define DDRPHY_SequenceReg0b19s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090063) -#define DDRPHY_SequenceReg0b104s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090163) -#define DDRPHY_SequenceReg0b19s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090064) -#define DDRPHY_SequenceReg0b105s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090164) -#define DDRPHY_SequenceReg0b20s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090065) -#define DDRPHY_SequenceReg0b105s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090165) -#define DDRPHY_SequenceReg0b20s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090066) -#define DDRPHY_SequenceReg0b105s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090166) -#define DDRPHY_SequenceReg0b20s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090067) -#define DDRPHY_SequenceReg0b106s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090167) -#define DDRPHY_SequenceReg0b21s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090068) -#define DDRPHY_SequenceReg0b106s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090168) -#define DDRPHY_SequenceReg0b21s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090069) -#define DDRPHY_SequenceReg0b106s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090169) -#define DDRPHY_SequenceReg0b21s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x09006a) -#define DDRPHY_SequenceReg0b107s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x09016a) -#define DDRPHY_SequenceReg0b22s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x09006b) -#define DDRPHY_SequenceReg0b107s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x09016b) -#define DDRPHY_SequenceReg0b22s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x09006c) -#define DDRPHY_SequenceReg0b107s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x09016c) -#define DDRPHY_SequenceReg0b22s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x09006d) -#define DDRPHY_SequenceReg0b108s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x09016d) -#define DDRPHY_SequenceReg0b23s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x09006e) -#define DDRPHY_SequenceReg0b108s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x09016e) -#define DDRPHY_SequenceReg0b23s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x09006f) -#define DDRPHY_SequenceReg0b108s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x09016f) -#define DDRPHY_SequenceReg0b23s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090070) -#define DDRPHY_SequenceReg0b109s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090170) -#define DDRPHY_SequenceReg0b24s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090071) -#define DDRPHY_SequenceReg0b109s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090171) -#define DDRPHY_SequenceReg0b24s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090072) -#define DDRPHY_SequenceReg0b109s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090172) -#define DDRPHY_SequenceReg0b24s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090073) -#define DDRPHY_SequenceReg0b110s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090173) -#define DDRPHY_SequenceReg0b25s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090074) -#define DDRPHY_SequenceReg0b110s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090174) -#define DDRPHY_SequenceReg0b25s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090075) -#define DDRPHY_SequenceReg0b110s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090175) -#define DDRPHY_SequenceReg0b25s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090076) -#define DDRPHY_SequenceReg0b111s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090176) -#define DDRPHY_SequenceReg0b26s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090077) -#define DDRPHY_SequenceReg0b111s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090177) -#define DDRPHY_SequenceReg0b26s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090078) -#define DDRPHY_SequenceReg0b111s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090178) -#define DDRPHY_SequenceReg0b26s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090079) -#define DDRPHY_SequenceReg0b112s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090179) -#define DDRPHY_SequenceReg0b27s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x09007a) -#define DDRPHY_SequenceReg0b112s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x09017a) -#define DDRPHY_SequenceReg0b27s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x09007b) -#define DDRPHY_SequenceReg0b112s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x09017b) -#define DDRPHY_SequenceReg0b27s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x09007c) -#define DDRPHY_SequenceReg0b113s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x09017c) -#define DDRPHY_SequenceReg0b28s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x09007d) -#define DDRPHY_SequenceReg0b113s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x09017d) -#define DDRPHY_SequenceReg0b28s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x09007e) -#define DDRPHY_SequenceReg0b113s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x09017e) -#define DDRPHY_SequenceReg0b28s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x09007f) -#define DDRPHY_SequenceReg0b114s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x09017f) -#define DDRPHY_SequenceReg0b29s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090080) -#define DDRPHY_SequenceReg0b114s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090180) -#define DDRPHY_SequenceReg0b29s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090081) -#define DDRPHY_SequenceReg0b114s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090181) -#define DDRPHY_SequenceReg0b29s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090082) -#define DDRPHY_SequenceReg0b115s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090182) -#define DDRPHY_SequenceReg0b30s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090083) -#define DDRPHY_SequenceReg0b115s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090183) -#define DDRPHY_SequenceReg0b30s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090084) -#define DDRPHY_SequenceReg0b115s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090184) -#define DDRPHY_SequenceReg0b30s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090085) -#define DDRPHY_SequenceReg0b116s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090185) -#define DDRPHY_SequenceReg0b31s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090086) -#define DDRPHY_SequenceReg0b116s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090186) -#define DDRPHY_SequenceReg0b31s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090087) -#define DDRPHY_SequenceReg0b116s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090187) -#define DDRPHY_SequenceReg0b31s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090088) -#define DDRPHY_SequenceReg0b117s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090188) -#define DDRPHY_SequenceReg0b32s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090089) -#define DDRPHY_SequenceReg0b117s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090189) -#define DDRPHY_SequenceReg0b32s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x09008a) -#define DDRPHY_SequenceReg0b117s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x09018a) -#define DDRPHY_SequenceReg0b32s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x09008b) -#define DDRPHY_SequenceReg0b118s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x09018b) -#define DDRPHY_SequenceReg0b33s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x09008c) -#define DDRPHY_SequenceReg0b118s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x09018c) -#define DDRPHY_SequenceReg0b33s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x09008d) -#define DDRPHY_SequenceReg0b118s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x09018d) -#define DDRPHY_SequenceReg0b33s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x09008e) -#define DDRPHY_SequenceReg0b119s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x09018e) -#define DDRPHY_SequenceReg0b34s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x09008f) -#define DDRPHY_SequenceReg0b119s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x09018f) -#define DDRPHY_SequenceReg0b34s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090090) -#define DDRPHY_SequenceReg0b119s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090190) -#define DDRPHY_SequenceReg0b34s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090091) -#define DDRPHY_SequenceReg0b120s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090191) -#define DDRPHY_SequenceReg0b35s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090092) -#define DDRPHY_SequenceReg0b120s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090192) -#define DDRPHY_SequenceReg0b35s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090093) -#define DDRPHY_SequenceReg0b120s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090193) -#define DDRPHY_SequenceReg0b35s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090094) -#define DDRPHY_SequenceReg0b121s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090194) -#define DDRPHY_SequenceReg0b36s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090095) -#define DDRPHY_SequenceReg0b121s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090195) -#define DDRPHY_SequenceReg0b36s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090096) -#define DDRPHY_SequenceReg0b121s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090196) -#define DDRPHY_SequenceReg0b36s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090097) -#define DDRPHY_SequenceReg0b37s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090098) -#define DDRPHY_SequenceReg0b37s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090099) -#define DDRPHY_SequenceReg0b37s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x09009a) -#define DDRPHY_SequenceReg0b38s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x09009b) -#define DDRPHY_SequenceReg0b38s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x09009c) -#define DDRPHY_SequenceReg0b38s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x09009d) -#define DDRPHY_SequenceReg0b39s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x09009e) -#define DDRPHY_SequenceReg0b39s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x09009f) -#define DDRPHY_SequenceReg0b39s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0900a0) -#define DDRPHY_SequenceReg0b40s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0900a1) -#define DDRPHY_SequenceReg0b40s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0900a2) -#define DDRPHY_SequenceReg0b40s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0900a3) -#define DDRPHY_SequenceReg0b41s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0900a4) -#define DDRPHY_SequenceReg0b41s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0900a5) -#define DDRPHY_SequenceReg0b41s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0900a6) -#define DDRPHY_SequenceReg0b42s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0900a7) -#define DDRPHY_SequenceReg0b42s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0900a8) -#define DDRPHY_SequenceReg0b42s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0900a9) -#define DDRPHY_SequenceReg0b43s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0900aa) -#define DDRPHY_SequenceReg0b43s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0900ab) -#define DDRPHY_SequenceReg0b43s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0900ac) -#define DDRPHY_SequenceReg0b44s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0900ad) -#define DDRPHY_SequenceReg0b44s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0900ae) -#define DDRPHY_SequenceReg0b44s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0900af) -#define DDRPHY_SequenceReg0b45s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0900b0) -#define DDRPHY_SequenceReg0b45s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0900b1) -#define DDRPHY_SequenceReg0b45s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0900b2) -#define DDRPHY_SequenceReg0b46s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0900b3) -#define DDRPHY_SequenceReg0b46s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0900b4) -#define DDRPHY_SequenceReg0b46s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0900b5) -#define DDRPHY_SequenceReg0b47s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0900b6) -#define DDRPHY_SequenceReg0b47s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0900b7) -#define DDRPHY_SequenceReg0b47s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0900b8) -#define DDRPHY_SequenceReg0b48s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0900b9) -#define DDRPHY_SequenceReg0b48s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0900ba) -#define DDRPHY_SequenceReg0b48s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0900bb) -#define DDRPHY_SequenceReg0b49s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0900bc) -#define DDRPHY_SequenceReg0b49s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0900bd) -#define DDRPHY_SequenceReg0b49s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0900be) -#define DDRPHY_SequenceReg0b50s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0900bf) -#define DDRPHY_SequenceReg0b50s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0900c0) -#define DDRPHY_SequenceReg0b50s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0900c1) -#define DDRPHY_SequenceReg0b51s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0900c2) -#define DDRPHY_SequenceReg0b51s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0900c3) -#define DDRPHY_SequenceReg0b51s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0900c4) -#define DDRPHY_SequenceReg0b52s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0900c5) -#define DDRPHY_SequenceReg0b52s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0900c6) -#define DDRPHY_SequenceReg0b52s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0900c7) -#define DDRPHY_SequenceReg0b53s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0900c8) -#define DDRPHY_SequenceReg0b53s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0900c9) -#define DDRPHY_SequenceReg0b53s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0900ca) -#define DDRPHY_SequenceReg0b54s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0900cb) -#define DDRPHY_SequenceReg0b54s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0900cc) -#define DDRPHY_SequenceReg0b54s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0900cd) -#define DDRPHY_SequenceReg0b55s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0900ce) -#define DDRPHY_SequenceReg0b55s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0900cf) -#define DDRPHY_SequenceReg0b55s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0900d0) -#define DDRPHY_SequenceReg0b56s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0900d1) -#define DDRPHY_SequenceReg0b56s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0900d2) -#define DDRPHY_SequenceReg0b56s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0900d3) -#define DDRPHY_SequenceReg0b57s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0900d4) -#define DDRPHY_SequenceReg0b57s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0900d5) -#define DDRPHY_SequenceReg0b57s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0900d6) -#define DDRPHY_SequenceReg0b58s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0900d7) -#define DDRPHY_SequenceReg0b58s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0900d8) -#define DDRPHY_SequenceReg0b58s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0900d9) -#define DDRPHY_SequenceReg0b59s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0900da) -#define DDRPHY_SequenceReg0b59s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0900db) -#define DDRPHY_SequenceReg0b59s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0900dc) -#define DDRPHY_SequenceReg0b60s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0900dd) -#define DDRPHY_SequenceReg0b60s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0900de) -#define DDRPHY_SequenceReg0b60s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0900df) -#define DDRPHY_SequenceReg0b61s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0900e0) -#define DDRPHY_SequenceReg0b61s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0900e1) -#define DDRPHY_SequenceReg0b61s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0900e2) -#define DDRPHY_SequenceReg0b62s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0900e3) -#define DDRPHY_SequenceReg0b62s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0900e4) -#define DDRPHY_SequenceReg0b62s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0900e5) -#define DDRPHY_SequenceReg0b63s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0900e6) -#define DDRPHY_SequenceReg0b63s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0900e7) -#define DDRPHY_SequenceReg0b63s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0900e8) -#define DDRPHY_SequenceReg0b64s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0900e9) -#define DDRPHY_SequenceReg0b64s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0900ea) -#define DDRPHY_SequenceReg0b64s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0900eb) -#define DDRPHY_SequenceReg0b65s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0900ec) -#define DDRPHY_SequenceReg0b65s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0900ed) -#define DDRPHY_SequenceReg0b65s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0900ee) -#define DDRPHY_SequenceReg0b66s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0900ef) -#define DDRPHY_SequenceReg0b66s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0900f0) -#define DDRPHY_SequenceReg0b66s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0900f1) -#define DDRPHY_SequenceReg0b67s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0900f2) -#define DDRPHY_SequenceReg0b67s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0900f3) -#define DDRPHY_SequenceReg0b67s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0900f4) -#define DDRPHY_SequenceReg0b68s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0900f5) -#define DDRPHY_SequenceReg0b68s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0900f6) -#define DDRPHY_SequenceReg0b68s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0900f7) -#define DDRPHY_SequenceReg0b69s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0900f8) -#define DDRPHY_SequenceReg0b69s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0900f9) -#define DDRPHY_SequenceReg0b69s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0900fa) -#define DDRPHY_SequenceReg0b70s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0900fb) -#define DDRPHY_SequenceReg0b70s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0900fc) -#define DDRPHY_SequenceReg0b70s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0900fd) -#define DDRPHY_SequenceReg0b71s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0900fe) -#define DDRPHY_SequenceReg0b71s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0900ff) - -#define DDRPHY_RxFifoInit(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x020000) -#define DDRPHY_MapCAA0toDfi(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x020100) -#define DDRPHY_ForceClkDisable(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x020001) -#define DDRPHY_MapCAA1toDfi(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x020101) -#define DDRPHY_ClockingCtrl(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x020002) -#define DDRPHY_MapCAA2toDfi(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x020102) -#define DDRPHY_MapCAA3toDfi(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x020103) -#define DDRPHY_MapCAA4toDfi(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x020104) -#define DDRPHY_MapCAA5toDfi(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x020105) -#define DDRPHY_MapCAA6toDfi(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x020106) -#define DDRPHY_TestBumpCntrl1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x020007) -#define DDRPHY_MapCAA7toDfi(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x020107) - -#define DDRPHY_CalUclkInfo_0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x020008) -#define DDRPHY_CalUclkInfo_1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x120008) -#define DDRPHY_CalUclkInfo_2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x220008) -#define DDRPHY_CalUclkInfo_3(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x320008) - -#define DDRPHY_MapCAA8toDfi(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x020108) -#define DDRPHY_MapCAA9toDfi(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x020109) -#define DDRPHY_TestBumpCntrl(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x02000A) - -#define DDRPHY_Seq0BDLY0_0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x02000B) -#define DDRPHY_Seq0BDLY0_1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x12000B) -#define DDRPHY_Seq0BDLY0_2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x22000B) -#define DDRPHY_Seq0BDLY0_3(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x32000B) - -#define DDRPHY_Seq0BDLY1_0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x02000C) -#define DDRPHY_Seq0BDLY1_1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x12000C) -#define DDRPHY_Seq0BDLY1_2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x22000C) -#define DDRPHY_Seq0BDLY1_3(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x32000C) - -#define DDRPHY_Seq0BDLY2_0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x02000D) -#define DDRPHY_Seq0BDLY2_1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x12000D) -#define DDRPHY_Seq0BDLY2_2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x22000D) -#define DDRPHY_Seq0BDLY2_3(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x32000D) - -#define DDRPHY_Seq0BDLY3_0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x02000E) -#define DDRPHY_Seq0BDLY3_1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x12000E) -#define DDRPHY_Seq0BDLY3_2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x22000E) -#define DDRPHY_Seq0BDLY3_3(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x32000E) - -#define DDRPHY_PhyAlertStatus(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x02000F) - -#define DDRPHY_PPTTrainSetup_0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x020010) -#define DDRPHY_PPTTrainSetup_1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x120010) -#define DDRPHY_PPTTrainSetup_2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x220010) -#define DDRPHY_PPTTrainSetup_3(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x320010) - -#define DDRPHY_MapCAB0toDfi(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x020110) - -#define DDRPHY_PPTTrainSetup2_0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x020011) -#define DDRPHY_PPTTrainSetup2_1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x120011) -#define DDRPHY_PPTTrainSetup2_2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x220011) -#define DDRPHY_PPTTrainSetup2_3(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x320011) - -#define DDRPHY_MapCAB1toDfi(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x020111) -#define DDRPHY_ATestMode(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x020012) -#define DDRPHY_MapCAB2toDfi(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x020112) - -#define DDRPHY_MapCAB3toDfi(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x020113) -#define DDRPHY_TxCalBinP(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x020014) -#define DDRPHY_MapCAB4toDfi(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x020114) -#define DDRPHY_TxCalBinN(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x020015) -#define DDRPHY_MapCAB5toDfi(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x020115) -#define DDRPHY_TxCalPOvr(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x020016) -#define DDRPHY_MapCAB6toDfi(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x020116) -#define DDRPHY_TxCalNOvr(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x020017) -#define DDRPHY_MapCAB7toDfi(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x020117) -#define DDRPHY_DfiMode(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x020018) -#define DDRPHY_MapCAB8toDfi(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x020118) - -#define DDRPHY_TristateModeCA_0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x020019) -#define DDRPHY_TristateModeCA_1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x120019) -#define DDRPHY_TristateModeCA_2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x220019) -#define DDRPHY_TristateModeCA_3(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x320019) - -#define DDRPHY_MapCAB9toDfi(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x020119) - -#define DDRPHY_MtestMuxSel(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x02001A) -#define DDRPHY_MtestPgmInfo(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x02001B) -#define DDRPHY_DynPwrDnUp(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x02001C) -#define DDRPHY_PMIEnable(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x02001D) -#define DDRPHY_PhyTID(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x02001E) - -#define DDRPHY_HwtMRL_0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x020020) -#define DDRPHY_HwtMRL_1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x120020) -#define DDRPHY_HwtMRL_2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x220020) -#define DDRPHY_HwtMRL_3(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x320020) - -#define DDRPHY_DFIPHYUPD(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x020021) -#define DDRPHY_PdaMrsWriteMode(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x020022) -#define DDRPHY_DFIGEARDOWNCTL(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x020023) - -#define DDRPHY_DqsPreambleControl_0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x020024) -#define DDRPHY_DqsPreambleControl_1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x120024) -#define DDRPHY_DqsPreambleControl_2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x220024) -#define DDRPHY_DqsPreambleControl_3(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x320024) - -#define DDRPHY_MasterX4Config(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x020025) -#define DDRPHY_WrLevBits(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x020026) -#define DDRPHY_EnableCsMulticast(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x020027) -#define DDRPHY_Acx4AnibDis(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x02002c) - -#define DDRPHY_ImgDramMR3_0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x02002D) -#define DDRPHY_ImgDramMR3_1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x12002D) -#define DDRPHY_ImgDramMR3_2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x22002D) -#define DDRPHY_ImgDramMR3_3(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x32002D) - -#define DDRPHY_ARdPtrInitVal_0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x02002E) -#define DDRPHY_ARdPtrInitVal_1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x12002E) -#define DDRPHY_ARdPtrInitVal_2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x22002E) -#define DDRPHY_ARdPtrInitVal_3(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x32002E) - -#define DDRPHY_Db0LcdlCalPhDetOut(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x020030) - -#define DDRPHY_Db1LcdlCalPhDetOut(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x020031) -#define DDRPHY_Db2LcdlCalPhDetOut(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x020032) -#define DDRPHY_Db3LcdlCalPhDetOut(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x020033) -#define DDRPHY_Db4LcdlCalPhDetOut(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x020034) -#define DDRPHY_Db5LcdlCalPhDetOut(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x020035) -#define DDRPHY_Db6LcdlCalPhDetOut(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x020036) -#define DDRPHY_Db7LcdlCalPhDetOut(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x020037) -#define DDRPHY_Db8LcdlCalPhDetOut(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x020038) -#define DDRPHY_Db9LcdlCalPhDetOut(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x020039) -#define DDRPHY_DbyteDllModeCntrl(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x02003A) -#define DDRPHY_DbyteRxEnTrain(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x02003B) -#define DDRPHY_AnLcdlCalPhDetOut(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x02003F) -#define DDRPHY_CalOffsets(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x020045) -#define DDRPHY_SarInitVals(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x020047) -#define DDRPHY_CalPExtOvr(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x020049) -#define DDRPHY_CalCmpr5Ovr(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x02004A) -#define DDRPHY_CalNIntOvr(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x02004B) -#define DDRPHY_CalDrvStr0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x020050) - -#define DDRPHY_ProcOdtCtl_0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x020055) -#define DDRPHY_ProcOdtCtl_1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x120055) -#define DDRPHY_ProcOdtCtl_2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x220055) -#define DDRPHY_ProcOdtCtl_3(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x320055) - -#define DDRPHY_ProcOdtTimeCtl_0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x020056) -#define DDRPHY_ProcOdtTimeCtl_1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x120056) -#define DDRPHY_ProcOdtTimeCtl_2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x220056) -#define DDRPHY_ProcOdtTimeCtl_3(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x320056) - -#define DDRPHY_MemAlertControl(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x02005B) -#define DDRPHY_MemAlertControl2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x02005C) -#define DDRPHY_MemResetL(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x020060) -#define DDRPHY_PUBMODE(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x02006E) -#define DDRPHY_MiscPhyStatus(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x02006F) -#define DDRPHY_CoreLoopbackSel(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x020070) -#define DDRPHY_DllTrainParam(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x020071) -#define DDRPHY_LpCsEnA(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x020072) -#define DDRPHY_LpCsEnB(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x020073) -#define DDRPHY_LpCsEnBypass(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x020074) -#define DDRPHY_DfiCAMode(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x020075) -#define DDRPHY_HwtCACtl(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x020076) -#define DDRPHY_HwtCAMode(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x020077) -#define DDRPHY_DllControl(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x020078) -#define DDRPHY_PulseDllUpdatePhase(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x020079) -#define DDRPHY_HwtControlOvr0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x02007A) -#define DDRPHY_HwtControlOvr1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x02007B) - -#define DDRPHY_DllGainCtl_0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x02007C) -#define DDRPHY_DllGainCtl_1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x12007C) -#define DDRPHY_DllGainCtl_2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x22007C) -#define DDRPHY_DllGainCtl_3(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x32007C) - -#define DDRPHY_DllLockParam(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x02007D) -#define DDRPHY_HwtControlVal0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x02007E) -#define DDRPHY_HwtControlVal1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x02007F) -#define DDRPHY_AcsmGlblStart(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x020081) -#define DDRPHY_AcsmGlblSglStpCtrl(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x020082) -#define DDRPHY_LcdlCalPhase(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x020084) -#define DDRPHY_LcdlCalCtrl(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x020085) -#define DDRPHY_CalRate(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x020088) -#define DDRPHY_CalZap(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x020089) -#define DDRPHY_PState(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x02008B) -#define DDRPHY_CalPreDriverOverride(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x02008C) -#define DDRPHY_PllOutGateControl(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x02008D) -#define DDRPHY_UcMemResetControl(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x02008F) - -#define DDRPHY_PorControl(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x020090) -#define DDRPHY_CalBusy(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x020097) -#define DDRPHY_CalMisc2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x020098) -#define DDRPHY_CalMisc(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x02009A) -#define DDRPHY_CalCmpr5(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x02009C) -#define DDRPHY_CalNInt(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x02009D) -#define DDRPHY_CalPExt(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x02009E) -#define DDRPHY_CalCmpInvert(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0200A8) -#define DDRPHY_CalCmpanaCntrl(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0200AE) - -#define DDRPHY_DfiRdDataCsDestMap_0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0200B0) -#define DDRPHY_DfiRdDataCsDestMap_1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x1200B0) -#define DDRPHY_DfiRdDataCsDestMap_2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x2200B0) -#define DDRPHY_DfiRdDataCsDestMap_3(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x3200B0) - -#define DDRPHY_VrefInGlobal_0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0200B2) -#define DDRPHY_VrefInGlobal_1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x1200B2) -#define DDRPHY_VrefInGlobal_2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x2200B2) -#define DDRPHY_VrefInGlobal_3(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x3200B2) - -#define DDRPHY_DfiWrDataCsDestMap_0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0200B4) -#define DDRPHY_DfiWrDataCsDestMap_1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x1200B4) -#define DDRPHY_DfiWrDataCsDestMap_2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x2200B4) -#define DDRPHY_DfiWrDataCsDestMap_3(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x3200B4) - -#define DDRPHY_PhyMasUpdGoodCtr(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0200B5) -#define DDRPHY_PhyCtlUpdGoodCtr(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0200B6) -#define DDRPHY_DctPhyUpdGoodCtr(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0200B7) -#define DDRPHY_PhyMasUpdFailCtr(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0200B8) -#define DDRPHY_PhyCtlUpdFailCtr(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0200B9) -#define DDRPHY_PhyCtlUpd1FailCtr(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0200BA) -#define DDRPHY_PhyPerfCtrEnable(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0200BB) -#define DDRPHY_PllPwrDn(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0200C3) -#define DDRPHY_PllReset(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0200C4) -#define DDRPHY_PllCtrl2_0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0200C5) -#define DDRPHY_PllCtrl2_1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x1200C5) -#define DDRPHY_PllCtrl2_2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x2200C5) -#define DDRPHY_PllCtrl2_3(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x3200C5) -#define DDRPHY_PllCtrl0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0200C6) -#define DDRPHY_PllCtrl1_0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0200C7) -#define DDRPHY_PllCtrl1_1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x1200C7) -#define DDRPHY_PllCtrl1_2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x2200C7) -#define DDRPHY_PllCtrl1_3(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x3200C7) -#define DDRPHY_PllTst(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0200C8) -#define DDRPHY_PllLockStatus(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0200C9) -#define DDRPHY_PllTestMode_0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0200CA) -#define DDRPHY_PllTestMode_1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x1200CA) -#define DDRPHY_PllTestMode_2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x2200CA) -#define DDRPHY_PllTestMode_3(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x3200CA) -#define DDRPHY_PllCtrl3(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0200CB) -#define DDRPHY_PllCtrl4_0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0200CC) -#define DDRPHY_PllCtrl4_1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x1200CC) -#define DDRPHY_PllCtrl4_2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x2200CC) -#define DDRPHY_PllCtrl4_3(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x3200CC) -#define DDRPHY_PllEndofCal(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0200CD) -#define DDRPHY_PllStandbyEff(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0200CE) -#define DDRPHY_PllDacValOut(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0200CF) -#define DDRPHY_DlyTestSeq(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0200D0) -#define DDRPHY_DlyTestRingSelDb(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0200D1) -#define DDRPHY_DlyTestRingSelAc(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0200D2) -#define DDRPHY_DlyTestCntDfiClkIV(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0200D3) -#define DDRPHY_DlyTestCntDfiClk(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0200D4) -#define DDRPHY_DlyTestCntRingOscDb0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0200D5) -#define DDRPHY_DlyTestCntRingOscDb1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0200D6) -#define DDRPHY_DlyTestCntRingOscDb2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0200D7) -#define DDRPHY_DlyTestCntRingOscDb3(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0200D8) -#define DDRPHY_DlyTestCntRingOscDb4(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0200D9) -#define DDRPHY_DlyTestCntRingOscDb5(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0200DA) -#define DDRPHY_DlyTestCntRingOscDb6(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0200DB) -#define DDRPHY_DlyTestCntRingOscDb7(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0200DC) -#define DDRPHY_DlyTestCntRingOscDb8(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0200DD) -#define DDRPHY_DlyTestCntRingOscDb9(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0200DE) -#define DDRPHY_DlyTestCntRingOscAc(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0200DF) -#define DDRPHY_MstLcdlDbgCntl(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0200E0) -#define DDRPHY_MstLcdl0DbgRes(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0200E1) -#define DDRPHY_MstLcdl1DbgRes(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0200E2) -#define DDRPHY_CUSTPHYREV(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0200ED) -#define DDRPHY_PHYREV(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0200EE) -#define DDRPHY_LP3ExitSeq0BStartVector(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0200EF) -#define DDRPHY_DfiFreqXlat0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0200F0) -#define DDRPHY_DfiFreqXlat1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0200F1) -#define DDRPHY_DfiFreqXlat2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0200F2) -#define DDRPHY_DfiFreqXlat3(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0200F3) -#define DDRPHY_DfiFreqXlat4(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0200F4) -#define DDRPHY_DfiFreqXlat5(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0200F5) -#define DDRPHY_DfiFreqXlat6(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0200F6) -#define DDRPHY_DfiFreqXlat7(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0200F7) -#define DDRPHY_TxRdPtrInit(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0200F8) -#define DDRPHY_DfiInitComplete(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0200F9) - -#define DDRPHY_DfiFreqRatio_0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0200FA) -#define DDRPHY_DfiFreqRatio_1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x1200FA) -#define DDRPHY_DfiFreqRatio_2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x2200FA) -#define DDRPHY_DfiFreqRatio_3(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x3200FA) - -#define DDRPHY_PPGCCtrl1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x070011) -#define DDRPHY_PpgcLane2CrcInMap0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x070015) -#define DDRPHY_PpgcLane2CrcInMap1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x070016) - -#define DDRPHY_PrbsTapDly0_0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x070024) -#define DDRPHY_PrbsTapDly0_1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x070124) -#define DDRPHY_PrbsTapDly0_2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x070224) -#define DDRPHY_PrbsTapDly0_3(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x070324) -#define DDRPHY_PrbsTapDly0_4(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x070424) -#define DDRPHY_PrbsTapDly0_5(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x070524) -#define DDRPHY_PrbsTapDly0_6(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x070624) -#define DDRPHY_PrbsTapDly0_7(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x070724) -#define DDRPHY_PrbsTapDly0_8(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x070824) - -#define DDRPHY_PrbsTapDly1_0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x070025) -#define DDRPHY_PrbsTapDly1_1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x070125) -#define DDRPHY_PrbsTapDly1_2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x070225) -#define DDRPHY_PrbsTapDly1_3(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x070325) -#define DDRPHY_PrbsTapDly1_4(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x070425) -#define DDRPHY_PrbsTapDly1_5(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x070525) -#define DDRPHY_PrbsTapDly1_6(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x070625) -#define DDRPHY_PrbsTapDly1_7(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x070725) -#define DDRPHY_PrbsTapDly1_8(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x070825) - -#define DDRPHY_PrbsTapDly2_0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x070026) -#define DDRPHY_PrbsTapDly2_1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x070126) -#define DDRPHY_PrbsTapDly2_2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x070226) -#define DDRPHY_PrbsTapDly2_3(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x070326) -#define DDRPHY_PrbsTapDly2_4(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x070426) -#define DDRPHY_PrbsTapDly2_5(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x070526) -#define DDRPHY_PrbsTapDly2_6(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x070626) -#define DDRPHY_PrbsTapDly2_7(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x070726) -#define DDRPHY_PrbsTapDly2_8(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x070826) - -#define DDRPHY_PrbsTapDly3_0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x070027) -#define DDRPHY_PrbsTapDly3_1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x070127) -#define DDRPHY_PrbsTapDly3_2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x070227) -#define DDRPHY_PrbsTapDly3_3(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x070327) -#define DDRPHY_PrbsTapDly3_4(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x070427) -#define DDRPHY_PrbsTapDly3_5(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x070527) -#define DDRPHY_PrbsTapDly3_6(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x070627) -#define DDRPHY_PrbsTapDly3_7(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x070727) -#define DDRPHY_PrbsTapDly3_8(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x070827) - -#define DDRPHY_GenPrbsByte0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x070030) -#define DDRPHY_GenPrbsByte1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x070031) -#define DDRPHY_GenPrbsByte2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x070032) -#define DDRPHY_GenPrbsByte3(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x070033) -#define DDRPHY_GenPrbsByte4(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x070034) -#define DDRPHY_GenPrbsByte5(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x070035) -#define DDRPHY_GenPrbsByte6(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x070036) -#define DDRPHY_GenPrbsByte7(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x070037) -#define DDRPHY_GenPrbsByte8(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x070038) -#define DDRPHY_GenPrbsByte9(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x070039) -#define DDRPHY_GenPrbsByte10(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x07003A) -#define DDRPHY_GenPrbsByte11(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x07003B) -#define DDRPHY_GenPrbsByte12(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x07003C) -#define DDRPHY_GenPrbsByte13(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x07003D) -#define DDRPHY_GenPrbsByte14(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x07003E) -#define DDRPHY_GenPrbsByte15(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x07003F) -#define DDRPHY_PrbsGenCtl(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x070060) -#define DDRPHY_PrbsGenStateLo(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x070061) -#define DDRPHY_PrbsGenStateHi(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x070062) -#define DDRPHY_PrbsChkStateLo(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x070063) -#define DDRPHY_PrbsChkStateHi(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x070064) -#define DDRPHY_PrbsGenCtl1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x070065) -#define DDRPHY_PrbsGenCtl2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x070066) - - -#define DRC_PERF_MON_BASE_ADDR(X) (0x3d800000 + (X * 0x2000000)) -#define DRC_PERF_MON_CNT0_CTL(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x0) -#define DRC_PERF_MON_CNT1_CTL(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x4) -#define DRC_PERF_MON_CNT2_CTL(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x8) -#define DRC_PERF_MON_CNT3_CTL(X) (DRC_PERF_MON_BASE_ADDR(X) + 0xC) -#define DRC_PERF_MON_CNT0_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x20) -#define DRC_PERF_MON_CNT1_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x24) -#define DRC_PERF_MON_CNT2_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x28) -#define DRC_PERF_MON_CNT3_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x2C) -#define DRC_PERF_MON_MRR0_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x40) -#define DRC_PERF_MON_MRR1_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x44) -#define DRC_PERF_MON_MRR2_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x48) -#define DRC_PERF_MON_MRR3_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x4C) -#define DRC_PERF_MON_MRR4_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x50) -#define DRC_PERF_MON_MRR5_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x54) -#define DRC_PERF_MON_MRR6_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x58) -#define DRC_PERF_MON_MRR7_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x5C) -#define DRC_PERF_MON_MRR8_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x60) -#define DRC_PERF_MON_MRR9_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x64) -#define DRC_PERF_MON_MRR10_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x68) -#define DRC_PERF_MON_MRR11_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x6C) -#define DRC_PERF_MON_MRR12_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x70) -#define DRC_PERF_MON_MRR13_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x74) -#define DRC_PERF_MON_MRR14_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x78) -#define DRC_PERF_MON_MRR15_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x7C) -#endif diff --git a/board/boundary/nitrogen8m/ddr/ddrphy_train.c b/board/boundary/nitrogen8m/ddr/ddrphy_train.c index 8a988e46252..70f02d7b3a1 100644 --- a/board/boundary/nitrogen8m/ddr/ddrphy_train.c +++ b/board/boundary/nitrogen8m/ddr/ddrphy_train.c @@ -7,11 +7,13 @@ #include <common.h> #include <asm/io.h> #include <asm/arch/clock.h> +#include <asm/arch/ddr.h> +#include <asm/arch/imx8m_ddr.h> #include "ddr_memory_map.h" #include "ddr.h" #include "lpddr4_dvfs.h" -extern void wait_ddrphy_training_complete(void); +extern void wait_ddrphy_training_complete1(void); void sscgpll_bypass_enable(unsigned int reg_addr) { @@ -89,1058 +91,1058 @@ void dwc_ddrphy_phyinit_userCustom_E_setDfiClk(int pstate) void lpddr4_800M_cfg_phy(void) { printf("start to config phy: p0=3200mts, p1=667mts with 1D2D training\n"); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x20110, 0x02); /* MapCAB0toDFI */ - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x20111, 0x03); /* MapCAB1toDFI */ - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x20112, 0x04); /* MapCAB2toDFI */ - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x20113, 0x05); /* MapCAB3toDFI */ - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x20114, 0x00); /* MapCAB4toDFI */ - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x20115, 0x01); /* MapCAB5toDFI */ + dwc_ddrphy_apb_wr0(4 * 0x20110, 0x02); /* MapCAB0toDFI */ + dwc_ddrphy_apb_wr0(4 * 0x20111, 0x03); /* MapCAB1toDFI */ + dwc_ddrphy_apb_wr0(4 * 0x20112, 0x04); /* MapCAB2toDFI */ + dwc_ddrphy_apb_wr0(4 * 0x20113, 0x05); /* MapCAB3toDFI */ + dwc_ddrphy_apb_wr0(4 * 0x20114, 0x00); /* MapCAB4toDFI */ + dwc_ddrphy_apb_wr0(4 * 0x20115, 0x01); /* MapCAB5toDFI */ /* Initialize PHY Configuration */ - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x1005f, 0x1ff); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x1015f, 0x1ff); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x1105f, 0x1ff); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x1115f, 0x1ff); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x1205f, 0x1ff); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x1215f, 0x1ff); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x1305f, 0x1ff); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x1315f, 0x1ff); + dwc_ddrphy_apb_wr0(4 * 0x1005f, 0x1ff); + dwc_ddrphy_apb_wr0(4 * 0x1015f, 0x1ff); + dwc_ddrphy_apb_wr0(4 * 0x1105f, 0x1ff); + dwc_ddrphy_apb_wr0(4 * 0x1115f, 0x1ff); + dwc_ddrphy_apb_wr0(4 * 0x1205f, 0x1ff); + dwc_ddrphy_apb_wr0(4 * 0x1215f, 0x1ff); + dwc_ddrphy_apb_wr0(4 * 0x1305f, 0x1ff); + dwc_ddrphy_apb_wr0(4 * 0x1315f, 0x1ff); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x11005f, 0x1ff); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x11015f, 0x1ff); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x11105f, 0x1ff); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x11115f, 0x1ff); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x11205f, 0x1ff); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x11215f, 0x1ff); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x11305f, 0x1ff); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x11315f, 0x1ff); + dwc_ddrphy_apb_wr0(4 * 0x11005f, 0x1ff); + dwc_ddrphy_apb_wr0(4 * 0x11015f, 0x1ff); + dwc_ddrphy_apb_wr0(4 * 0x11105f, 0x1ff); + dwc_ddrphy_apb_wr0(4 * 0x11115f, 0x1ff); + dwc_ddrphy_apb_wr0(4 * 0x11205f, 0x1ff); + dwc_ddrphy_apb_wr0(4 * 0x11215f, 0x1ff); + dwc_ddrphy_apb_wr0(4 * 0x11305f, 0x1ff); + dwc_ddrphy_apb_wr0(4 * 0x11315f, 0x1ff); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x21005f, 0x1ff); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x21015f, 0x1ff); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x21105f, 0x1ff); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x21115f, 0x1ff); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x21205f, 0x1ff); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x21215f, 0x1ff); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x21305f, 0x1ff); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x21315f, 0x1ff); + dwc_ddrphy_apb_wr0(4 * 0x21005f, 0x1ff); + dwc_ddrphy_apb_wr0(4 * 0x21015f, 0x1ff); + dwc_ddrphy_apb_wr0(4 * 0x21105f, 0x1ff); + dwc_ddrphy_apb_wr0(4 * 0x21115f, 0x1ff); + dwc_ddrphy_apb_wr0(4 * 0x21205f, 0x1ff); + dwc_ddrphy_apb_wr0(4 * 0x21215f, 0x1ff); + dwc_ddrphy_apb_wr0(4 * 0x21305f, 0x1ff); + dwc_ddrphy_apb_wr0(4 * 0x21315f, 0x1ff); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x55, 0x1ff); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x1055, 0x1ff); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x2055, 0x1ff); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x3055, 0x1ff); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4055, 0x1ff); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5055, 0x1ff); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x6055, 0x1ff); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x7055, 0x1ff); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x8055, 0x1ff); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9055, 0x1ff); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x200c5, 0x19); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x1200c5, 0x7); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x2200c5, 0x7); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x2002e, 0x2); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x12002e, 0x1); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x22002e, 0x2); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90204, 0x0); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x190204, 0x0); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x290204, 0x0); + dwc_ddrphy_apb_wr0(4 * 0x55, 0x1ff); + dwc_ddrphy_apb_wr0(4 * 0x1055, 0x1ff); + dwc_ddrphy_apb_wr0(4 * 0x2055, 0x1ff); + dwc_ddrphy_apb_wr0(4 * 0x3055, 0x1ff); + dwc_ddrphy_apb_wr0(4 * 0x4055, 0x1ff); + dwc_ddrphy_apb_wr0(4 * 0x5055, 0x1ff); + dwc_ddrphy_apb_wr0(4 * 0x6055, 0x1ff); + dwc_ddrphy_apb_wr0(4 * 0x7055, 0x1ff); + dwc_ddrphy_apb_wr0(4 * 0x8055, 0x1ff); + dwc_ddrphy_apb_wr0(4 * 0x9055, 0x1ff); + dwc_ddrphy_apb_wr0(4 * 0x200c5, 0x19); + dwc_ddrphy_apb_wr0(4 * 0x1200c5, 0x7); + dwc_ddrphy_apb_wr0(4 * 0x2200c5, 0x7); + dwc_ddrphy_apb_wr0(4 * 0x2002e, 0x2); + dwc_ddrphy_apb_wr0(4 * 0x12002e, 0x1); + dwc_ddrphy_apb_wr0(4 * 0x22002e, 0x2); + dwc_ddrphy_apb_wr0(4 * 0x90204, 0x0); + dwc_ddrphy_apb_wr0(4 * 0x190204, 0x0); + dwc_ddrphy_apb_wr0(4 * 0x290204, 0x0); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x20024, 0xe3); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x2003a, 0x2); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x120024, 0xa3); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x2003a, 0x2); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x220024, 0xa3); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x2003a, 0x2); + dwc_ddrphy_apb_wr0(4 * 0x20024, 0xe3); + dwc_ddrphy_apb_wr0(4 * 0x2003a, 0x2); + dwc_ddrphy_apb_wr0(4 * 0x120024, 0xa3); + dwc_ddrphy_apb_wr0(4 * 0x2003a, 0x2); + dwc_ddrphy_apb_wr0(4 * 0x220024, 0xa3); + dwc_ddrphy_apb_wr0(4 * 0x2003a, 0x2); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x20056, 0x3); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x120056, 0xa); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x220056, 0xa); + dwc_ddrphy_apb_wr0(4 * 0x20056, 0x3); + dwc_ddrphy_apb_wr0(4 * 0x120056, 0xa); + dwc_ddrphy_apb_wr0(4 * 0x220056, 0xa); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x1004d, 0xe00); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x1014d, 0xe00); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x1104d, 0xe00); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x1114d, 0xe00); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x1204d, 0xe00); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x1214d, 0xe00); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x1304d, 0xe00); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x1314d, 0xe00); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x11004d, 0xe00); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x11014d, 0xe00); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x11104d, 0xe00); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x11114d, 0xe00); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x11204d, 0xe00); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x11214d, 0xe00); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x11304d, 0xe00); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x11314d, 0xe00); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x21004d, 0xe00); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x21014d, 0xe00); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x21104d, 0xe00); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x21114d, 0xe00); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x21204d, 0xe00); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x21214d, 0xe00); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x21304d, 0xe00); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x21314d, 0xe00); + dwc_ddrphy_apb_wr0(4 * 0x1004d, 0xe00); + dwc_ddrphy_apb_wr0(4 * 0x1014d, 0xe00); + dwc_ddrphy_apb_wr0(4 * 0x1104d, 0xe00); + dwc_ddrphy_apb_wr0(4 * 0x1114d, 0xe00); + dwc_ddrphy_apb_wr0(4 * 0x1204d, 0xe00); + dwc_ddrphy_apb_wr0(4 * 0x1214d, 0xe00); + dwc_ddrphy_apb_wr0(4 * 0x1304d, 0xe00); + dwc_ddrphy_apb_wr0(4 * 0x1314d, 0xe00); + dwc_ddrphy_apb_wr0(4 * 0x11004d, 0xe00); + dwc_ddrphy_apb_wr0(4 * 0x11014d, 0xe00); + dwc_ddrphy_apb_wr0(4 * 0x11104d, 0xe00); + dwc_ddrphy_apb_wr0(4 * 0x11114d, 0xe00); + dwc_ddrphy_apb_wr0(4 * 0x11204d, 0xe00); + dwc_ddrphy_apb_wr0(4 * 0x11214d, 0xe00); + dwc_ddrphy_apb_wr0(4 * 0x11304d, 0xe00); + dwc_ddrphy_apb_wr0(4 * 0x11314d, 0xe00); + dwc_ddrphy_apb_wr0(4 * 0x21004d, 0xe00); + dwc_ddrphy_apb_wr0(4 * 0x21014d, 0xe00); + dwc_ddrphy_apb_wr0(4 * 0x21104d, 0xe00); + dwc_ddrphy_apb_wr0(4 * 0x21114d, 0xe00); + dwc_ddrphy_apb_wr0(4 * 0x21204d, 0xe00); + dwc_ddrphy_apb_wr0(4 * 0x21214d, 0xe00); + dwc_ddrphy_apb_wr0(4 * 0x21304d, 0xe00); + dwc_ddrphy_apb_wr0(4 * 0x21314d, 0xe00); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x10049, 0xfbe); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x10149, 0xfbe); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x11049, 0xfbe); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x11149, 0xfbe); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x12049, 0xfbe); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x12149, 0xfbe); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x13049, 0xfbe); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x13149, 0xfbe); + dwc_ddrphy_apb_wr0(4 * 0x10049, 0xfbe); + dwc_ddrphy_apb_wr0(4 * 0x10149, 0xfbe); + dwc_ddrphy_apb_wr0(4 * 0x11049, 0xfbe); + dwc_ddrphy_apb_wr0(4 * 0x11149, 0xfbe); + dwc_ddrphy_apb_wr0(4 * 0x12049, 0xfbe); + dwc_ddrphy_apb_wr0(4 * 0x12149, 0xfbe); + dwc_ddrphy_apb_wr0(4 * 0x13049, 0xfbe); + dwc_ddrphy_apb_wr0(4 * 0x13149, 0xfbe); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x110049, 0xfbe); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x110149, 0xfbe); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x111049, 0xfbe); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x111149, 0xfbe); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x112049, 0xfbe); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x112149, 0xfbe); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x113049, 0xfbe); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x113149, 0xfbe); + dwc_ddrphy_apb_wr0(4 * 0x110049, 0xfbe); + dwc_ddrphy_apb_wr0(4 * 0x110149, 0xfbe); + dwc_ddrphy_apb_wr0(4 * 0x111049, 0xfbe); + dwc_ddrphy_apb_wr0(4 * 0x111149, 0xfbe); + dwc_ddrphy_apb_wr0(4 * 0x112049, 0xfbe); + dwc_ddrphy_apb_wr0(4 * 0x112149, 0xfbe); + dwc_ddrphy_apb_wr0(4 * 0x113049, 0xfbe); + dwc_ddrphy_apb_wr0(4 * 0x113149, 0xfbe); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x210049, 0xfbe); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x210149, 0xfbe); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x211049, 0xfbe); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x211149, 0xfbe); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x212049, 0xfbe); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x212149, 0xfbe); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x213049, 0xfbe); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x213149, 0xfbe); + dwc_ddrphy_apb_wr0(4 * 0x210049, 0xfbe); + dwc_ddrphy_apb_wr0(4 * 0x210149, 0xfbe); + dwc_ddrphy_apb_wr0(4 * 0x211049, 0xfbe); + dwc_ddrphy_apb_wr0(4 * 0x211149, 0xfbe); + dwc_ddrphy_apb_wr0(4 * 0x212049, 0xfbe); + dwc_ddrphy_apb_wr0(4 * 0x212149, 0xfbe); + dwc_ddrphy_apb_wr0(4 * 0x213049, 0xfbe); + dwc_ddrphy_apb_wr0(4 * 0x213149, 0xfbe); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x43, 0x63); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x1043, 0x63); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x2043, 0x63); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x3043, 0x63); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4043, 0x63); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5043, 0x63); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x6043, 0x63); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x7043, 0x63); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x8043, 0x63); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9043, 0x63); + dwc_ddrphy_apb_wr0(4 * 0x43, 0x63); + dwc_ddrphy_apb_wr0(4 * 0x1043, 0x63); + dwc_ddrphy_apb_wr0(4 * 0x2043, 0x63); + dwc_ddrphy_apb_wr0(4 * 0x3043, 0x63); + dwc_ddrphy_apb_wr0(4 * 0x4043, 0x63); + dwc_ddrphy_apb_wr0(4 * 0x5043, 0x63); + dwc_ddrphy_apb_wr0(4 * 0x6043, 0x63); + dwc_ddrphy_apb_wr0(4 * 0x7043, 0x63); + dwc_ddrphy_apb_wr0(4 * 0x8043, 0x63); + dwc_ddrphy_apb_wr0(4 * 0x9043, 0x63); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x20018, 0x3); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x20075, 0x4); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x20050, 0x0); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x20008, 0x320); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x120008, 0xa7); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x220008, 0x19); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x20088, 0x9); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x200b2, 0x104); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x10043, 0x5a1); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x10143, 0x5a1); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x11043, 0x5a1); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x11143, 0x5a1); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x12043, 0x5a1); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x12143, 0x5a1); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x13043, 0x5a1); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x13143, 0x5a1); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x1200b2, 0x104); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x110043, 0x5a1); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x110143, 0x5a1); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x111043, 0x5a1); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x111143, 0x5a1); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x112043, 0x5a1); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x112143, 0x5a1); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x113043, 0x5a1); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x113143, 0x5a1); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x2200b2, 0x104); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x210043, 0x5a1); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x210143, 0x5a1); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x211043, 0x5a1); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x211143, 0x5a1); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x212043, 0x5a1); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x212143, 0x5a1); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x213043, 0x5a1); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x213143, 0x5a1); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x200fa, 0x1); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x1200fa, 0x1); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x2200fa, 0x1); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x20019, 0x1); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x120019, 0x1); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x220019, 0x1); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x200f0, 0x600); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x200f1, 0x0); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x200f2, 0x4444); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x200f3, 0x8888); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x200f4, 0x5655); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x200f5, 0x0); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x200f6, 0x0); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x200f7, 0xf000); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x20025, 0x0); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x2002d, 0x0); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x12002d, 0x0); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x22002d, 0x0); + dwc_ddrphy_apb_wr0(4 * 0x20018, 0x3); + dwc_ddrphy_apb_wr0(4 * 0x20075, 0x4); + dwc_ddrphy_apb_wr0(4 * 0x20050, 0x0); + dwc_ddrphy_apb_wr0(4 * 0x20008, 0x320); + dwc_ddrphy_apb_wr0(4 * 0x120008, 0xa7); + dwc_ddrphy_apb_wr0(4 * 0x220008, 0x19); + dwc_ddrphy_apb_wr0(4 * 0x20088, 0x9); + dwc_ddrphy_apb_wr0(4 * 0x200b2, 0x104); + dwc_ddrphy_apb_wr0(4 * 0x10043, 0x5a1); + dwc_ddrphy_apb_wr0(4 * 0x10143, 0x5a1); + dwc_ddrphy_apb_wr0(4 * 0x11043, 0x5a1); + dwc_ddrphy_apb_wr0(4 * 0x11143, 0x5a1); + dwc_ddrphy_apb_wr0(4 * 0x12043, 0x5a1); + dwc_ddrphy_apb_wr0(4 * 0x12143, 0x5a1); + dwc_ddrphy_apb_wr0(4 * 0x13043, 0x5a1); + dwc_ddrphy_apb_wr0(4 * 0x13143, 0x5a1); + dwc_ddrphy_apb_wr0(4 * 0x1200b2, 0x104); + dwc_ddrphy_apb_wr0(4 * 0x110043, 0x5a1); + dwc_ddrphy_apb_wr0(4 * 0x110143, 0x5a1); + dwc_ddrphy_apb_wr0(4 * 0x111043, 0x5a1); + dwc_ddrphy_apb_wr0(4 * 0x111143, 0x5a1); + dwc_ddrphy_apb_wr0(4 * 0x112043, 0x5a1); + dwc_ddrphy_apb_wr0(4 * 0x112143, 0x5a1); + dwc_ddrphy_apb_wr0(4 * 0x113043, 0x5a1); + dwc_ddrphy_apb_wr0(4 * 0x113143, 0x5a1); + dwc_ddrphy_apb_wr0(4 * 0x2200b2, 0x104); + dwc_ddrphy_apb_wr0(4 * 0x210043, 0x5a1); + dwc_ddrphy_apb_wr0(4 * 0x210143, 0x5a1); + dwc_ddrphy_apb_wr0(4 * 0x211043, 0x5a1); + dwc_ddrphy_apb_wr0(4 * 0x211143, 0x5a1); + dwc_ddrphy_apb_wr0(4 * 0x212043, 0x5a1); + dwc_ddrphy_apb_wr0(4 * 0x212143, 0x5a1); + dwc_ddrphy_apb_wr0(4 * 0x213043, 0x5a1); + dwc_ddrphy_apb_wr0(4 * 0x213143, 0x5a1); + dwc_ddrphy_apb_wr0(4 * 0x200fa, 0x1); + dwc_ddrphy_apb_wr0(4 * 0x1200fa, 0x1); + dwc_ddrphy_apb_wr0(4 * 0x2200fa, 0x1); + dwc_ddrphy_apb_wr0(4 * 0x20019, 0x1); + dwc_ddrphy_apb_wr0(4 * 0x120019, 0x1); + dwc_ddrphy_apb_wr0(4 * 0x220019, 0x1); + dwc_ddrphy_apb_wr0(4 * 0x200f0, 0x600); + dwc_ddrphy_apb_wr0(4 * 0x200f1, 0x0); + dwc_ddrphy_apb_wr0(4 * 0x200f2, 0x4444); + dwc_ddrphy_apb_wr0(4 * 0x200f3, 0x8888); + dwc_ddrphy_apb_wr0(4 * 0x200f4, 0x5655); + dwc_ddrphy_apb_wr0(4 * 0x200f5, 0x0); + dwc_ddrphy_apb_wr0(4 * 0x200f6, 0x0); + dwc_ddrphy_apb_wr0(4 * 0x200f7, 0xf000); + dwc_ddrphy_apb_wr0(4 * 0x20025, 0x0); + dwc_ddrphy_apb_wr0(4 * 0x2002d, 0x0); + dwc_ddrphy_apb_wr0(4 * 0x12002d, 0x0); + dwc_ddrphy_apb_wr0(4 * 0x22002d, 0x0); /* Load the 1D IMEM image */ - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x0); + dwc_ddrphy_apb_wr0(4 * 0xd0000, 0x0); ddr_load_train_code(FW_1D_IMAGE); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x1); + dwc_ddrphy_apb_wr0(4 * 0xd0000, 0x1); /* Set the PHY input clocks for pstate 0 */ dwc_ddrphy_phyinit_userCustom_E_setDfiClk (0); /* Load the 1D DMEM image and write the 1D Message Block parameters for the training firmware */ - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x0); + dwc_ddrphy_apb_wr0(4 * 0xd0000, 0x0); printf("config to do 3200 1d training.\n"); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x0); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54000, 0x0); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54001, 0x0); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54002, 0x0); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54003, 0xc80); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54004, 0x2); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54005, ((LPDDR4_PHY_RON<<8) | LPDDR4_PHY_RTT)); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54006, LPDDR4_PHY_VREF_VALUE); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54007, 0x0); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54008, 0x131f); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54009, LPDDR4_HDT_CTL_3200_1D); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400a, 0x0); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400b, 0x2); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400c, 0x0); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400d, (LPDDR4_CATRAIN_3200_1d << 8)); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400e, 0x0); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400f, 0x0); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54010, 0x0); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54011, 0x0); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54012, 0x310); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54013, 0x0); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54014, 0x0); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54015, 0x0); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54016, 0x0); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54017, 0x0); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54018, 0x0); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54019, 0x2dd4); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401a, (((LPDDR4_RON) << 3) | 0x3)); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401b, ((LPDDR4_VREF_VALUE_CA << 8) | (LPDDR4_RTT_CA_BANK0 << 4) | LPDDR4_RTT_DQ)); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401c, ((LPDDR4_VREF_VALUE_DQ_RANK0 << 8) | 0x08)); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401d, 0x0); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401e, LPDDR4_MR22_RANK0); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401f, 0x2dd4); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54020, (((LPDDR4_RON) << 3) | 0x3)); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54021, ((LPDDR4_VREF_VALUE_CA << 8) | (LPDDR4_RTT_CA_BANK1 << 4) | LPDDR4_RTT_DQ)); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54022, ((LPDDR4_VREF_VALUE_DQ_RANK1 << 8) | 0x08)); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54023, 0x0); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54024, LPDDR4_MR22_RANK1); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54025, 0x0); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54026, 0x0); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54027, 0x0); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54028, 0x0); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54029, 0x0); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402a, 0x0); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402b, 0x1000); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402c, 0x3); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402d, 0x0); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402e, 0x0); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402f, 0x0); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54030, 0x0); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54031, 0x0); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54032, 0xd400); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54033, ((((LPDDR4_RON) << 3) | 0x3) << 8) | 0x2d); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54034, (((LPDDR4_RTT_CA_BANK0 << 4) | LPDDR4_RTT_DQ) << 8)); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54035, (0x0800|LPDDR4_VREF_VALUE_CA)); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54036, LPDDR4_VREF_VALUE_DQ_RANK0); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54037, (LPDDR4_MR22_RANK0 << 8)); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54038, 0xd400); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54039, ((((LPDDR4_RON) << 3) | 0x3) << 8) | 0x2d); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403a, (((LPDDR4_RTT_CA_BANK1 << 4) | LPDDR4_RTT_DQ) << 8)); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403b, (0x0800 | LPDDR4_VREF_VALUE_CA)); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403c, LPDDR4_VREF_VALUE_DQ_RANK1); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403d, (LPDDR4_MR22_RANK1 << 8)); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403d, (LPDDR4_MR22_RANK1 << 8)); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403e, 0x0); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403f, 0x0); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54040, 0x0); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54041, 0x0); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54042, 0x0); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54043, 0x0); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54044, 0x0); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x1); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x1); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x9); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x1); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x0); + dwc_ddrphy_apb_wr0(4 * 0xd0000, 0x0); + dwc_ddrphy_apb_wr0(4 * 0x54000, 0x0); + dwc_ddrphy_apb_wr0(4 * 0x54001, 0x0); + dwc_ddrphy_apb_wr0(4 * 0x54002, 0x0); + dwc_ddrphy_apb_wr0(4 * 0x54003, 0xc80); + dwc_ddrphy_apb_wr0(4 * 0x54004, 0x2); + dwc_ddrphy_apb_wr0(4 * 0x54005, ((LPDDR4_PHY_RON<<8) | LPDDR4_PHY_RTT)); + dwc_ddrphy_apb_wr0(4 * 0x54006, LPDDR4_PHY_VREF_VALUE); + dwc_ddrphy_apb_wr0(4 * 0x54007, 0x0); + dwc_ddrphy_apb_wr0(4 * 0x54008, 0x131f); + dwc_ddrphy_apb_wr0(4 * 0x54009, LPDDR4_HDT_CTL_3200_1D); + dwc_ddrphy_apb_wr0(4 * 0x5400a, 0x0); + dwc_ddrphy_apb_wr0(4 * 0x5400b, 0x2); + dwc_ddrphy_apb_wr0(4 * 0x5400c, 0x0); + dwc_ddrphy_apb_wr0(4 * 0x5400d, (LPDDR4_CATRAIN_3200_1d << 8)); + dwc_ddrphy_apb_wr0(4 * 0x5400e, 0x0); + dwc_ddrphy_apb_wr0(4 * 0x5400f, 0x0); + dwc_ddrphy_apb_wr0(4 * 0x54010, 0x0); + dwc_ddrphy_apb_wr0(4 * 0x54011, 0x0); + dwc_ddrphy_apb_wr0(4 * 0x54012, 0x310); + dwc_ddrphy_apb_wr0(4 * 0x54013, 0x0); + dwc_ddrphy_apb_wr0(4 * 0x54014, 0x0); + dwc_ddrphy_apb_wr0(4 * 0x54015, 0x0); + dwc_ddrphy_apb_wr0(4 * 0x54016, 0x0); + dwc_ddrphy_apb_wr0(4 * 0x54017, 0x0); + dwc_ddrphy_apb_wr0(4 * 0x54018, 0x0); + dwc_ddrphy_apb_wr0(4 * 0x54019, 0x2dd4); + dwc_ddrphy_apb_wr0(4 * 0x5401a, (((LPDDR4_RON) << 3) | 0x3)); + dwc_ddrphy_apb_wr0(4 * 0x5401b, ((LPDDR4_VREF_VALUE_CA << 8) | (LPDDR4_RTT_CA_BANK0 << 4) | LPDDR4_RTT_DQ)); + dwc_ddrphy_apb_wr0(4 * 0x5401c, ((LPDDR4_VREF_VALUE_DQ_RANK0 << 8) | 0x08)); + dwc_ddrphy_apb_wr0(4 * 0x5401d, 0x0); + dwc_ddrphy_apb_wr0(4 * 0x5401e, LPDDR4_MR22_RANK0); + dwc_ddrphy_apb_wr0(4 * 0x5401f, 0x2dd4); + dwc_ddrphy_apb_wr0(4 * 0x54020, (((LPDDR4_RON) << 3) | 0x3)); + dwc_ddrphy_apb_wr0(4 * 0x54021, ((LPDDR4_VREF_VALUE_CA << 8) | (LPDDR4_RTT_CA_BANK1 << 4) | LPDDR4_RTT_DQ)); + dwc_ddrphy_apb_wr0(4 * 0x54022, ((LPDDR4_VREF_VALUE_DQ_RANK1 << 8) | 0x08)); + dwc_ddrphy_apb_wr0(4 * 0x54023, 0x0); + dwc_ddrphy_apb_wr0(4 * 0x54024, LPDDR4_MR22_RANK1); + dwc_ddrphy_apb_wr0(4 * 0x54025, 0x0); + dwc_ddrphy_apb_wr0(4 * 0x54026, 0x0); + dwc_ddrphy_apb_wr0(4 * 0x54027, 0x0); + dwc_ddrphy_apb_wr0(4 * 0x54028, 0x0); + dwc_ddrphy_apb_wr0(4 * 0x54029, 0x0); + dwc_ddrphy_apb_wr0(4 * 0x5402a, 0x0); + dwc_ddrphy_apb_wr0(4 * 0x5402b, 0x1000); + dwc_ddrphy_apb_wr0(4 * 0x5402c, 0x3); + dwc_ddrphy_apb_wr0(4 * 0x5402d, 0x0); + dwc_ddrphy_apb_wr0(4 * 0x5402e, 0x0); + dwc_ddrphy_apb_wr0(4 * 0x5402f, 0x0); + dwc_ddrphy_apb_wr0(4 * 0x54030, 0x0); + dwc_ddrphy_apb_wr0(4 * 0x54031, 0x0); + dwc_ddrphy_apb_wr0(4 * 0x54032, 0xd400); + dwc_ddrphy_apb_wr0(4 * 0x54033, ((((LPDDR4_RON) << 3) | 0x3) << 8) | 0x2d); + dwc_ddrphy_apb_wr0(4 * 0x54034, (((LPDDR4_RTT_CA_BANK0 << 4) | LPDDR4_RTT_DQ) << 8)); + dwc_ddrphy_apb_wr0(4 * 0x54035, (0x0800|LPDDR4_VREF_VALUE_CA)); + dwc_ddrphy_apb_wr0(4 * 0x54036, LPDDR4_VREF_VALUE_DQ_RANK0); + dwc_ddrphy_apb_wr0(4 * 0x54037, (LPDDR4_MR22_RANK0 << 8)); + dwc_ddrphy_apb_wr0(4 * 0x54038, 0xd400); + dwc_ddrphy_apb_wr0(4 * 0x54039, ((((LPDDR4_RON) << 3) | 0x3) << 8) | 0x2d); + dwc_ddrphy_apb_wr0(4 * 0x5403a, (((LPDDR4_RTT_CA_BANK1 << 4) | LPDDR4_RTT_DQ) << 8)); + dwc_ddrphy_apb_wr0(4 * 0x5403b, (0x0800 | LPDDR4_VREF_VALUE_CA)); + dwc_ddrphy_apb_wr0(4 * 0x5403c, LPDDR4_VREF_VALUE_DQ_RANK1); + dwc_ddrphy_apb_wr0(4 * 0x5403d, (LPDDR4_MR22_RANK1 << 8)); + dwc_ddrphy_apb_wr0(4 * 0x5403d, (LPDDR4_MR22_RANK1 << 8)); + dwc_ddrphy_apb_wr0(4 * 0x5403e, 0x0); + dwc_ddrphy_apb_wr0(4 * 0x5403f, 0x0); + dwc_ddrphy_apb_wr0(4 * 0x54040, 0x0); + dwc_ddrphy_apb_wr0(4 * 0x54041, 0x0); + dwc_ddrphy_apb_wr0(4 * 0x54042, 0x0); + dwc_ddrphy_apb_wr0(4 * 0x54043, 0x0); + dwc_ddrphy_apb_wr0(4 * 0x54044, 0x0); + dwc_ddrphy_apb_wr0(4 * 0xd0000, 0x1); + dwc_ddrphy_apb_wr0(4 * 0xd0000, 0x1); + dwc_ddrphy_apb_wr0(4 * 0xd0099, 0x9); + dwc_ddrphy_apb_wr0(4 * 0xd0099, 0x1); + dwc_ddrphy_apb_wr0(4 * 0xd0099, 0x0); /* wait for train complete */ - wait_ddrphy_training_complete(); + wait_ddrphy_training_complete1(); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x1); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x0); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x1); + dwc_ddrphy_apb_wr0(4 * 0xd0099, 0x1); + dwc_ddrphy_apb_wr0(4 * 0xd0000, 0x0); + dwc_ddrphy_apb_wr0(4 * 0xd0000, 0x1); /* Load the 2D IMEM image */ - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x0); + dwc_ddrphy_apb_wr0(4 * 0xd0000, 0x0); ddr_load_train_code(FW_2D_IMAGE); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x1); + dwc_ddrphy_apb_wr0(4 * 0xd0000, 0x1); /* 3200 mts 2D training */ printf("config to do 3200 2d training.\n"); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x0); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54000, 0x0); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54001, 0x0); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54002, 0x0); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54003, 0xc80); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54004, 0x2); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54005, ((LPDDR4_PHY_RON << 8) | LPDDR4_PHY_RTT)); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54006, LPDDR4_PHY_VREF_VALUE); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54007, 0x0); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54008, 0x61); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54009, LPDDR4_HDT_CTL_2D); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400a, 0x0); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400b, 0x2); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400c, 0x0); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400d, (LPDDR4_CATRAIN_3200_2d << 8)); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400e, 0x0); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400f, (LPDDR4_2D_SHARE << 8) | 0x00); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54010, LPDDR4_2D_WEIGHT); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54011, 0x0); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54012, 0x310); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54013, 0x0); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54014, 0x0); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54015, 0x0); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54016, 0x0); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54017, 0x0); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54018, 0x0); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54024, 0x5); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54019, 0x2dd4); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401a, (((LPDDR4_RON) << 3) | 0x3)); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401b, ((LPDDR4_VREF_VALUE_CA << 8) | (LPDDR4_RTT_CA_BANK0 << 4) | LPDDR4_RTT_DQ)); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401c, ((LPDDR4_VREF_VALUE_DQ_RANK0 << 8) | 0x08)); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401d, 0x0); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401e, LPDDR4_MR22_RANK0); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401f, 0x2dd4); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54020, (((LPDDR4_RON) << 3) | 0x3)); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54021, ((LPDDR4_VREF_VALUE_CA << 8) | (LPDDR4_RTT_CA_BANK1 << 4) | LPDDR4_RTT_DQ)); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54022, ((LPDDR4_VREF_VALUE_DQ_RANK1 << 8) | 0x08)); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54023, 0x0); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54024, LPDDR4_MR22_RANK1); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54025, 0x0); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54026, 0x0); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54027, 0x0); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54028, 0x0); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54029, 0x0); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402a, 0x0); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402b, 0x1000); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402c, 0x3); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402d, 0x0); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402e, 0x0); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402f, 0x0); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54030, 0x0); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54031, 0x0); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54032, 0xd400); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54033, ((((LPDDR4_RON) << 3) | 0x3) << 8) | 0x2d); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54034, (((LPDDR4_RTT_CA_BANK0 << 4) | LPDDR4_RTT_DQ) << 8)); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54035, (0x0800|LPDDR4_VREF_VALUE_CA)); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54036, LPDDR4_VREF_VALUE_DQ_RANK0); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54037, (LPDDR4_MR22_RANK0 << 8)); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54038, 0xd400); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54039, ((((LPDDR4_RON) << 3) | 0x3) << 8) | 0x2d); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403a, (((LPDDR4_RTT_CA_BANK1 << 4) | LPDDR4_RTT_DQ) << 8)); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403b, (0x0800|LPDDR4_VREF_VALUE_CA)); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403c, LPDDR4_VREF_VALUE_DQ_RANK1); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403d, (LPDDR4_MR22_RANK1 << 8)); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403e, 0x0); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403f, 0x0); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54040, 0x0); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54041, 0x0); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54042, 0x0); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54043, 0x0); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54044, 0x0); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x1); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x1); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x9); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x1); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x0); + dwc_ddrphy_apb_wr0(4 * 0xd0000, 0x0); + dwc_ddrphy_apb_wr0(4 * 0x54000, 0x0); + dwc_ddrphy_apb_wr0(4 * 0x54001, 0x0); + dwc_ddrphy_apb_wr0(4 * 0x54002, 0x0); + dwc_ddrphy_apb_wr0(4 * 0x54003, 0xc80); + dwc_ddrphy_apb_wr0(4 * 0x54004, 0x2); + dwc_ddrphy_apb_wr0(4 * 0x54005, ((LPDDR4_PHY_RON << 8) | LPDDR4_PHY_RTT)); + dwc_ddrphy_apb_wr0(4 * 0x54006, LPDDR4_PHY_VREF_VALUE); + dwc_ddrphy_apb_wr0(4 * 0x54007, 0x0); + dwc_ddrphy_apb_wr0(4 * 0x54008, 0x61); + dwc_ddrphy_apb_wr0(4 * 0x54009, LPDDR4_HDT_CTL_2D); + dwc_ddrphy_apb_wr0(4 * 0x5400a, 0x0); + dwc_ddrphy_apb_wr0(4 * 0x5400b, 0x2); + dwc_ddrphy_apb_wr0(4 * 0x5400c, 0x0); + dwc_ddrphy_apb_wr0(4 * 0x5400d, (LPDDR4_CATRAIN_3200_2d << 8)); + dwc_ddrphy_apb_wr0(4 * 0x5400e, 0x0); + dwc_ddrphy_apb_wr0(4 * 0x5400f, (LPDDR4_2D_SHARE << 8) | 0x00); + dwc_ddrphy_apb_wr0(4 * 0x54010, LPDDR4_2D_WEIGHT); + dwc_ddrphy_apb_wr0(4 * 0x54011, 0x0); + dwc_ddrphy_apb_wr0(4 * 0x54012, 0x310); + dwc_ddrphy_apb_wr0(4 * 0x54013, 0x0); + dwc_ddrphy_apb_wr0(4 * 0x54014, 0x0); + dwc_ddrphy_apb_wr0(4 * 0x54015, 0x0); + dwc_ddrphy_apb_wr0(4 * 0x54016, 0x0); + dwc_ddrphy_apb_wr0(4 * 0x54017, 0x0); + dwc_ddrphy_apb_wr0(4 * 0x54018, 0x0); + dwc_ddrphy_apb_wr0(4 * 0x54024, 0x5); + dwc_ddrphy_apb_wr0(4 * 0x54019, 0x2dd4); + dwc_ddrphy_apb_wr0(4 * 0x5401a, (((LPDDR4_RON) << 3) | 0x3)); + dwc_ddrphy_apb_wr0(4 * 0x5401b, ((LPDDR4_VREF_VALUE_CA << 8) | (LPDDR4_RTT_CA_BANK0 << 4) | LPDDR4_RTT_DQ)); + dwc_ddrphy_apb_wr0(4 * 0x5401c, ((LPDDR4_VREF_VALUE_DQ_RANK0 << 8) | 0x08)); + dwc_ddrphy_apb_wr0(4 * 0x5401d, 0x0); + dwc_ddrphy_apb_wr0(4 * 0x5401e, LPDDR4_MR22_RANK0); + dwc_ddrphy_apb_wr0(4 * 0x5401f, 0x2dd4); + dwc_ddrphy_apb_wr0(4 * 0x54020, (((LPDDR4_RON) << 3) | 0x3)); + dwc_ddrphy_apb_wr0(4 * 0x54021, ((LPDDR4_VREF_VALUE_CA << 8) | (LPDDR4_RTT_CA_BANK1 << 4) | LPDDR4_RTT_DQ)); + dwc_ddrphy_apb_wr0(4 * 0x54022, ((LPDDR4_VREF_VALUE_DQ_RANK1 << 8) | 0x08)); + dwc_ddrphy_apb_wr0(4 * 0x54023, 0x0); + dwc_ddrphy_apb_wr0(4 * 0x54024, LPDDR4_MR22_RANK1); + dwc_ddrphy_apb_wr0(4 * 0x54025, 0x0); + dwc_ddrphy_apb_wr0(4 * 0x54026, 0x0); + dwc_ddrphy_apb_wr0(4 * 0x54027, 0x0); + dwc_ddrphy_apb_wr0(4 * 0x54028, 0x0); + dwc_ddrphy_apb_wr0(4 * 0x54029, 0x0); + dwc_ddrphy_apb_wr0(4 * 0x5402a, 0x0); + dwc_ddrphy_apb_wr0(4 * 0x5402b, 0x1000); + dwc_ddrphy_apb_wr0(4 * 0x5402c, 0x3); + dwc_ddrphy_apb_wr0(4 * 0x5402d, 0x0); + dwc_ddrphy_apb_wr0(4 * 0x5402e, 0x0); + dwc_ddrphy_apb_wr0(4 * 0x5402f, 0x0); + dwc_ddrphy_apb_wr0(4 * 0x54030, 0x0); + dwc_ddrphy_apb_wr0(4 * 0x54031, 0x0); + dwc_ddrphy_apb_wr0(4 * 0x54032, 0xd400); + dwc_ddrphy_apb_wr0(4 * 0x54033, ((((LPDDR4_RON) << 3) | 0x3) << 8) | 0x2d); + dwc_ddrphy_apb_wr0(4 * 0x54034, (((LPDDR4_RTT_CA_BANK0 << 4) | LPDDR4_RTT_DQ) << 8)); + dwc_ddrphy_apb_wr0(4 * 0x54035, (0x0800|LPDDR4_VREF_VALUE_CA)); + dwc_ddrphy_apb_wr0(4 * 0x54036, LPDDR4_VREF_VALUE_DQ_RANK0); + dwc_ddrphy_apb_wr0(4 * 0x54037, (LPDDR4_MR22_RANK0 << 8)); + dwc_ddrphy_apb_wr0(4 * 0x54038, 0xd400); + dwc_ddrphy_apb_wr0(4 * 0x54039, ((((LPDDR4_RON) << 3) | 0x3) << 8) | 0x2d); + dwc_ddrphy_apb_wr0(4 * 0x5403a, (((LPDDR4_RTT_CA_BANK1 << 4) | LPDDR4_RTT_DQ) << 8)); + dwc_ddrphy_apb_wr0(4 * 0x5403b, (0x0800|LPDDR4_VREF_VALUE_CA)); + dwc_ddrphy_apb_wr0(4 * 0x5403c, LPDDR4_VREF_VALUE_DQ_RANK1); + dwc_ddrphy_apb_wr0(4 * 0x5403d, (LPDDR4_MR22_RANK1 << 8)); + dwc_ddrphy_apb_wr0(4 * 0x5403e, 0x0); + dwc_ddrphy_apb_wr0(4 * 0x5403f, 0x0); + dwc_ddrphy_apb_wr0(4 * 0x54040, 0x0); + dwc_ddrphy_apb_wr0(4 * 0x54041, 0x0); + dwc_ddrphy_apb_wr0(4 * 0x54042, 0x0); + dwc_ddrphy_apb_wr0(4 * 0x54043, 0x0); + dwc_ddrphy_apb_wr0(4 * 0x54044, 0x0); + dwc_ddrphy_apb_wr0(4 * 0xd0000, 0x1); + dwc_ddrphy_apb_wr0(4 * 0xd0000, 0x1); + dwc_ddrphy_apb_wr0(4 * 0xd0099, 0x9); + dwc_ddrphy_apb_wr0(4 * 0xd0099, 0x1); + dwc_ddrphy_apb_wr0(4 * 0xd0099, 0x0); /* wait for train complete */ - wait_ddrphy_training_complete(); + wait_ddrphy_training_complete1(); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x1); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x0); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x1); + dwc_ddrphy_apb_wr0(4 * 0xd0099, 0x1); + dwc_ddrphy_apb_wr0(4 * 0xd0000, 0x0); + dwc_ddrphy_apb_wr0(4 * 0xd0000, 0x1); /* Step (E) Set the PHY input clocks for pstate 1 */ dwc_ddrphy_phyinit_userCustom_E_setDfiClk (1); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x0); + dwc_ddrphy_apb_wr0(4 * 0xd0000, 0x0); ddr_load_train_code(FW_1D_IMAGE); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x1); + dwc_ddrphy_apb_wr0(4 * 0xd0000, 0x1); printf("pstate=1: set dfi clk done done\n"); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x0); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54000, 0x0); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54001, 0x0); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54002, 0x1); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54003, 0x29c); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54004, 0x2); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54005, ((LPDDR4_PHY_RON << 8) | LPDDR4_PHY_RTT)); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54006, LPDDR4_PHY_VREF_VALUE); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54007, 0x0); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54008, 0x121f); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54009, 0xc8); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400a, 0x0); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400b, 0x2); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400c, 0x0); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400d, 0x0); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400e, 0x0); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400f, 0x0); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54010, 0x0); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54011, 0x0); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54012, 0x310); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54013, 0x0); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54014, 0x0); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54015, 0x0); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54016, 0x0); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54017, 0x0); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54018, 0x0); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54019, 0x914); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401a, (((LPDDR4_RON) << 3) | 0x1)); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401b, ((LPDDR4_VREF_VALUE_CA << 8) | (LPDDR4_RTT_CA_BANK0 << 4) | LPDDR4_RTT_DQ)); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401c, ((LPDDR4_VREF_VALUE_DQ_RANK0 << 8) | 0x08)); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401e, 0x6); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401f, 0x914); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54020, (((LPDDR4_RON) << 3) | 0x1)); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54021, ((LPDDR4_VREF_VALUE_CA << 8) | (LPDDR4_RTT_CA_BANK1 << 4) | LPDDR4_RTT_DQ)); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54022, ((LPDDR4_VREF_VALUE_DQ_RANK1 << 8) | 0x08)); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54023, 0x0); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54024, LPDDR4_MR22_RANK1); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54025, 0x0); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54026, 0x0); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54027, 0x0); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54028, 0x0); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54029, 0x0); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402a, 0x0); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402b, 0x1000); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402c, 0x3); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402d, 0x0); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402e, 0x0); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402f, 0x0); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54030, 0x0); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54031, 0x0); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54032, 0x1400); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54033, ((((LPDDR4_RON) << 3) | 0x1) << 8) | 0x09); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54034, (((LPDDR4_RTT_CA_BANK0 << 4) | LPDDR4_RTT_DQ) << 8)); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54035, (0x0800|LPDDR4_VREF_VALUE_CA)); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54036, LPDDR4_VREF_VALUE_DQ_RANK0); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54037, 0x600); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54038, 0x1400); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54039, ((((LPDDR4_RON) << 3) | 0x1) << 8) | 0x09); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403a, (((LPDDR4_RTT_CA_BANK1 << 4) | LPDDR4_RTT_DQ) << 8)); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403b, (0x0800|LPDDR4_VREF_VALUE_CA)); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403c, LPDDR4_VREF_VALUE_DQ_RANK1); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403d, (LPDDR4_MR22_RANK1 << 8)); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403e, 0x0); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403f, 0x0); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54040, 0x0); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54041, 0x0); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54042, 0x0); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54043, 0x0); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x1); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x1); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x9); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x1); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x0); + dwc_ddrphy_apb_wr0(4 * 0xd0000, 0x0); + dwc_ddrphy_apb_wr0(4 * 0x54000, 0x0); + dwc_ddrphy_apb_wr0(4 * 0x54001, 0x0); + dwc_ddrphy_apb_wr0(4 * 0x54002, 0x1); + dwc_ddrphy_apb_wr0(4 * 0x54003, 0x29c); + dwc_ddrphy_apb_wr0(4 * 0x54004, 0x2); + dwc_ddrphy_apb_wr0(4 * 0x54005, ((LPDDR4_PHY_RON << 8) | LPDDR4_PHY_RTT)); + dwc_ddrphy_apb_wr0(4 * 0x54006, LPDDR4_PHY_VREF_VALUE); + dwc_ddrphy_apb_wr0(4 * 0x54007, 0x0); + dwc_ddrphy_apb_wr0(4 * 0x54008, 0x121f); + dwc_ddrphy_apb_wr0(4 * 0x54009, 0xc8); + dwc_ddrphy_apb_wr0(4 * 0x5400a, 0x0); + dwc_ddrphy_apb_wr0(4 * 0x5400b, 0x2); + dwc_ddrphy_apb_wr0(4 * 0x5400c, 0x0); + dwc_ddrphy_apb_wr0(4 * 0x5400d, 0x0); + dwc_ddrphy_apb_wr0(4 * 0x5400e, 0x0); + dwc_ddrphy_apb_wr0(4 * 0x5400f, 0x0); + dwc_ddrphy_apb_wr0(4 * 0x54010, 0x0); + dwc_ddrphy_apb_wr0(4 * 0x54011, 0x0); + dwc_ddrphy_apb_wr0(4 * 0x54012, 0x310); + dwc_ddrphy_apb_wr0(4 * 0x54013, 0x0); + dwc_ddrphy_apb_wr0(4 * 0x54014, 0x0); + dwc_ddrphy_apb_wr0(4 * 0x54015, 0x0); + dwc_ddrphy_apb_wr0(4 * 0x54016, 0x0); + dwc_ddrphy_apb_wr0(4 * 0x54017, 0x0); + dwc_ddrphy_apb_wr0(4 * 0x54018, 0x0); + dwc_ddrphy_apb_wr0(4 * 0x54019, 0x914); + dwc_ddrphy_apb_wr0(4 * 0x5401a, (((LPDDR4_RON) << 3) | 0x1)); + dwc_ddrphy_apb_wr0(4 * 0x5401b, ((LPDDR4_VREF_VALUE_CA << 8) | (LPDDR4_RTT_CA_BANK0 << 4) | LPDDR4_RTT_DQ)); + dwc_ddrphy_apb_wr0(4 * 0x5401c, ((LPDDR4_VREF_VALUE_DQ_RANK0 << 8) | 0x08)); + dwc_ddrphy_apb_wr0(4 * 0x5401e, 0x6); + dwc_ddrphy_apb_wr0(4 * 0x5401f, 0x914); + dwc_ddrphy_apb_wr0(4 * 0x54020, (((LPDDR4_RON) << 3) | 0x1)); + dwc_ddrphy_apb_wr0(4 * 0x54021, ((LPDDR4_VREF_VALUE_CA << 8) | (LPDDR4_RTT_CA_BANK1 << 4) | LPDDR4_RTT_DQ)); + dwc_ddrphy_apb_wr0(4 * 0x54022, ((LPDDR4_VREF_VALUE_DQ_RANK1 << 8) | 0x08)); + dwc_ddrphy_apb_wr0(4 * 0x54023, 0x0); + dwc_ddrphy_apb_wr0(4 * 0x54024, LPDDR4_MR22_RANK1); + dwc_ddrphy_apb_wr0(4 * 0x54025, 0x0); + dwc_ddrphy_apb_wr0(4 * 0x54026, 0x0); + dwc_ddrphy_apb_wr0(4 * 0x54027, 0x0); + dwc_ddrphy_apb_wr0(4 * 0x54028, 0x0); + dwc_ddrphy_apb_wr0(4 * 0x54029, 0x0); + dwc_ddrphy_apb_wr0(4 * 0x5402a, 0x0); + dwc_ddrphy_apb_wr0(4 * 0x5402b, 0x1000); + dwc_ddrphy_apb_wr0(4 * 0x5402c, 0x3); + dwc_ddrphy_apb_wr0(4 * 0x5402d, 0x0); + dwc_ddrphy_apb_wr0(4 * 0x5402e, 0x0); + dwc_ddrphy_apb_wr0(4 * 0x5402f, 0x0); + dwc_ddrphy_apb_wr0(4 * 0x54030, 0x0); + dwc_ddrphy_apb_wr0(4 * 0x54031, 0x0); + dwc_ddrphy_apb_wr0(4 * 0x54032, 0x1400); + dwc_ddrphy_apb_wr0(4 * 0x54033, ((((LPDDR4_RON) << 3) | 0x1) << 8) | 0x09); + dwc_ddrphy_apb_wr0(4 * 0x54034, (((LPDDR4_RTT_CA_BANK0 << 4) | LPDDR4_RTT_DQ) << 8)); + dwc_ddrphy_apb_wr0(4 * 0x54035, (0x0800|LPDDR4_VREF_VALUE_CA)); + dwc_ddrphy_apb_wr0(4 * 0x54036, LPDDR4_VREF_VALUE_DQ_RANK0); + dwc_ddrphy_apb_wr0(4 * 0x54037, 0x600); + dwc_ddrphy_apb_wr0(4 * 0x54038, 0x1400); + dwc_ddrphy_apb_wr0(4 * 0x54039, ((((LPDDR4_RON) << 3) | 0x1) << 8) | 0x09); + dwc_ddrphy_apb_wr0(4 * 0x5403a, (((LPDDR4_RTT_CA_BANK1 << 4) | LPDDR4_RTT_DQ) << 8)); + dwc_ddrphy_apb_wr0(4 * 0x5403b, (0x0800|LPDDR4_VREF_VALUE_CA)); + dwc_ddrphy_apb_wr0(4 * 0x5403c, LPDDR4_VREF_VALUE_DQ_RANK1); + dwc_ddrphy_apb_wr0(4 * 0x5403d, (LPDDR4_MR22_RANK1 << 8)); + dwc_ddrphy_apb_wr0(4 * 0x5403e, 0x0); + dwc_ddrphy_apb_wr0(4 * 0x5403f, 0x0); + dwc_ddrphy_apb_wr0(4 * 0x54040, 0x0); + dwc_ddrphy_apb_wr0(4 * 0x54041, 0x0); + dwc_ddrphy_apb_wr0(4 * 0x54042, 0x0); + dwc_ddrphy_apb_wr0(4 * 0x54043, 0x0); + dwc_ddrphy_apb_wr0(4 * 0xd0000, 0x1); + dwc_ddrphy_apb_wr0(4 * 0xd0000, 0x1); + dwc_ddrphy_apb_wr0(4 * 0xd0099, 0x9); + dwc_ddrphy_apb_wr0(4 * 0xd0099, 0x1); + dwc_ddrphy_apb_wr0(4 * 0xd0099, 0x0); /* wait for train complete */ - wait_ddrphy_training_complete(); + wait_ddrphy_training_complete1(); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x1); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x0); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x1); + dwc_ddrphy_apb_wr0(4 * 0xd0099, 0x1); + dwc_ddrphy_apb_wr0(4 * 0xd0000, 0x0); + dwc_ddrphy_apb_wr0(4 * 0xd0000, 0x1); /* (I) Load PHY Init Engine Image */ printf("Load 201711 PIE\n"); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x0); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90000, 0x10); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90001, 0x400); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90002, 0x10e); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90003, 0x0); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90004, 0x0); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90005, 0x8); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90029, 0xb); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9002a, 0x480); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9002b, 0x109); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9002c, 0x8); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9002d, 0x448); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9002e, 0x139); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9002f, 0x8); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90030, 0x478); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90031, 0x109); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90032, 0x0); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90033, 0xe8); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90034, 0x109); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90035, 0x2); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90036, 0x10); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90037, 0x139); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90038, 0xb); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90039, 0x7c0); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9003a, 0x139); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9003b, 0x44); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9003c, 0x630); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9003d, 0x159); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9003e, 0x14f); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9003f, 0x630); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90040, 0x159); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90041, 0x47); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90042, 0x630); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90043, 0x149); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90044, 0x4f); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90045, 0x630); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90046, 0x179); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90047, 0x8); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90048, 0xe0); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90049, 0x109); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9004a, 0x0); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9004b, 0x7c8); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9004c, 0x109); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9004d, 0x0); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9004e, 0x1); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9004f, 0x8); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90050, 0x0); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90051, 0x45a); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90052, 0x9); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90053, 0x0); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90054, 0x448); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90055, 0x109); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90056, 0x40); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90057, 0x630); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90058, 0x179); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90059, 0x1); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9005a, 0x618); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9005b, 0x109); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9005c, 0x40c0); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9005d, 0x630); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9005e, 0x149); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9005f, 0x8); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90060, 0x4); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90061, 0x48); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90062, 0x4040); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90063, 0x630); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90064, 0x149); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90065, 0x0); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90066, 0x4); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90067, 0x48); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90068, 0x40); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90069, 0x630); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9006a, 0x149); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9006b, 0x10); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9006c, 0x4); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9006d, 0x18); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9006e, 0x0); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9006f, 0x4); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90070, 0x78); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90071, 0x549); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90072, 0x630); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90073, 0x159); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90074, 0xd49); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90075, 0x630); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90076, 0x159); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90077, 0x94a); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90078, 0x630); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90079, 0x159); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9007a, 0x441); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9007b, 0x630); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9007c, 0x149); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9007d, 0x42); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9007e, 0x630); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9007f, 0x149); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90080, 0x1); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90081, 0x630); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90082, 0x149); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90083, 0x0); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90084, 0xe0); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90085, 0x109); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90086, 0xa); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90087, 0x10); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90088, 0x109); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90089, 0x9); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9008a, 0x3c0); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9008b, 0x149); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9008c, 0x9); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9008d, 0x3c0); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9008e, 0x159); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9008f, 0x18); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90090, 0x10); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90091, 0x109); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90092, 0x0); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90093, 0x3c0); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90094, 0x109); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90095, 0x18); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90096, 0x4); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90097, 0x48); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90098, 0x18); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90099, 0x4); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9009a, 0x58); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9009b, 0xa); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9009c, 0x10); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9009d, 0x109); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9009e, 0x2); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9009f, 0x10); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900a0, 0x109); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900a1, 0x5); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900a2, 0x7c0); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900a3, 0x109); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900a4, 0xd); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900a5, 0x7c0); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900a6, 0x109); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900a7, 0x4); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900a8, 0x7c0); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900a9, 0x109); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40000, 0x811); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40020, 0x880); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40040, 0x0); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40060, 0x0); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40001, 0x4008); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40021, 0x83); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40041, 0x4f); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40061, 0x0); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40002, 0x4040); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40022, 0x83); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40042, 0x51); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40062, 0x0); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40003, 0x811); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40023, 0x880); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40043, 0x0); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40063, 0x0); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40004, 0x720); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40024, 0xf); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40044, 0x1740); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40064, 0x0); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40005, 0x16); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40025, 0x83); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40045, 0x4b); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40065, 0x0); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40006, 0x716); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40026, 0xf); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40046, 0x2001); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40066, 0x0); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40007, 0x716); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40027, 0xf); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40047, 0x2800); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40067, 0x0); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40008, 0x716); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40028, 0xf); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40048, 0xf00); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40068, 0x0); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40009, 0x720); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40029, 0xf); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40049, 0x1400); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40069, 0x0); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4000a, 0xe08); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4002a, 0xc15); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4004a, 0x0); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4006a, 0x0); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4000b, 0x623); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4002b, 0x15); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4004b, 0x0); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4006b, 0x0); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4000c, 0x4028); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4002c, 0x80); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4004c, 0x0); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4006c, 0x0); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4000d, 0xe08); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4002d, 0xc1a); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4004d, 0x0); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4006d, 0x0); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4000e, 0x623); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4002e, 0x1a); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4004e, 0x0); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4006e, 0x0); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4000f, 0x4040); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4002f, 0x80); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4004f, 0x0); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4006f, 0x0); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40010, 0x2604); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40030, 0x15); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40050, 0x0); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40070, 0x0); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40011, 0x708); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40031, 0x5); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40051, 0x0); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40071, 0x2002); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40012, 0x8); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40032, 0x80); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40052, 0x0); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40072, 0x0); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40013, 0x2604); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40033, 0x1a); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40053, 0x0); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40073, 0x0); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40014, 0x708); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40034, 0xa); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40054, 0x0); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40074, 0x2002); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40015, 0x4040); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40035, 0x80); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40055, 0x0); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40075, 0x0); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40016, 0x60a); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40036, 0x15); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40056, 0x1200); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40076, 0x0); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40017, 0x61a); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40037, 0x15); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40057, 0x1300); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40077, 0x0); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40018, 0x60a); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40038, 0x1a); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40058, 0x1200); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40078, 0x0); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40019, 0x642); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40039, 0x1a); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40059, 0x1300); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40079, 0x0); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4001a, 0x4808); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4003a, 0x880); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4005a, 0x0); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4007a, 0x0); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900aa, 0x0); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900ab, 0x790); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900ac, 0x11a); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900ad, 0x8); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900ae, 0x7aa); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900af, 0x2a); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900b0, 0x10); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900b1, 0x7b2); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900b2, 0x2a); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900b3, 0x0); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900b4, 0x7c8); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900b5, 0x109); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900b6, 0x10); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900b7, 0x10); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900b8, 0x109); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900b9, 0x10); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900ba, 0x2a8); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900bb, 0x129); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900bc, 0x8); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900bd, 0x370); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900be, 0x129); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900bf, 0xa); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900c0, 0x3c8); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900c1, 0x1a9); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900c2, 0xc); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900c3, 0x408); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900c4, 0x199); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900c5, 0x14); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900c6, 0x790); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900c7, 0x11a); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900c8, 0x8); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900c9, 0x4); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900ca, 0x18); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900cb, 0xe); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900cc, 0x408); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900cd, 0x199); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900ce, 0x8); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900cf, 0x8568); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900d0, 0x108); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900d1, 0x18); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900d2, 0x790); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900d3, 0x16a); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900d4, 0x8); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900d5, 0x1d8); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900d6, 0x169); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900d7, 0x10); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900d8, 0x8558); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900d9, 0x168); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900da, 0x70); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900db, 0x788); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900dc, 0x16a); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900dd, 0x1ff8); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900de, 0x85a8); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900df, 0x1e8); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900e0, 0x50); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900e1, 0x798); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900e2, 0x16a); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900e3, 0x60); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900e4, 0x7a0); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900e5, 0x16a); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900e6, 0x8); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900e7, 0x8310); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900e8, 0x168); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900e9, 0x8); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900ea, 0xa310); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900eb, 0x168); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900ec, 0xa); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900ed, 0x408); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900ee, 0x169); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900ef, 0x6e); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900f0, 0x0); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900f1, 0x68); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900f2, 0x0); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900f3, 0x408); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900f4, 0x169); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900f5, 0x0); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900f6, 0x8310); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900f7, 0x168); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900f8, 0x0); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900f9, 0xa310); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900fa, 0x168); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900fb, 0x1ff8); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900fc, 0x85a8); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900fd, 0x1e8); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900fe, 0x68); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900ff, 0x798); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90100, 0x16a); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90101, 0x78); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90102, 0x7a0); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90103, 0x16a); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90104, 0x68); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90105, 0x790); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90106, 0x16a); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90107, 0x8); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90108, 0x8b10); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90109, 0x168); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9010a, 0x8); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9010b, 0xab10); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9010c, 0x168); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9010d, 0xa); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9010e, 0x408); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9010f, 0x169); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90110, 0x58); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90111, 0x0); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90112, 0x68); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90113, 0x0); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90114, 0x408); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90115, 0x169); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90116, 0x0); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90117, 0x8b10); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90118, 0x168); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90119, 0x0); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9011a, 0xab10); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9011b, 0x168); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9011c, 0x0); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9011d, 0x1d8); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9011e, 0x169); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9011f, 0x80); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90120, 0x790); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90121, 0x16a); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90122, 0x18); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90123, 0x7aa); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90124, 0x6a); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90125, 0xa); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90126, 0x0); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90127, 0x1e9); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90128, 0x8); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90129, 0x8080); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9012a, 0x108); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9012b, 0xf); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9012c, 0x408); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9012d, 0x169); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9012e, 0xc); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9012f, 0x0); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90130, 0x68); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90131, 0x9); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90132, 0x0); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90133, 0x1a9); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90134, 0x0); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90135, 0x408); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90136, 0x169); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90137, 0x0); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90138, 0x8080); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90139, 0x108); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9013a, 0x8); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9013b, 0x7aa); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9013c, 0x6a); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9013d, 0x0); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9013e, 0x8568); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9013f, 0x108); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90140, 0xb7); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90141, 0x790); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90142, 0x16a); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90143, 0x1f); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90144, 0x0); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90145, 0x68); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90146, 0x8); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90147, 0x8558); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90148, 0x168); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90149, 0xf); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9014a, 0x408); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9014b, 0x169); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9014c, 0xc); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9014d, 0x0); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9014e, 0x68); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9014f, 0x0); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90150, 0x408); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90151, 0x169); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90152, 0x0); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90153, 0x8558); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90154, 0x168); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90155, 0x8); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90156, 0x3c8); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90157, 0x1a9); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90158, 0x3); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90159, 0x370); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9015a, 0x129); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9015b, 0x20); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9015c, 0x2aa); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9015d, 0x9); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9015e, 0x0); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9015f, 0x400); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90160, 0x10e); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90161, 0x8); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90162, 0xe8); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90163, 0x109); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90164, 0x0); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90165, 0x8140); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90166, 0x10c); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90167, 0x10); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90168, 0x8138); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90169, 0x10c); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9016a, 0x8); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9016b, 0x7c8); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9016c, 0x101); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9016d, 0x8); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9016e, 0x0); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9016f, 0x8); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90170, 0x8); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90171, 0x448); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90172, 0x109); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90173, 0xf); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90174, 0x7c0); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90175, 0x109); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90176, 0x0); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90177, 0xe8); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90178, 0x109); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90179, 0x47); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9017a, 0x630); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9017b, 0x109); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9017c, 0x8); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9017d, 0x618); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9017e, 0x109); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9017f, 0x8); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90180, 0xe0); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90181, 0x109); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90182, 0x0); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90183, 0x7c8); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90184, 0x109); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90185, 0x8); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90186, 0x8140); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90187, 0x10c); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90188, 0x0); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90189, 0x1); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9018a, 0x8); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9018b, 0x8); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9018c, 0x4); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9018d, 0x8); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9018e, 0x8); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9018f, 0x7c8); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90190, 0x101); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90006, 0x0); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90007, 0x0); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90008, 0x8); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90009, 0x0); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9000a, 0x0); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9000b, 0x0); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd00e7, 0x400); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90017, 0x0); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9001f, 0x2b); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90026, 0x6c); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x400d0, 0x0); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x400d1, 0x101); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x400d2, 0x105); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x400d3, 0x107); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x400d4, 0x10f); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x400d5, 0x202); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x400d6, 0x20a); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x400d7, 0x20b); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x2003a, 0x2); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x2000b, 0x64); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x2000c, 0xc8); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x2000d, 0x7d0); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x2000e, 0x2c); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x12000b, 0x14); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x12000c, 0x29); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x12000d, 0x1a1); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x12000e, 0x10); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x22000b, 0x3); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x22000c, 0x6); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x22000d, 0x3e); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x22000e, 0x10); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9000c, 0x0); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9000d, 0x173); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9000e, 0x60); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9000f, 0x6110); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90010, 0x2152); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90011, 0xdfbd); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90012, 0x60); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90013, 0x6152); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x20010, 0x5a); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x20011, 0x3); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40080, 0xe0); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40081, 0x12); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40082, 0xe0); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40083, 0x12); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40084, 0xe0); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40085, 0x12); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x140080, 0xe0); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x140081, 0x12); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x140082, 0xe0); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x140083, 0x12); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x140084, 0xe0); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x140085, 0x12); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x240080, 0xe0); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x240081, 0x12); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x240082, 0xe0); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x240083, 0x12); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x240084, 0xe0); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x240085, 0x12); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x400fd, 0xf); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x10011, 0x1); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x10012, 0x1); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x10013, 0x180); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x10018, 0x1); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x10002, 0x6209); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x100b2, 0x1); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x101b4, 0x1); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x102b4, 0x1); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x103b4, 0x1); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x104b4, 0x1); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x105b4, 0x1); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x106b4, 0x1); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x107b4, 0x1); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x108b4, 0x1); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x11011, 0x1); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x11012, 0x1); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x11013, 0x180); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x11018, 0x1); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x11002, 0x6209); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x110b2, 0x1); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x111b4, 0x1); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x112b4, 0x1); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x113b4, 0x1); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x114b4, 0x1); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x115b4, 0x1); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x116b4, 0x1); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x117b4, 0x1); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x118b4, 0x1); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x12011, 0x1); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x12012, 0x1); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x12013, 0x180); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x12018, 0x1); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x12002, 0x6209); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x120b2, 0x1); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x121b4, 0x1); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x122b4, 0x1); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x123b4, 0x1); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x124b4, 0x1); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x125b4, 0x1); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x126b4, 0x1); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x127b4, 0x1); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x128b4, 0x1); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x13011, 0x1); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x13012, 0x1); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x13013, 0x180); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x13018, 0x1); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x13002, 0x6209); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x130b2, 0x1); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x131b4, 0x1); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x132b4, 0x1); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x133b4, 0x1); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x134b4, 0x1); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x135b4, 0x1); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x136b4, 0x1); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x137b4, 0x1); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x138b4, 0x1); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x20089, 0x1); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x20088, 0x19); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xc0080, 0x2); - dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x1); + dwc_ddrphy_apb_wr0(4 * 0xd0000, 0x0); + dwc_ddrphy_apb_wr0(4 * 0x90000, 0x10); + dwc_ddrphy_apb_wr0(4 * 0x90001, 0x400); + dwc_ddrphy_apb_wr0(4 * 0x90002, 0x10e); + dwc_ddrphy_apb_wr0(4 * 0x90003, 0x0); + dwc_ddrphy_apb_wr0(4 * 0x90004, 0x0); + dwc_ddrphy_apb_wr0(4 * 0x90005, 0x8); + dwc_ddrphy_apb_wr0(4 * 0x90029, 0xb); + dwc_ddrphy_apb_wr0(4 * 0x9002a, 0x480); + dwc_ddrphy_apb_wr0(4 * 0x9002b, 0x109); + dwc_ddrphy_apb_wr0(4 * 0x9002c, 0x8); + dwc_ddrphy_apb_wr0(4 * 0x9002d, 0x448); + dwc_ddrphy_apb_wr0(4 * 0x9002e, 0x139); + dwc_ddrphy_apb_wr0(4 * 0x9002f, 0x8); + dwc_ddrphy_apb_wr0(4 * 0x90030, 0x478); + dwc_ddrphy_apb_wr0(4 * 0x90031, 0x109); + dwc_ddrphy_apb_wr0(4 * 0x90032, 0x0); + dwc_ddrphy_apb_wr0(4 * 0x90033, 0xe8); + dwc_ddrphy_apb_wr0(4 * 0x90034, 0x109); + dwc_ddrphy_apb_wr0(4 * 0x90035, 0x2); + dwc_ddrphy_apb_wr0(4 * 0x90036, 0x10); + dwc_ddrphy_apb_wr0(4 * 0x90037, 0x139); + dwc_ddrphy_apb_wr0(4 * 0x90038, 0xb); + dwc_ddrphy_apb_wr0(4 * 0x90039, 0x7c0); + dwc_ddrphy_apb_wr0(4 * 0x9003a, 0x139); + dwc_ddrphy_apb_wr0(4 * 0x9003b, 0x44); + dwc_ddrphy_apb_wr0(4 * 0x9003c, 0x630); + dwc_ddrphy_apb_wr0(4 * 0x9003d, 0x159); + dwc_ddrphy_apb_wr0(4 * 0x9003e, 0x14f); + dwc_ddrphy_apb_wr0(4 * 0x9003f, 0x630); + dwc_ddrphy_apb_wr0(4 * 0x90040, 0x159); + dwc_ddrphy_apb_wr0(4 * 0x90041, 0x47); + dwc_ddrphy_apb_wr0(4 * 0x90042, 0x630); + dwc_ddrphy_apb_wr0(4 * 0x90043, 0x149); + dwc_ddrphy_apb_wr0(4 * 0x90044, 0x4f); + dwc_ddrphy_apb_wr0(4 * 0x90045, 0x630); + dwc_ddrphy_apb_wr0(4 * 0x90046, 0x179); + dwc_ddrphy_apb_wr0(4 * 0x90047, 0x8); + dwc_ddrphy_apb_wr0(4 * 0x90048, 0xe0); + dwc_ddrphy_apb_wr0(4 * 0x90049, 0x109); + dwc_ddrphy_apb_wr0(4 * 0x9004a, 0x0); + dwc_ddrphy_apb_wr0(4 * 0x9004b, 0x7c8); + dwc_ddrphy_apb_wr0(4 * 0x9004c, 0x109); + dwc_ddrphy_apb_wr0(4 * 0x9004d, 0x0); + dwc_ddrphy_apb_wr0(4 * 0x9004e, 0x1); + dwc_ddrphy_apb_wr0(4 * 0x9004f, 0x8); + dwc_ddrphy_apb_wr0(4 * 0x90050, 0x0); + dwc_ddrphy_apb_wr0(4 * 0x90051, 0x45a); + dwc_ddrphy_apb_wr0(4 * 0x90052, 0x9); + dwc_ddrphy_apb_wr0(4 * 0x90053, 0x0); + dwc_ddrphy_apb_wr0(4 * 0x90054, 0x448); + dwc_ddrphy_apb_wr0(4 * 0x90055, 0x109); + dwc_ddrphy_apb_wr0(4 * 0x90056, 0x40); + dwc_ddrphy_apb_wr0(4 * 0x90057, 0x630); + dwc_ddrphy_apb_wr0(4 * 0x90058, 0x179); + dwc_ddrphy_apb_wr0(4 * 0x90059, 0x1); + dwc_ddrphy_apb_wr0(4 * 0x9005a, 0x618); + dwc_ddrphy_apb_wr0(4 * 0x9005b, 0x109); + dwc_ddrphy_apb_wr0(4 * 0x9005c, 0x40c0); + dwc_ddrphy_apb_wr0(4 * 0x9005d, 0x630); + dwc_ddrphy_apb_wr0(4 * 0x9005e, 0x149); + dwc_ddrphy_apb_wr0(4 * 0x9005f, 0x8); + dwc_ddrphy_apb_wr0(4 * 0x90060, 0x4); + dwc_ddrphy_apb_wr0(4 * 0x90061, 0x48); + dwc_ddrphy_apb_wr0(4 * 0x90062, 0x4040); + dwc_ddrphy_apb_wr0(4 * 0x90063, 0x630); + dwc_ddrphy_apb_wr0(4 * 0x90064, 0x149); + dwc_ddrphy_apb_wr0(4 * 0x90065, 0x0); + dwc_ddrphy_apb_wr0(4 * 0x90066, 0x4); + dwc_ddrphy_apb_wr0(4 * 0x90067, 0x48); + dwc_ddrphy_apb_wr0(4 * 0x90068, 0x40); + dwc_ddrphy_apb_wr0(4 * 0x90069, 0x630); + dwc_ddrphy_apb_wr0(4 * 0x9006a, 0x149); + dwc_ddrphy_apb_wr0(4 * 0x9006b, 0x10); + dwc_ddrphy_apb_wr0(4 * 0x9006c, 0x4); + dwc_ddrphy_apb_wr0(4 * 0x9006d, 0x18); + dwc_ddrphy_apb_wr0(4 * 0x9006e, 0x0); + dwc_ddrphy_apb_wr0(4 * 0x9006f, 0x4); + dwc_ddrphy_apb_wr0(4 * 0x90070, 0x78); + dwc_ddrphy_apb_wr0(4 * 0x90071, 0x549); + dwc_ddrphy_apb_wr0(4 * 0x90072, 0x630); + dwc_ddrphy_apb_wr0(4 * 0x90073, 0x159); + dwc_ddrphy_apb_wr0(4 * 0x90074, 0xd49); + dwc_ddrphy_apb_wr0(4 * 0x90075, 0x630); + dwc_ddrphy_apb_wr0(4 * 0x90076, 0x159); + dwc_ddrphy_apb_wr0(4 * 0x90077, 0x94a); + dwc_ddrphy_apb_wr0(4 * 0x90078, 0x630); + dwc_ddrphy_apb_wr0(4 * 0x90079, 0x159); + dwc_ddrphy_apb_wr0(4 * 0x9007a, 0x441); + dwc_ddrphy_apb_wr0(4 * 0x9007b, 0x630); + dwc_ddrphy_apb_wr0(4 * 0x9007c, 0x149); + dwc_ddrphy_apb_wr0(4 * 0x9007d, 0x42); + dwc_ddrphy_apb_wr0(4 * 0x9007e, 0x630); + dwc_ddrphy_apb_wr0(4 * 0x9007f, 0x149); + dwc_ddrphy_apb_wr0(4 * 0x90080, 0x1); + dwc_ddrphy_apb_wr0(4 * 0x90081, 0x630); + dwc_ddrphy_apb_wr0(4 * 0x90082, 0x149); + dwc_ddrphy_apb_wr0(4 * 0x90083, 0x0); + dwc_ddrphy_apb_wr0(4 * 0x90084, 0xe0); + dwc_ddrphy_apb_wr0(4 * 0x90085, 0x109); + dwc_ddrphy_apb_wr0(4 * 0x90086, 0xa); + dwc_ddrphy_apb_wr0(4 * 0x90087, 0x10); + dwc_ddrphy_apb_wr0(4 * 0x90088, 0x109); + dwc_ddrphy_apb_wr0(4 * 0x90089, 0x9); + dwc_ddrphy_apb_wr0(4 * 0x9008a, 0x3c0); + dwc_ddrphy_apb_wr0(4 * 0x9008b, 0x149); + dwc_ddrphy_apb_wr0(4 * 0x9008c, 0x9); + dwc_ddrphy_apb_wr0(4 * 0x9008d, 0x3c0); + dwc_ddrphy_apb_wr0(4 * 0x9008e, 0x159); + dwc_ddrphy_apb_wr0(4 * 0x9008f, 0x18); + dwc_ddrphy_apb_wr0(4 * 0x90090, 0x10); + dwc_ddrphy_apb_wr0(4 * 0x90091, 0x109); + dwc_ddrphy_apb_wr0(4 * 0x90092, 0x0); + dwc_ddrphy_apb_wr0(4 * 0x90093, 0x3c0); + dwc_ddrphy_apb_wr0(4 * 0x90094, 0x109); + dwc_ddrphy_apb_wr0(4 * 0x90095, 0x18); + dwc_ddrphy_apb_wr0(4 * 0x90096, 0x4); + dwc_ddrphy_apb_wr0(4 * 0x90097, 0x48); + dwc_ddrphy_apb_wr0(4 * 0x90098, 0x18); + dwc_ddrphy_apb_wr0(4 * 0x90099, 0x4); + dwc_ddrphy_apb_wr0(4 * 0x9009a, 0x58); + dwc_ddrphy_apb_wr0(4 * 0x9009b, 0xa); + dwc_ddrphy_apb_wr0(4 * 0x9009c, 0x10); + dwc_ddrphy_apb_wr0(4 * 0x9009d, 0x109); + dwc_ddrphy_apb_wr0(4 * 0x9009e, 0x2); + dwc_ddrphy_apb_wr0(4 * 0x9009f, 0x10); + dwc_ddrphy_apb_wr0(4 * 0x900a0, 0x109); + dwc_ddrphy_apb_wr0(4 * 0x900a1, 0x5); + dwc_ddrphy_apb_wr0(4 * 0x900a2, 0x7c0); + dwc_ddrphy_apb_wr0(4 * 0x900a3, 0x109); + dwc_ddrphy_apb_wr0(4 * 0x900a4, 0xd); + dwc_ddrphy_apb_wr0(4 * 0x900a5, 0x7c0); + dwc_ddrphy_apb_wr0(4 * 0x900a6, 0x109); + dwc_ddrphy_apb_wr0(4 * 0x900a7, 0x4); + dwc_ddrphy_apb_wr0(4 * 0x900a8, 0x7c0); + dwc_ddrphy_apb_wr0(4 * 0x900a9, 0x109); + dwc_ddrphy_apb_wr0(4 * 0x40000, 0x811); + dwc_ddrphy_apb_wr0(4 * 0x40020, 0x880); + dwc_ddrphy_apb_wr0(4 * 0x40040, 0x0); + dwc_ddrphy_apb_wr0(4 * 0x40060, 0x0); + dwc_ddrphy_apb_wr0(4 * 0x40001, 0x4008); + dwc_ddrphy_apb_wr0(4 * 0x40021, 0x83); + dwc_ddrphy_apb_wr0(4 * 0x40041, 0x4f); + dwc_ddrphy_apb_wr0(4 * 0x40061, 0x0); + dwc_ddrphy_apb_wr0(4 * 0x40002, 0x4040); + dwc_ddrphy_apb_wr0(4 * 0x40022, 0x83); + dwc_ddrphy_apb_wr0(4 * 0x40042, 0x51); + dwc_ddrphy_apb_wr0(4 * 0x40062, 0x0); + dwc_ddrphy_apb_wr0(4 * 0x40003, 0x811); + dwc_ddrphy_apb_wr0(4 * 0x40023, 0x880); + dwc_ddrphy_apb_wr0(4 * 0x40043, 0x0); + dwc_ddrphy_apb_wr0(4 * 0x40063, 0x0); + dwc_ddrphy_apb_wr0(4 * 0x40004, 0x720); + dwc_ddrphy_apb_wr0(4 * 0x40024, 0xf); + dwc_ddrphy_apb_wr0(4 * 0x40044, 0x1740); + dwc_ddrphy_apb_wr0(4 * 0x40064, 0x0); + dwc_ddrphy_apb_wr0(4 * 0x40005, 0x16); + dwc_ddrphy_apb_wr0(4 * 0x40025, 0x83); + dwc_ddrphy_apb_wr0(4 * 0x40045, 0x4b); + dwc_ddrphy_apb_wr0(4 * 0x40065, 0x0); + dwc_ddrphy_apb_wr0(4 * 0x40006, 0x716); + dwc_ddrphy_apb_wr0(4 * 0x40026, 0xf); + dwc_ddrphy_apb_wr0(4 * 0x40046, 0x2001); + dwc_ddrphy_apb_wr0(4 * 0x40066, 0x0); + dwc_ddrphy_apb_wr0(4 * 0x40007, 0x716); + dwc_ddrphy_apb_wr0(4 * 0x40027, 0xf); + dwc_ddrphy_apb_wr0(4 * 0x40047, 0x2800); + dwc_ddrphy_apb_wr0(4 * 0x40067, 0x0); + dwc_ddrphy_apb_wr0(4 * 0x40008, 0x716); + dwc_ddrphy_apb_wr0(4 * 0x40028, 0xf); + dwc_ddrphy_apb_wr0(4 * 0x40048, 0xf00); + dwc_ddrphy_apb_wr0(4 * 0x40068, 0x0); + dwc_ddrphy_apb_wr0(4 * 0x40009, 0x720); + dwc_ddrphy_apb_wr0(4 * 0x40029, 0xf); + dwc_ddrphy_apb_wr0(4 * 0x40049, 0x1400); + dwc_ddrphy_apb_wr0(4 * 0x40069, 0x0); + dwc_ddrphy_apb_wr0(4 * 0x4000a, 0xe08); + dwc_ddrphy_apb_wr0(4 * 0x4002a, 0xc15); + dwc_ddrphy_apb_wr0(4 * 0x4004a, 0x0); + dwc_ddrphy_apb_wr0(4 * 0x4006a, 0x0); + dwc_ddrphy_apb_wr0(4 * 0x4000b, 0x623); + dwc_ddrphy_apb_wr0(4 * 0x4002b, 0x15); + dwc_ddrphy_apb_wr0(4 * 0x4004b, 0x0); + dwc_ddrphy_apb_wr0(4 * 0x4006b, 0x0); + dwc_ddrphy_apb_wr0(4 * 0x4000c, 0x4028); + dwc_ddrphy_apb_wr0(4 * 0x4002c, 0x80); + dwc_ddrphy_apb_wr0(4 * 0x4004c, 0x0); + dwc_ddrphy_apb_wr0(4 * 0x4006c, 0x0); + dwc_ddrphy_apb_wr0(4 * 0x4000d, 0xe08); + dwc_ddrphy_apb_wr0(4 * 0x4002d, 0xc1a); + dwc_ddrphy_apb_wr0(4 * 0x4004d, 0x0); + dwc_ddrphy_apb_wr0(4 * 0x4006d, 0x0); + dwc_ddrphy_apb_wr0(4 * 0x4000e, 0x623); + dwc_ddrphy_apb_wr0(4 * 0x4002e, 0x1a); + dwc_ddrphy_apb_wr0(4 * 0x4004e, 0x0); + dwc_ddrphy_apb_wr0(4 * 0x4006e, 0x0); + dwc_ddrphy_apb_wr0(4 * 0x4000f, 0x4040); + dwc_ddrphy_apb_wr0(4 * 0x4002f, 0x80); + dwc_ddrphy_apb_wr0(4 * 0x4004f, 0x0); + dwc_ddrphy_apb_wr0(4 * 0x4006f, 0x0); + dwc_ddrphy_apb_wr0(4 * 0x40010, 0x2604); + dwc_ddrphy_apb_wr0(4 * 0x40030, 0x15); + dwc_ddrphy_apb_wr0(4 * 0x40050, 0x0); + dwc_ddrphy_apb_wr0(4 * 0x40070, 0x0); + dwc_ddrphy_apb_wr0(4 * 0x40011, 0x708); + dwc_ddrphy_apb_wr0(4 * 0x40031, 0x5); + dwc_ddrphy_apb_wr0(4 * 0x40051, 0x0); + dwc_ddrphy_apb_wr0(4 * 0x40071, 0x2002); + dwc_ddrphy_apb_wr0(4 * 0x40012, 0x8); + dwc_ddrphy_apb_wr0(4 * 0x40032, 0x80); + dwc_ddrphy_apb_wr0(4 * 0x40052, 0x0); + dwc_ddrphy_apb_wr0(4 * 0x40072, 0x0); + dwc_ddrphy_apb_wr0(4 * 0x40013, 0x2604); + dwc_ddrphy_apb_wr0(4 * 0x40033, 0x1a); + dwc_ddrphy_apb_wr0(4 * 0x40053, 0x0); + dwc_ddrphy_apb_wr0(4 * 0x40073, 0x0); + dwc_ddrphy_apb_wr0(4 * 0x40014, 0x708); + dwc_ddrphy_apb_wr0(4 * 0x40034, 0xa); + dwc_ddrphy_apb_wr0(4 * 0x40054, 0x0); + dwc_ddrphy_apb_wr0(4 * 0x40074, 0x2002); + dwc_ddrphy_apb_wr0(4 * 0x40015, 0x4040); + dwc_ddrphy_apb_wr0(4 * 0x40035, 0x80); + dwc_ddrphy_apb_wr0(4 * 0x40055, 0x0); + dwc_ddrphy_apb_wr0(4 * 0x40075, 0x0); + dwc_ddrphy_apb_wr0(4 * 0x40016, 0x60a); + dwc_ddrphy_apb_wr0(4 * 0x40036, 0x15); + dwc_ddrphy_apb_wr0(4 * 0x40056, 0x1200); + dwc_ddrphy_apb_wr0(4 * 0x40076, 0x0); + dwc_ddrphy_apb_wr0(4 * 0x40017, 0x61a); + dwc_ddrphy_apb_wr0(4 * 0x40037, 0x15); + dwc_ddrphy_apb_wr0(4 * 0x40057, 0x1300); + dwc_ddrphy_apb_wr0(4 * 0x40077, 0x0); + dwc_ddrphy_apb_wr0(4 * 0x40018, 0x60a); + dwc_ddrphy_apb_wr0(4 * 0x40038, 0x1a); + dwc_ddrphy_apb_wr0(4 * 0x40058, 0x1200); + dwc_ddrphy_apb_wr0(4 * 0x40078, 0x0); + dwc_ddrphy_apb_wr0(4 * 0x40019, 0x642); + dwc_ddrphy_apb_wr0(4 * 0x40039, 0x1a); + dwc_ddrphy_apb_wr0(4 * 0x40059, 0x1300); + dwc_ddrphy_apb_wr0(4 * 0x40079, 0x0); + dwc_ddrphy_apb_wr0(4 * 0x4001a, 0x4808); + dwc_ddrphy_apb_wr0(4 * 0x4003a, 0x880); + dwc_ddrphy_apb_wr0(4 * 0x4005a, 0x0); + dwc_ddrphy_apb_wr0(4 * 0x4007a, 0x0); + dwc_ddrphy_apb_wr0(4 * 0x900aa, 0x0); + dwc_ddrphy_apb_wr0(4 * 0x900ab, 0x790); + dwc_ddrphy_apb_wr0(4 * 0x900ac, 0x11a); + dwc_ddrphy_apb_wr0(4 * 0x900ad, 0x8); + dwc_ddrphy_apb_wr0(4 * 0x900ae, 0x7aa); + dwc_ddrphy_apb_wr0(4 * 0x900af, 0x2a); + dwc_ddrphy_apb_wr0(4 * 0x900b0, 0x10); + dwc_ddrphy_apb_wr0(4 * 0x900b1, 0x7b2); + dwc_ddrphy_apb_wr0(4 * 0x900b2, 0x2a); + dwc_ddrphy_apb_wr0(4 * 0x900b3, 0x0); + dwc_ddrphy_apb_wr0(4 * 0x900b4, 0x7c8); + dwc_ddrphy_apb_wr0(4 * 0x900b5, 0x109); + dwc_ddrphy_apb_wr0(4 * 0x900b6, 0x10); + dwc_ddrphy_apb_wr0(4 * 0x900b7, 0x10); + dwc_ddrphy_apb_wr0(4 * 0x900b8, 0x109); + dwc_ddrphy_apb_wr0(4 * 0x900b9, 0x10); + dwc_ddrphy_apb_wr0(4 * 0x900ba, 0x2a8); + dwc_ddrphy_apb_wr0(4 * 0x900bb, 0x129); + dwc_ddrphy_apb_wr0(4 * 0x900bc, 0x8); + dwc_ddrphy_apb_wr0(4 * 0x900bd, 0x370); + dwc_ddrphy_apb_wr0(4 * 0x900be, 0x129); + dwc_ddrphy_apb_wr0(4 * 0x900bf, 0xa); + dwc_ddrphy_apb_wr0(4 * 0x900c0, 0x3c8); + dwc_ddrphy_apb_wr0(4 * 0x900c1, 0x1a9); + dwc_ddrphy_apb_wr0(4 * 0x900c2, 0xc); + dwc_ddrphy_apb_wr0(4 * 0x900c3, 0x408); + dwc_ddrphy_apb_wr0(4 * 0x900c4, 0x199); + dwc_ddrphy_apb_wr0(4 * 0x900c5, 0x14); + dwc_ddrphy_apb_wr0(4 * 0x900c6, 0x790); + dwc_ddrphy_apb_wr0(4 * 0x900c7, 0x11a); + dwc_ddrphy_apb_wr0(4 * 0x900c8, 0x8); + dwc_ddrphy_apb_wr0(4 * 0x900c9, 0x4); + dwc_ddrphy_apb_wr0(4 * 0x900ca, 0x18); + dwc_ddrphy_apb_wr0(4 * 0x900cb, 0xe); + dwc_ddrphy_apb_wr0(4 * 0x900cc, 0x408); + dwc_ddrphy_apb_wr0(4 * 0x900cd, 0x199); + dwc_ddrphy_apb_wr0(4 * 0x900ce, 0x8); + dwc_ddrphy_apb_wr0(4 * 0x900cf, 0x8568); + dwc_ddrphy_apb_wr0(4 * 0x900d0, 0x108); + dwc_ddrphy_apb_wr0(4 * 0x900d1, 0x18); + dwc_ddrphy_apb_wr0(4 * 0x900d2, 0x790); + dwc_ddrphy_apb_wr0(4 * 0x900d3, 0x16a); + dwc_ddrphy_apb_wr0(4 * 0x900d4, 0x8); + dwc_ddrphy_apb_wr0(4 * 0x900d5, 0x1d8); + dwc_ddrphy_apb_wr0(4 * 0x900d6, 0x169); + dwc_ddrphy_apb_wr0(4 * 0x900d7, 0x10); + dwc_ddrphy_apb_wr0(4 * 0x900d8, 0x8558); + dwc_ddrphy_apb_wr0(4 * 0x900d9, 0x168); + dwc_ddrphy_apb_wr0(4 * 0x900da, 0x70); + dwc_ddrphy_apb_wr0(4 * 0x900db, 0x788); + dwc_ddrphy_apb_wr0(4 * 0x900dc, 0x16a); + dwc_ddrphy_apb_wr0(4 * 0x900dd, 0x1ff8); + dwc_ddrphy_apb_wr0(4 * 0x900de, 0x85a8); + dwc_ddrphy_apb_wr0(4 * 0x900df, 0x1e8); + dwc_ddrphy_apb_wr0(4 * 0x900e0, 0x50); + dwc_ddrphy_apb_wr0(4 * 0x900e1, 0x798); + dwc_ddrphy_apb_wr0(4 * 0x900e2, 0x16a); + dwc_ddrphy_apb_wr0(4 * 0x900e3, 0x60); + dwc_ddrphy_apb_wr0(4 * 0x900e4, 0x7a0); + dwc_ddrphy_apb_wr0(4 * 0x900e5, 0x16a); + dwc_ddrphy_apb_wr0(4 * 0x900e6, 0x8); + dwc_ddrphy_apb_wr0(4 * 0x900e7, 0x8310); + dwc_ddrphy_apb_wr0(4 * 0x900e8, 0x168); + dwc_ddrphy_apb_wr0(4 * 0x900e9, 0x8); + dwc_ddrphy_apb_wr0(4 * 0x900ea, 0xa310); + dwc_ddrphy_apb_wr0(4 * 0x900eb, 0x168); + dwc_ddrphy_apb_wr0(4 * 0x900ec, 0xa); + dwc_ddrphy_apb_wr0(4 * 0x900ed, 0x408); + dwc_ddrphy_apb_wr0(4 * 0x900ee, 0x169); + dwc_ddrphy_apb_wr0(4 * 0x900ef, 0x6e); + dwc_ddrphy_apb_wr0(4 * 0x900f0, 0x0); + dwc_ddrphy_apb_wr0(4 * 0x900f1, 0x68); + dwc_ddrphy_apb_wr0(4 * 0x900f2, 0x0); + dwc_ddrphy_apb_wr0(4 * 0x900f3, 0x408); + dwc_ddrphy_apb_wr0(4 * 0x900f4, 0x169); + dwc_ddrphy_apb_wr0(4 * 0x900f5, 0x0); + dwc_ddrphy_apb_wr0(4 * 0x900f6, 0x8310); + dwc_ddrphy_apb_wr0(4 * 0x900f7, 0x168); + dwc_ddrphy_apb_wr0(4 * 0x900f8, 0x0); + dwc_ddrphy_apb_wr0(4 * 0x900f9, 0xa310); + dwc_ddrphy_apb_wr0(4 * 0x900fa, 0x168); + dwc_ddrphy_apb_wr0(4 * 0x900fb, 0x1ff8); + dwc_ddrphy_apb_wr0(4 * 0x900fc, 0x85a8); + dwc_ddrphy_apb_wr0(4 * 0x900fd, 0x1e8); + dwc_ddrphy_apb_wr0(4 * 0x900fe, 0x68); + dwc_ddrphy_apb_wr0(4 * 0x900ff, 0x798); + dwc_ddrphy_apb_wr0(4 * 0x90100, 0x16a); + dwc_ddrphy_apb_wr0(4 * 0x90101, 0x78); + dwc_ddrphy_apb_wr0(4 * 0x90102, 0x7a0); + dwc_ddrphy_apb_wr0(4 * 0x90103, 0x16a); + dwc_ddrphy_apb_wr0(4 * 0x90104, 0x68); + dwc_ddrphy_apb_wr0(4 * 0x90105, 0x790); + dwc_ddrphy_apb_wr0(4 * 0x90106, 0x16a); + dwc_ddrphy_apb_wr0(4 * 0x90107, 0x8); + dwc_ddrphy_apb_wr0(4 * 0x90108, 0x8b10); + dwc_ddrphy_apb_wr0(4 * 0x90109, 0x168); + dwc_ddrphy_apb_wr0(4 * 0x9010a, 0x8); + dwc_ddrphy_apb_wr0(4 * 0x9010b, 0xab10); + dwc_ddrphy_apb_wr0(4 * 0x9010c, 0x168); + dwc_ddrphy_apb_wr0(4 * 0x9010d, 0xa); + dwc_ddrphy_apb_wr0(4 * 0x9010e, 0x408); + dwc_ddrphy_apb_wr0(4 * 0x9010f, 0x169); + dwc_ddrphy_apb_wr0(4 * 0x90110, 0x58); + dwc_ddrphy_apb_wr0(4 * 0x90111, 0x0); + dwc_ddrphy_apb_wr0(4 * 0x90112, 0x68); + dwc_ddrphy_apb_wr0(4 * 0x90113, 0x0); + dwc_ddrphy_apb_wr0(4 * 0x90114, 0x408); + dwc_ddrphy_apb_wr0(4 * 0x90115, 0x169); + dwc_ddrphy_apb_wr0(4 * 0x90116, 0x0); + dwc_ddrphy_apb_wr0(4 * 0x90117, 0x8b10); + dwc_ddrphy_apb_wr0(4 * 0x90118, 0x168); + dwc_ddrphy_apb_wr0(4 * 0x90119, 0x0); + dwc_ddrphy_apb_wr0(4 * 0x9011a, 0xab10); + dwc_ddrphy_apb_wr0(4 * 0x9011b, 0x168); + dwc_ddrphy_apb_wr0(4 * 0x9011c, 0x0); + dwc_ddrphy_apb_wr0(4 * 0x9011d, 0x1d8); + dwc_ddrphy_apb_wr0(4 * 0x9011e, 0x169); + dwc_ddrphy_apb_wr0(4 * 0x9011f, 0x80); + dwc_ddrphy_apb_wr0(4 * 0x90120, 0x790); + dwc_ddrphy_apb_wr0(4 * 0x90121, 0x16a); + dwc_ddrphy_apb_wr0(4 * 0x90122, 0x18); + dwc_ddrphy_apb_wr0(4 * 0x90123, 0x7aa); + dwc_ddrphy_apb_wr0(4 * 0x90124, 0x6a); + dwc_ddrphy_apb_wr0(4 * 0x90125, 0xa); + dwc_ddrphy_apb_wr0(4 * 0x90126, 0x0); + dwc_ddrphy_apb_wr0(4 * 0x90127, 0x1e9); + dwc_ddrphy_apb_wr0(4 * 0x90128, 0x8); + dwc_ddrphy_apb_wr0(4 * 0x90129, 0x8080); + dwc_ddrphy_apb_wr0(4 * 0x9012a, 0x108); + dwc_ddrphy_apb_wr0(4 * 0x9012b, 0xf); + dwc_ddrphy_apb_wr0(4 * 0x9012c, 0x408); + dwc_ddrphy_apb_wr0(4 * 0x9012d, 0x169); + dwc_ddrphy_apb_wr0(4 * 0x9012e, 0xc); + dwc_ddrphy_apb_wr0(4 * 0x9012f, 0x0); + dwc_ddrphy_apb_wr0(4 * 0x90130, 0x68); + dwc_ddrphy_apb_wr0(4 * 0x90131, 0x9); + dwc_ddrphy_apb_wr0(4 * 0x90132, 0x0); + dwc_ddrphy_apb_wr0(4 * 0x90133, 0x1a9); + dwc_ddrphy_apb_wr0(4 * 0x90134, 0x0); + dwc_ddrphy_apb_wr0(4 * 0x90135, 0x408); + dwc_ddrphy_apb_wr0(4 * 0x90136, 0x169); + dwc_ddrphy_apb_wr0(4 * 0x90137, 0x0); + dwc_ddrphy_apb_wr0(4 * 0x90138, 0x8080); + dwc_ddrphy_apb_wr0(4 * 0x90139, 0x108); + dwc_ddrphy_apb_wr0(4 * 0x9013a, 0x8); + dwc_ddrphy_apb_wr0(4 * 0x9013b, 0x7aa); + dwc_ddrphy_apb_wr0(4 * 0x9013c, 0x6a); + dwc_ddrphy_apb_wr0(4 * 0x9013d, 0x0); + dwc_ddrphy_apb_wr0(4 * 0x9013e, 0x8568); + dwc_ddrphy_apb_wr0(4 * 0x9013f, 0x108); + dwc_ddrphy_apb_wr0(4 * 0x90140, 0xb7); + dwc_ddrphy_apb_wr0(4 * 0x90141, 0x790); + dwc_ddrphy_apb_wr0(4 * 0x90142, 0x16a); + dwc_ddrphy_apb_wr0(4 * 0x90143, 0x1f); + dwc_ddrphy_apb_wr0(4 * 0x90144, 0x0); + dwc_ddrphy_apb_wr0(4 * 0x90145, 0x68); + dwc_ddrphy_apb_wr0(4 * 0x90146, 0x8); + dwc_ddrphy_apb_wr0(4 * 0x90147, 0x8558); + dwc_ddrphy_apb_wr0(4 * 0x90148, 0x168); + dwc_ddrphy_apb_wr0(4 * 0x90149, 0xf); + dwc_ddrphy_apb_wr0(4 * 0x9014a, 0x408); + dwc_ddrphy_apb_wr0(4 * 0x9014b, 0x169); + dwc_ddrphy_apb_wr0(4 * 0x9014c, 0xc); + dwc_ddrphy_apb_wr0(4 * 0x9014d, 0x0); + dwc_ddrphy_apb_wr0(4 * 0x9014e, 0x68); + dwc_ddrphy_apb_wr0(4 * 0x9014f, 0x0); + dwc_ddrphy_apb_wr0(4 * 0x90150, 0x408); + dwc_ddrphy_apb_wr0(4 * 0x90151, 0x169); + dwc_ddrphy_apb_wr0(4 * 0x90152, 0x0); + dwc_ddrphy_apb_wr0(4 * 0x90153, 0x8558); + dwc_ddrphy_apb_wr0(4 * 0x90154, 0x168); + dwc_ddrphy_apb_wr0(4 * 0x90155, 0x8); + dwc_ddrphy_apb_wr0(4 * 0x90156, 0x3c8); + dwc_ddrphy_apb_wr0(4 * 0x90157, 0x1a9); + dwc_ddrphy_apb_wr0(4 * 0x90158, 0x3); + dwc_ddrphy_apb_wr0(4 * 0x90159, 0x370); + dwc_ddrphy_apb_wr0(4 * 0x9015a, 0x129); + dwc_ddrphy_apb_wr0(4 * 0x9015b, 0x20); + dwc_ddrphy_apb_wr0(4 * 0x9015c, 0x2aa); + dwc_ddrphy_apb_wr0(4 * 0x9015d, 0x9); + dwc_ddrphy_apb_wr0(4 * 0x9015e, 0x0); + dwc_ddrphy_apb_wr0(4 * 0x9015f, 0x400); + dwc_ddrphy_apb_wr0(4 * 0x90160, 0x10e); + dwc_ddrphy_apb_wr0(4 * 0x90161, 0x8); + dwc_ddrphy_apb_wr0(4 * 0x90162, 0xe8); + dwc_ddrphy_apb_wr0(4 * 0x90163, 0x109); + dwc_ddrphy_apb_wr0(4 * 0x90164, 0x0); + dwc_ddrphy_apb_wr0(4 * 0x90165, 0x8140); + dwc_ddrphy_apb_wr0(4 * 0x90166, 0x10c); + dwc_ddrphy_apb_wr0(4 * 0x90167, 0x10); + dwc_ddrphy_apb_wr0(4 * 0x90168, 0x8138); + dwc_ddrphy_apb_wr0(4 * 0x90169, 0x10c); + dwc_ddrphy_apb_wr0(4 * 0x9016a, 0x8); + dwc_ddrphy_apb_wr0(4 * 0x9016b, 0x7c8); + dwc_ddrphy_apb_wr0(4 * 0x9016c, 0x101); + dwc_ddrphy_apb_wr0(4 * 0x9016d, 0x8); + dwc_ddrphy_apb_wr0(4 * 0x9016e, 0x0); + dwc_ddrphy_apb_wr0(4 * 0x9016f, 0x8); + dwc_ddrphy_apb_wr0(4 * 0x90170, 0x8); + dwc_ddrphy_apb_wr0(4 * 0x90171, 0x448); + dwc_ddrphy_apb_wr0(4 * 0x90172, 0x109); + dwc_ddrphy_apb_wr0(4 * 0x90173, 0xf); + dwc_ddrphy_apb_wr0(4 * 0x90174, 0x7c0); + dwc_ddrphy_apb_wr0(4 * 0x90175, 0x109); + dwc_ddrphy_apb_wr0(4 * 0x90176, 0x0); + dwc_ddrphy_apb_wr0(4 * 0x90177, 0xe8); + dwc_ddrphy_apb_wr0(4 * 0x90178, 0x109); + dwc_ddrphy_apb_wr0(4 * 0x90179, 0x47); + dwc_ddrphy_apb_wr0(4 * 0x9017a, 0x630); + dwc_ddrphy_apb_wr0(4 * 0x9017b, 0x109); + dwc_ddrphy_apb_wr0(4 * 0x9017c, 0x8); + dwc_ddrphy_apb_wr0(4 * 0x9017d, 0x618); + dwc_ddrphy_apb_wr0(4 * 0x9017e, 0x109); + dwc_ddrphy_apb_wr0(4 * 0x9017f, 0x8); + dwc_ddrphy_apb_wr0(4 * 0x90180, 0xe0); + dwc_ddrphy_apb_wr0(4 * 0x90181, 0x109); + dwc_ddrphy_apb_wr0(4 * 0x90182, 0x0); + dwc_ddrphy_apb_wr0(4 * 0x90183, 0x7c8); + dwc_ddrphy_apb_wr0(4 * 0x90184, 0x109); + dwc_ddrphy_apb_wr0(4 * 0x90185, 0x8); + dwc_ddrphy_apb_wr0(4 * 0x90186, 0x8140); + dwc_ddrphy_apb_wr0(4 * 0x90187, 0x10c); + dwc_ddrphy_apb_wr0(4 * 0x90188, 0x0); + dwc_ddrphy_apb_wr0(4 * 0x90189, 0x1); + dwc_ddrphy_apb_wr0(4 * 0x9018a, 0x8); + dwc_ddrphy_apb_wr0(4 * 0x9018b, 0x8); + dwc_ddrphy_apb_wr0(4 * 0x9018c, 0x4); + dwc_ddrphy_apb_wr0(4 * 0x9018d, 0x8); + dwc_ddrphy_apb_wr0(4 * 0x9018e, 0x8); + dwc_ddrphy_apb_wr0(4 * 0x9018f, 0x7c8); + dwc_ddrphy_apb_wr0(4 * 0x90190, 0x101); + dwc_ddrphy_apb_wr0(4 * 0x90006, 0x0); + dwc_ddrphy_apb_wr0(4 * 0x90007, 0x0); + dwc_ddrphy_apb_wr0(4 * 0x90008, 0x8); + dwc_ddrphy_apb_wr0(4 * 0x90009, 0x0); + dwc_ddrphy_apb_wr0(4 * 0x9000a, 0x0); + dwc_ddrphy_apb_wr0(4 * 0x9000b, 0x0); + dwc_ddrphy_apb_wr0(4 * 0xd00e7, 0x400); + dwc_ddrphy_apb_wr0(4 * 0x90017, 0x0); + dwc_ddrphy_apb_wr0(4 * 0x9001f, 0x2b); + dwc_ddrphy_apb_wr0(4 * 0x90026, 0x6c); + dwc_ddrphy_apb_wr0(4 * 0x400d0, 0x0); + dwc_ddrphy_apb_wr0(4 * 0x400d1, 0x101); + dwc_ddrphy_apb_wr0(4 * 0x400d2, 0x105); + dwc_ddrphy_apb_wr0(4 * 0x400d3, 0x107); + dwc_ddrphy_apb_wr0(4 * 0x400d4, 0x10f); + dwc_ddrphy_apb_wr0(4 * 0x400d5, 0x202); + dwc_ddrphy_apb_wr0(4 * 0x400d6, 0x20a); + dwc_ddrphy_apb_wr0(4 * 0x400d7, 0x20b); + dwc_ddrphy_apb_wr0(4 * 0x2003a, 0x2); + dwc_ddrphy_apb_wr0(4 * 0x2000b, 0x64); + dwc_ddrphy_apb_wr0(4 * 0x2000c, 0xc8); + dwc_ddrphy_apb_wr0(4 * 0x2000d, 0x7d0); + dwc_ddrphy_apb_wr0(4 * 0x2000e, 0x2c); + dwc_ddrphy_apb_wr0(4 * 0x12000b, 0x14); + dwc_ddrphy_apb_wr0(4 * 0x12000c, 0x29); + dwc_ddrphy_apb_wr0(4 * 0x12000d, 0x1a1); + dwc_ddrphy_apb_wr0(4 * 0x12000e, 0x10); + dwc_ddrphy_apb_wr0(4 * 0x22000b, 0x3); + dwc_ddrphy_apb_wr0(4 * 0x22000c, 0x6); + dwc_ddrphy_apb_wr0(4 * 0x22000d, 0x3e); + dwc_ddrphy_apb_wr0(4 * 0x22000e, 0x10); + dwc_ddrphy_apb_wr0(4 * 0x9000c, 0x0); + dwc_ddrphy_apb_wr0(4 * 0x9000d, 0x173); + dwc_ddrphy_apb_wr0(4 * 0x9000e, 0x60); + dwc_ddrphy_apb_wr0(4 * 0x9000f, 0x6110); + dwc_ddrphy_apb_wr0(4 * 0x90010, 0x2152); + dwc_ddrphy_apb_wr0(4 * 0x90011, 0xdfbd); + dwc_ddrphy_apb_wr0(4 * 0x90012, 0x60); + dwc_ddrphy_apb_wr0(4 * 0x90013, 0x6152); + dwc_ddrphy_apb_wr0(4 * 0x20010, 0x5a); + dwc_ddrphy_apb_wr0(4 * 0x20011, 0x3); + dwc_ddrphy_apb_wr0(4 * 0x40080, 0xe0); + dwc_ddrphy_apb_wr0(4 * 0x40081, 0x12); + dwc_ddrphy_apb_wr0(4 * 0x40082, 0xe0); + dwc_ddrphy_apb_wr0(4 * 0x40083, 0x12); + dwc_ddrphy_apb_wr0(4 * 0x40084, 0xe0); + dwc_ddrphy_apb_wr0(4 * 0x40085, 0x12); + dwc_ddrphy_apb_wr0(4 * 0x140080, 0xe0); + dwc_ddrphy_apb_wr0(4 * 0x140081, 0x12); + dwc_ddrphy_apb_wr0(4 * 0x140082, 0xe0); + dwc_ddrphy_apb_wr0(4 * 0x140083, 0x12); + dwc_ddrphy_apb_wr0(4 * 0x140084, 0xe0); + dwc_ddrphy_apb_wr0(4 * 0x140085, 0x12); + dwc_ddrphy_apb_wr0(4 * 0x240080, 0xe0); + dwc_ddrphy_apb_wr0(4 * 0x240081, 0x12); + dwc_ddrphy_apb_wr0(4 * 0x240082, 0xe0); + dwc_ddrphy_apb_wr0(4 * 0x240083, 0x12); + dwc_ddrphy_apb_wr0(4 * 0x240084, 0xe0); + dwc_ddrphy_apb_wr0(4 * 0x240085, 0x12); + dwc_ddrphy_apb_wr0(4 * 0x400fd, 0xf); + dwc_ddrphy_apb_wr0(4 * 0x10011, 0x1); + dwc_ddrphy_apb_wr0(4 * 0x10012, 0x1); + dwc_ddrphy_apb_wr0(4 * 0x10013, 0x180); + dwc_ddrphy_apb_wr0(4 * 0x10018, 0x1); + dwc_ddrphy_apb_wr0(4 * 0x10002, 0x6209); + dwc_ddrphy_apb_wr0(4 * 0x100b2, 0x1); + dwc_ddrphy_apb_wr0(4 * 0x101b4, 0x1); + dwc_ddrphy_apb_wr0(4 * 0x102b4, 0x1); + dwc_ddrphy_apb_wr0(4 * 0x103b4, 0x1); + dwc_ddrphy_apb_wr0(4 * 0x104b4, 0x1); + dwc_ddrphy_apb_wr0(4 * 0x105b4, 0x1); + dwc_ddrphy_apb_wr0(4 * 0x106b4, 0x1); + dwc_ddrphy_apb_wr0(4 * 0x107b4, 0x1); + dwc_ddrphy_apb_wr0(4 * 0x108b4, 0x1); + dwc_ddrphy_apb_wr0(4 * 0x11011, 0x1); + dwc_ddrphy_apb_wr0(4 * 0x11012, 0x1); + dwc_ddrphy_apb_wr0(4 * 0x11013, 0x180); + dwc_ddrphy_apb_wr0(4 * 0x11018, 0x1); + dwc_ddrphy_apb_wr0(4 * 0x11002, 0x6209); + dwc_ddrphy_apb_wr0(4 * 0x110b2, 0x1); + dwc_ddrphy_apb_wr0(4 * 0x111b4, 0x1); + dwc_ddrphy_apb_wr0(4 * 0x112b4, 0x1); + dwc_ddrphy_apb_wr0(4 * 0x113b4, 0x1); + dwc_ddrphy_apb_wr0(4 * 0x114b4, 0x1); + dwc_ddrphy_apb_wr0(4 * 0x115b4, 0x1); + dwc_ddrphy_apb_wr0(4 * 0x116b4, 0x1); + dwc_ddrphy_apb_wr0(4 * 0x117b4, 0x1); + dwc_ddrphy_apb_wr0(4 * 0x118b4, 0x1); + dwc_ddrphy_apb_wr0(4 * 0x12011, 0x1); + dwc_ddrphy_apb_wr0(4 * 0x12012, 0x1); + dwc_ddrphy_apb_wr0(4 * 0x12013, 0x180); + dwc_ddrphy_apb_wr0(4 * 0x12018, 0x1); + dwc_ddrphy_apb_wr0(4 * 0x12002, 0x6209); + dwc_ddrphy_apb_wr0(4 * 0x120b2, 0x1); + dwc_ddrphy_apb_wr0(4 * 0x121b4, 0x1); + dwc_ddrphy_apb_wr0(4 * 0x122b4, 0x1); + dwc_ddrphy_apb_wr0(4 * 0x123b4, 0x1); + dwc_ddrphy_apb_wr0(4 * 0x124b4, 0x1); + dwc_ddrphy_apb_wr0(4 * 0x125b4, 0x1); + dwc_ddrphy_apb_wr0(4 * 0x126b4, 0x1); + dwc_ddrphy_apb_wr0(4 * 0x127b4, 0x1); + dwc_ddrphy_apb_wr0(4 * 0x128b4, 0x1); + dwc_ddrphy_apb_wr0(4 * 0x13011, 0x1); + dwc_ddrphy_apb_wr0(4 * 0x13012, 0x1); + dwc_ddrphy_apb_wr0(4 * 0x13013, 0x180); + dwc_ddrphy_apb_wr0(4 * 0x13018, 0x1); + dwc_ddrphy_apb_wr0(4 * 0x13002, 0x6209); + dwc_ddrphy_apb_wr0(4 * 0x130b2, 0x1); + dwc_ddrphy_apb_wr0(4 * 0x131b4, 0x1); + dwc_ddrphy_apb_wr0(4 * 0x132b4, 0x1); + dwc_ddrphy_apb_wr0(4 * 0x133b4, 0x1); + dwc_ddrphy_apb_wr0(4 * 0x134b4, 0x1); + dwc_ddrphy_apb_wr0(4 * 0x135b4, 0x1); + dwc_ddrphy_apb_wr0(4 * 0x136b4, 0x1); + dwc_ddrphy_apb_wr0(4 * 0x137b4, 0x1); + dwc_ddrphy_apb_wr0(4 * 0x138b4, 0x1); + dwc_ddrphy_apb_wr0(4 * 0x20089, 0x1); + dwc_ddrphy_apb_wr0(4 * 0x20088, 0x19); + dwc_ddrphy_apb_wr0(4 * 0xc0080, 0x2); + dwc_ddrphy_apb_wr0(4 * 0xd0000, 0x1); } diff --git a/board/boundary/nitrogen8m/ddr/helper.c b/board/boundary/nitrogen8m/ddr/helper.c index c9a02e0ccb0..1d2a3761264 100644 --- a/board/boundary/nitrogen8m/ddr/helper.c +++ b/board/boundary/nitrogen8m/ddr/helper.c @@ -9,9 +9,9 @@ #include <asm/io.h> #include <errno.h> #include <asm/io.h> +#include <asm/arch/ddr.h> #include <asm/sections.h> #include "ddr_memory_map.h" - #include "ddr.h" DECLARE_GLOBAL_DATA_PTR; diff --git a/board/boundary/nitrogen8m/ddr/wait_ddrphy_training_complete.c b/board/boundary/nitrogen8m/ddr/wait_ddrphy_training_complete.c index 0b42e58bd1d..47d622db774 100644 --- a/board/boundary/nitrogen8m/ddr/wait_ddrphy_training_complete.c +++ b/board/boundary/nitrogen8m/ddr/wait_ddrphy_training_complete.c @@ -77,7 +77,7 @@ static inline void decode_streaming_message(void) ddr_printf("\n"); } -void wait_ddrphy_training_complete(void) +void wait_ddrphy_training_complete1(void) { unsigned int mail; while (1) { diff --git a/board/boundary/nitrogen8m/lpddr4_timing.c b/board/boundary/nitrogen8m/lpddr4_timing.c index c7252d235a5..4e46d7dd967 100644 --- a/board/boundary/nitrogen8m/lpddr4_timing.c +++ b/board/boundary/nitrogen8m/lpddr4_timing.c @@ -5,6 +5,7 @@ */ #include <config.h> #include <linux/kernel.h> +#include <asm/arch/ddr.h> #include <asm/arch/ddr_memory_map.h> #include <asm/arch/lpddr4_define.h> #include <asm/arch/imx8m_ddr.h> diff --git a/board/boundary/nitrogen8m/spl.c b/board/boundary/nitrogen8m/spl.c index b22eca685fa..23b5c4bb0eb 100644 --- a/board/boundary/nitrogen8m/spl.c +++ b/board/boundary/nitrogen8m/spl.c @@ -19,22 +19,22 @@ #include <asm/mach-imx/mxc_i2c.h> #include <fsl_esdhc.h> #include <mmc.h> +#include <asm/arch/ddr.h> #ifdef CONFIG_IMX8M_LPDDR4 #include <asm/arch/imx8m_ddr.h> -#else +#endif #include "ddr/ddr.h" #include "ddr/ddr_memory_map.h" -#endif DECLARE_GLOBAL_DATA_PTR; void spl_dram_init(void) { /* ddr init */ -#ifdef CONFIG_IMX8M_LPDDR4 +#if 0 //def CONFIG_IMX8M_LPDDR4 ddr_init(&lpddr4_timing); #else - ddr_init(); + ddr_init1(); #endif } diff --git a/configs/nitrogen8m_3g_defconfig b/configs/nitrogen8m_3g_defconfig index 5b43f4f5c90..b2cae28f86c 100644 --- a/configs/nitrogen8m_3g_defconfig +++ b/configs/nitrogen8m_3g_defconfig @@ -1,6 +1,7 @@ CONFIG_ARM=y CONFIG_ARCH_IMX8M=y CONFIG_SYS_TEXT_BASE=0x40200000 +CONFIG_IMX8M_LPDDR4=y CONFIG_SPL_GPIO_SUPPORT=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y diff --git a/configs/nitrogen8m_4g_defconfig b/configs/nitrogen8m_4g_defconfig index 79eb28b6d1f..7fca6aa98d6 100644 --- a/configs/nitrogen8m_4g_defconfig +++ b/configs/nitrogen8m_4g_defconfig @@ -1,6 +1,7 @@ CONFIG_ARM=y CONFIG_ARCH_IMX8M=y CONFIG_SYS_TEXT_BASE=0x40200000 +CONFIG_IMX8M_LPDDR4=y CONFIG_SPL_GPIO_SUPPORT=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y diff --git a/configs/nitrogen8m_defconfig b/configs/nitrogen8m_defconfig index f719f088545..8151500ca34 100644 --- a/configs/nitrogen8m_defconfig +++ b/configs/nitrogen8m_defconfig @@ -1,7 +1,7 @@ CONFIG_ARM=y CONFIG_ARCH_IMX8M=y CONFIG_SYS_TEXT_BASE=0x40200000 -# CONFIG_IMX8M_LPDDR4=y +CONFIG_IMX8M_LPDDR4=y CONFIG_SPL_GPIO_SUPPORT=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y -- GitLab