diff --git a/board/boundary/nitrogen6x/1066mhz_4x128mx16.cfg b/board/boundary/nitrogen6x/1066mhz_4x128mx16.cfg
deleted file mode 100644
index c38c151472785d0ef9c07d37222e4a53c7e48cb5..0000000000000000000000000000000000000000
--- a/board/boundary/nitrogen6x/1066mhz_4x128mx16.cfg
+++ /dev/null
@@ -1,41 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2013 Boundary Devices
- */
-
-DATA 4, MX6_MMDC_P0_MDPDC, 0x00020036
-DATA 4, MX6_MMDC_P0_MDCFG0, 0x555A7974
-DATA 4, MX6_MMDC_P0_MDCFG1, 0xDB538F64
-DATA 4, MX6_MMDC_P0_MDCFG2, 0x01FF00DB
-DATA 4, MX6_MMDC_P0_MDRWD, 0x000026D2
-DATA 4, MX6_MMDC_P0_MDOR, 0x005A1023
-DATA 4, MX6_MMDC_P0_MDOTC, 0x09444040
-DATA 4, MX6_MMDC_P0_MDPDC, 0x00025576
-DATA 4, MX6_MMDC_P0_MDASP, 0x00000027
-DATA 4, MX6_MMDC_P0_MDCTL, 0x831A0000
-DATA 4, MX6_MMDC_P0_MDSCR, 0x04088032
-DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033
-DATA 4, MX6_MMDC_P0_MDSCR, 0x00428031
-DATA 4, MX6_MMDC_P0_MDSCR, 0x19308030
-DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040
-DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003
-DATA 4, MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003
-DATA 4, MX6_MMDC_P0_MDREF, 0x00005800
-DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00022227
-DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00022227
-DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x42720306
-DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x026F0266
-DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x4273030A
-DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x02740240
-DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x45393B3E
-DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x403A3747
-DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x40434541
-DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x473E4A3B
-DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x0011000E
-DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x000E001B
-DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x00190015
-DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x00070018
-DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800
-DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800
-DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000
-DATA 4, MX6_MMDC_P0_MAPSR, 0x00011006
diff --git a/board/boundary/nitrogen6x/1066mhz_4x256mx16.cfg b/board/boundary/nitrogen6x/1066mhz_4x256mx16.cfg
deleted file mode 100644
index f81d49106a487707a7e89a04a344d2bc8360bdb0..0000000000000000000000000000000000000000
--- a/board/boundary/nitrogen6x/1066mhz_4x256mx16.cfg
+++ /dev/null
@@ -1,41 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2013 Boundary Devices
- */
-
-DATA 4, MX6_MMDC_P0_MDPDC, 0x00020036
-DATA 4, MX6_MMDC_P0_MDCFG0, 0x898E7974
-DATA 4, MX6_MMDC_P0_MDCFG1, 0xDB538F64
-DATA 4, MX6_MMDC_P0_MDCFG2, 0x01FF00DB
-DATA 4, MX6_MMDC_P0_MDRWD, 0x000026D2
-DATA 4, MX6_MMDC_P0_MDOR, 0x008E1023
-DATA 4, MX6_MMDC_P0_MDOTC, 0x09444040
-DATA 4, MX6_MMDC_P0_MDPDC, 0x00025576
-DATA 4, MX6_MMDC_P0_MDASP, 0x00000047
-DATA 4, MX6_MMDC_P0_MDCTL, 0x841A0000
-DATA 4, MX6_MMDC_P0_MDSCR, 0x04088032
-DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033
-DATA 4, MX6_MMDC_P0_MDSCR, 0x00428031
-DATA 4, MX6_MMDC_P0_MDSCR, 0x19308030
-DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040
-DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003
-DATA 4, MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003
-DATA 4, MX6_MMDC_P0_MDREF, 0x00007800
-DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00022227
-DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00022227
-DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x42740304
-DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x026e0265
-DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x02750306
-DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x02720244
-DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x463d4041
-DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x42413c47
-DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x37414441
-DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x4633473b
-DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x0025001f
-DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x00290027
-DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x001f002b
-DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x000f0029
-DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800
-DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800
-DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000
-DATA 4, MX6_MMDC_P0_MAPSR, 0x00011006
diff --git a/board/boundary/nitrogen6x/6x_bootscript-mainline.txt b/board/boundary/nitrogen6x/6x_bootscript-mainline.txt
new file mode 100644
index 0000000000000000000000000000000000000000..85be2416114104ae48b72740a19c6d726b2b32a7
--- /dev/null
+++ b/board/boundary/nitrogen6x/6x_bootscript-mainline.txt
@@ -0,0 +1,153 @@
+setenv bootargs ''
+
+setenv initrd_high 0xffffffff
+a_base=0x10000000
+if itest.s x51 == "x${cpu}" ; then
+ a_base=0x90000000
+elif itest.s x53 == "x${cpu}"; then
+ a_base=0x70000000
+elif itest.s x6SX == "x${cpu}" || itest.s x7D == "x${cpu}"; then
+ a_base=0x80000000
+fi
+
+setexpr a_script ${a_base} + 0x00800000
+setexpr a_zImage ${a_base} + 0x00800000
+setexpr a_fdt ${a_base} + 0x03000000
+setexpr a_ramdisk ${a_base} + 0x03800000
+setexpr a_initrd ${a_base} + 0x03a00000
+setexpr a_reset_cause_marker ${a_base} + 0x80
+setexpr a_reset_cause ${a_base} + 0x84
+
+if itest.s "x" == "x${board}" ; then
+ echo "!!!! Error: Your u-boot is outdated. Please upgrade.";
+ exit;
+fi
+
+if itest.s "x" == "x${dtbname}" ; then
+ if itest.s x6SOLO == "x${cpu}" ; then
+ dtbname=imx6dl-${board}.dtb;
+ elif itest.s x6DL == "x${cpu}" ; then
+ dtbname=imx6dl-${board}.dtb;
+ elif itest.s x6QP == "x${cpu}" ; then
+ dtbname=imx6qp-${board}.dtb;
+ elif itest.s x6SX == "x${cpu}" ; then
+ dtbname=imx6sx-${board}.dtb;
+ elif itest.s x7D == "x${cpu}" ; then
+ dtbname=imx7d-${board}.dtb;
+ elif itest.s x51 == "x${cpu}" ; then
+ dtbname=imx51-${board}${m4}.dtb;
+ elif itest.s x53 == "x${cpu}" ; then
+ dtbname=imx53-${board}${m4}.dtb;
+ else
+ dtbname=imx6q-${board}.dtb;
+ fi
+fi
+
+if load ${dtype} ${disk}:1 ${a_script} uEnv.txt ; then
+ env import -t ${a_script} ${filesize}
+fi
+
+if itest.s x == x${bootdir} ; then
+ bootdir=/
+fi
+
+if itest.s x${bootpart} == x ; then
+ bootpart=1
+fi
+
+if load ${dtype} ${disk}:${bootpart} ${a_fdt} ${bootdir}${dtbname} ; then
+ fdt addr ${a_fdt}
+ setenv fdt_high 0xffffffff
+else
+ echo "!!!! Error loading ${bootdir}${dtbname}";
+ exit;
+fi
+
+fdt resize
+if itest.s "x" != "x${cmd_custom}" ; then
+ run cmd_custom
+fi
+
+## HDMI ##
+if itest.s "xoff" == "x$fb_hdmi" ; then
+ setenv bootargs $bootargs video=HDMI-A-1:d
+else
+ if itest.s "x" != "x$force_edid" ; then
+ echo "------ forcing EDID to /lib/firmware/$force_edid"
+ setenv bootargs $bootargs drm_kms_helper.edid_firmware=$force_edid
+ fi
+fi
+
+## LVDS ##
+if itest.s "xoff" == "x$fb_lvds" ; then
+ setenv bootargs $bootargs video=LVDS-1:d
+elif itest.s "xhannstar7" == "x$fb_lvds" ; then
+ fdt set /panel-lvds0 compatible "hannstar,hsd070pww1"
+elif itest.s "xtm070jdhg30" == "x$fb_lvds" ; then
+ fdt set /panel-lvds0 compatible "tianma,tm070jdhg30"
+elif itest.s "xdt070btft" == "x$fb_lvds" ; then
+ fdt set /panel-lvds0 compatible "innolux,zj070na-01p"
+fi
+
+if itest.s "xoff" == "x$fb_lvds2" ; then
+ setenv bootargs $bootargs video=LVDS-2:d
+elif itest.s "xhannstar7" == "x$fb_lvds2" ; then
+ fdt set /panel-lvds1 compatible "hannstar,hsd070pww1"
+elif itest.s "xtm070jdhg30" == "x$fb_lvds2" ; then
+ fdt set /panel-lvds1 compatible "tianma,tm070jdhg30"
+elif itest.s "xdt070btft" == "x$fb_lvds2" ; then
+ fdt set /panel-lvds1 compatible "innolux,zj070na-01p"
+fi
+
+## LCD ##
+if itest.s "xoff" == "x$fb_lcd" ; then
+ setenv bootargs $bootargs video=VGA-1:d
+fi
+
+if itest.s x${rfspart} == x ; then
+ rfspart=2
+fi
+
+if itest.s "x" == "x${root}"; then
+ part uuid ${dtype} ${disk}:${rfspart} uuid
+ if itest.s "x" != "x${uuid}"; then
+ root=PARTUUID=${uuid}
+ elif test "sata" = "${dtype}" || test "usb" = "${dtype}" ; then
+ root=/dev/sda${rfspart}
+ else
+ root=/dev/mmcblk${disk}p${rfspart}
+ fi
+fi
+
+if itest.s "x" == "x$cma" ; then
+ cma=256M
+fi
+
+if itest.s "x" == "x$vmalloc" ; then
+ vmalloc=400M
+fi
+
+if itest.s "x" != "x$show_fdt" ; then
+ fdt print /
+fi
+
+if itest.s "x" != "x$show_env" ; then
+ printenv
+fi
+
+setenv bootargs "$bootargs console=${console},115200 vmalloc=${vmalloc}"
+setenv bootargs "$bootargs cma=${cma} consoleblank=0 root=${root} rootwait"
+
+if itest.s "x" != "x${loglevel}" ; then
+ setenv bootargs ${bootargs} loglevel=${loglevel}
+fi
+
+if itest *${a_reset_cause_marker} == 12345678 ; then
+ setexpr.l reset_cause *${a_reset_cause}
+ setenv bootargs $bootargs reset_cause=0x${reset_cause}
+fi
+
+if load ${dtype} ${disk}:${bootpart} ${a_zImage} ${bootdir}zImage ; then
+ bootz ${a_zImage} - ${a_fdt}
+fi
+echo "Error loading kernel image"
diff --git a/board/boundary/nitrogen6x/6x_bootscript-ubuntu-3.10.17.txt b/board/boundary/nitrogen6x/6x_bootscript-ubuntu-3.10.17.txt
new file mode 100644
index 0000000000000000000000000000000000000000..d525f757f6019573d8d9b7001bc713c0d99c5943
--- /dev/null
+++ b/board/boundary/nitrogen6x/6x_bootscript-ubuntu-3.10.17.txt
@@ -0,0 +1,240 @@
+if ${fs}load ${dtype} ${disk}:1 10800000 uEnv.txt ; then
+ env import -t 10800000 $filesize
+else
+ setenv bootargs enable_wait_mode=off
+fi
+
+setenv nextcon 0;
+
+if itest.s x == x${hdmires} ; then
+ setenv hdmires 1280x720M@60,if=RGB24,bpp=32
+ setenv only_cea 1
+fi
+
+# if hdmidet ; then
+i2c dev 1 ;
+if i2c probe 0x50 ; then
+ setenv bootargs $bootargs video=mxcfb${nextcon}:dev=hdmi,${hdmires}
+ setenv fbmem "fbmem=28M";
+ setexpr nextcon $nextcon + 1
+else
+ echo "------ no HDMI monitor";
+fi
+
+i2c dev 2
+if i2c probe 0x04 ; then
+ setenv bootargs $bootargs video=mxcfb${nextcon}:dev=ldb,LDB-XGA,if=RGB666
+ if test "0" -eq $nextcon; then
+ setenv fbmem "fbmem=10M";
+ else
+ setenv fbmem ${fbmem},10M
+ fi
+ setexpr nextcon $nextcon + 1
+else
+ echo "------ no Freescale display";
+fi
+
+if i2c probe 0x38 ; then
+ if itest.s "xLDB-WXGA" == "x$panel"; then
+ setenv bootargs $bootargs video=mxcfb${nextcon}:dev=ldb,1280x800MR@60,if=RGB666
+ screenres=1280,800
+ else
+ setenv bootargs $bootargs video=mxcfb${nextcon}:dev=ldb,1024x600M@60,if=RGB666
+ screenres=1024,600
+ fi
+ if test "0" -eq $nextcon; then
+ setenv fbmem "fbmem=10M";
+ else
+ setenv fbmem ${fbmem},10M
+ fi
+ setexpr nextcon $nextcon + 1
+ setenv bootargs $bootargs ft5x06_ts.screenres=$screenres
+ if itest.s "x" -ne "x$calibration" ; then
+ setenv bootargs $bootargs ft5x06_ts.calibration=$calibration
+ fi
+else
+ echo "------ no ft5x06 touch controller";
+fi
+
+if i2c probe 0x41 ; then
+ setenv bootargs $bootargs video=mxcfb${nextcon}:dev=ldb,1024x600M@60,if=RGB666
+ if test "0" -eq $nextcon; then
+ setenv fbmem "fbmem=10M";
+ else
+ setenv fbmem ${fbmem},10M
+ fi
+ setexpr nextcon $nextcon + 1
+else
+ echo "------ no ILI210x touch controller";
+fi
+
+if i2c probe 0x48 ; then
+ if itest.s "xqvga" == "x$panel" ; then
+ display="320x240MR@60,if=RGB24";
+ else
+ display="CLAA-WVGA,if=RGB666";
+ fi
+ setenv bootargs $bootargs video=mxcfb${nextcon}:dev=lcd,$display
+ if test "0" -eq $nextcon; then
+ setenv fbmem "fbmem=10M";
+ else
+ setenv fbmem ${fbmem},10M
+ fi
+ setexpr nextcon $nextcon + 1
+else
+ echo "------ no 800x480 display";
+fi
+
+if itest.s "x1080P" == "x$panel" ; then
+ setenv bootargs $bootargs ldb=spl0 video=mxcfb${nextcon}:dev=ldb,1920x1080MR@60,if=RGB24
+ if test "0" -eq $nextcon; then
+ setenv fbmem "fbmem=48M";
+ else
+ setenv fbmem ${fbmem},48M
+ fi
+ setexpr nextcon $nextcon + 1
+fi
+
+while test "4" -ne $nextcon ; do
+ setenv bootargs $bootargs video=mxcfb${nextcon}:off ;
+ setexpr nextcon $nextcon + 1 ;
+done
+
+setenv bootargs $bootargs $fbmem
+setenv bootargs "$bootargs console=ttymxc1,115200 vmalloc=400M consoleblank=0 rootwait fixrtc"
+
+if itest.s "x" != "x$wlmac" ; then
+ setenv bootargs $bootargs wlcore.mac=$wlmac
+fi
+
+if itest.s x$bootpart == x ; then
+ bootpart=1
+fi
+
+setenv bpart "$bootpart"
+
+if itest.s "$bpart" == a ; then
+ setenv bpart 10
+elif itest.s "$bpart" == b ; then
+ setenv bpart 11
+elif itest.s "$bpart" == c ; then
+ setenv bpart 12
+elif itest.s "$bpart" == d ; then
+ setenv bpart 13
+fi
+
+if test "sata" = "${dtype}" ; then
+ setenv bootargs "$bootargs root=/dev/sda$bpart" ;
+else
+ if test "usb" = "${dtype}" ; then
+ setenv bootargs "$bootargs root=/dev/sda$bpart" ;
+ elif itest 0 -eq ${disk}; then
+ setenv bootargs "$bootargs root=/dev/disk/by-path/platform-2198000.usdhc-part1" ;
+ else
+ setenv bootargs "$bootargs root=/dev/disk/by-path/platform-219c000.usdhc-part1" ;
+ fi
+fi
+
+
+
+if itest.s x == "x$dtbname" ; then
+ dtbname="imx6";
+ if itest.s x6SOLO == "x$cpu" ; then
+ dtbname=${dtbname}dl-;
+ elif itest.s x6DL == "x$cpu" ; then
+ dtbname=${dtbname}dl-;
+ else
+ dtbname=${dtbname}q-;
+ fi
+
+ if itest.s x == "x$board" ; then
+ board=sabrelite
+ fi
+
+ dtbname=${dtbname}${board}.dtb;
+fi
+
+if itest.s x == x${bootdir} ; then
+ bootdir=/boot
+fi
+
+if itest.s x == x${only_cea} ; then
+ if itest.s x == x$allow_noncea ; then
+ setenv only_cea 1
+ echo "only CEA modes allowed on HDMI port";
+ else
+ setenv only_cea 0
+ echo "non-CEA modes allowed on HDMI port, audio may be affected";
+ fi
+fi
+
+setenv bootargs $bootargs mxc_hdmi.only_cea=${only_cea}
+
+if itest.s "x" != "x${disable_giga}" ; then
+ setenv bootargs $bootargs fec.disable_giga=1
+fi
+
+if itest.s "x" != "x$gpumem" ; then
+ setenv bootargs $bootargs galcore.contiguousSize=$gpumem
+fi
+
+if itest.s "no" != "$dosplash" ; then
+ setenv bootargs $bootargs splash quiet plymouth.ignore-serial-consoles
+fi
+
+if itest.s "x" != "x$overlayfs" ; then
+ setenv bootargs $bootargs overlayfs=${overlayfs}
+ if itest.s "x" != "x${ofs-size}" ; then
+ setenv bootargs $bootargs ofs-size=${ofs-size}
+ fi
+fi
+
+if kbd ; then
+ if itest.s "xv" == "x$keybd" ; then
+ ${fs}load ${dtype} ${disk}:${bootpart} 0x10800000 ${bootdir}/uImage-recovery &&
+ ${fs}load ${dtype} ${disk}:${bootpart} 0x12800000 ${bootdir}/uramdisk-recovery.img &&
+ bootm 10800000 12800000;
+ echo "--- error launching recovery!"
+ exit;
+ fi
+fi
+
+setenv fdt_high 0xffffffff
+setenv initrd_high 0xffffffff
+
+setenv initrd_addr 0x12a00000
+setenv fdt_addr 0x13000000
+
+echo "----------- trying to load /initrd.img";
+if ${fs}load ${dtype} ${disk}:${bootpart} ${initrd_addr} /initrd.img ; then
+ haverd=1;
+ setenv initrd_size ${filesize}
+else
+ haverd=
+fi
+
+echo "----------- trying to load ${bootdir}/$dtbname";
+if ${fs}load ${dtype} ${disk}:${bootpart} ${fdt_addr} ${bootdir}/$dtbname ; then
+ havedtb=1;
+else
+ havedtb=
+fi
+
+if itest.s x$haverd == x ; then
+ if ${fs}load ${dtype} ${disk}:${bootpart} 0x10800000 /vmlinuz ; then
+ if itest.s x$havedtb == x ; then
+ bootz 0x10800000 ;
+ else
+ bootz 0x10800000 - ${fdt_addr}
+ fi
+ fi
+else
+ if ${fs}load ${dtype} ${disk}:${bootpart} 0x10800000 /vmlinuz ; then
+ if itest.s x$havedtb == x ; then
+ bootz 0x10800000 ${initrd_addr}:${initrd_size} ;
+ else
+ bootz 0x10800000 ${initrd_addr}:${initrd_size} ${fdt_addr} ;
+ fi
+ fi
+fi
+echo "Error loading kernel image"
diff --git a/board/boundary/nitrogen6x/6x_bootscript-ubuntu-3.10.53.txt b/board/boundary/nitrogen6x/6x_bootscript-ubuntu-3.10.53.txt
new file mode 100644
index 0000000000000000000000000000000000000000..6b9c34f078b6f9cd02a0304d617680a07843f4e4
--- /dev/null
+++ b/board/boundary/nitrogen6x/6x_bootscript-ubuntu-3.10.53.txt
@@ -0,0 +1,235 @@
+setenv bootargs ''
+
+if ${fs}load ${dtype} ${disk}:1 10800000 uEnv.txt ; then
+ env import -t 10800000 $filesize
+fi
+
+if itest.s "x" == "x$dtbname" ; then
+ dtbname="imx6";
+ if itest.s x6SOLO == "x$cpu" ; then
+ dtbname=${dtbname}dl-;
+ elif itest.s x6DL == "x$cpu" ; then
+ dtbname=${dtbname}dl-;
+ else
+ dtbname=${dtbname}q-;
+ fi
+ if itest.s x == "x$board" ; then
+ board=sabrelite
+ fi
+ dtbname=${dtbname}${board}.dtb;
+fi
+
+if itest.s x == x${bootdir} ; then
+ bootdir=/boot/
+fi
+
+if itest.s x$bootpart == x ; then
+ bootpart=1
+fi
+
+setenv fdt_addr 0x12000000
+if ${fs}load ${dtype} ${disk}:${bootpart} $fdt_addr ${bootdir}$dtbname ; then
+ fdt addr $fdt_addr
+ setenv fdt_high 0xffffffff
+else
+ echo "!!!! Error loading ${bootdir}$dtbname";
+ exit;
+fi
+
+# ------------------- HDMI detection
+i2c dev 1 ;
+if i2c probe 0x50 ; then
+ echo "------ have HDMI monitor";
+ if itest.s x == x$allow_noncea ; then
+ setenv bootargs $bootargs mxc_hdmi.only_cea=1;
+ echo "only CEA modes allowed on HDMI port";
+ else
+ setenv bootargs $bootargs mxc_hdmi.only_cea=0;
+ echo "non-CEA modes allowed on HDMI, audio may be affected";
+ fi
+else
+ fdt rm hdmi_display
+ echo "------ no HDMI monitor";
+fi
+
+# ------------------- LVDS detection
+if itest.s "x" != "x$lvds_1080p" ; then
+ echo "----- 1080P dual channel LVDS";
+ fdt rm okaya1024x600
+ fdt rm lg1280x800
+ fdt rm hannstar;
+ fdt set ldb split-mode 1
+ fdt set lvds_display interface_pix_fmt "RGB24"
+ fdt set ldb/lvds-channel@0 fsl,data-width <24>
+else
+ fdt rm ldb split-mode
+ fdt rm lvds1080p
+
+ # -------- LVDS0 (bottom on Nitrogen6_Max)
+ setenv have_lvds
+ i2c dev 2
+ if i2c probe 0x04 ; then
+ echo "------ have Freescale display";
+ setenv have_lvds 1
+ else
+ echo "------ no Freescale display";
+ fdt rm hannstar;
+ fi
+
+ if i2c probe 0x38 ; then
+ if itest.s "xLDB-WXGA" == "x$panel"; then
+ screenres=1280,800
+ fdt rm okaya1024x600
+ else
+ screenres=1024,600
+ fdt rm lg1280x800
+ fi
+ setenv have_lvds 1
+ setenv bootargs $bootargs ft5x06_ts.screenres=$screenres
+ if itest.s "x" -ne "x$calibration" ; then
+ setenv bootargs $bootargs ft5x06_ts.calibration=$calibration
+ fi
+ else
+ echo "------ no ft5x06 touch controller";
+ fdt rm okaya1024x600
+ fdt rm lg1280x800
+ fi
+
+ if itest.s "x" == "x$have_lvds"; then
+ fdt rm lvds_display;
+ fi
+
+ # -------- LVDS1 (top on Nitrogen6_Max)
+ if itest.s "xhannstar" == "x$lvds1_panel" ; then
+ echo "configure LVDS1 for Hannstar panel"
+ fdt rm okaya1024x600_2;
+ fdt rm lg1280x800_2;
+ fdt set lvds_display_2 status okay
+ elif itest.s "xokaya1024x600" == "x$lvds1_panel" ; then
+ echo "configure LVDS1 for 1024x600 panel"
+ fdt rm hannstar_2;
+ fdt rm lg1280x800_2;
+ fdt set lvds_display_2 status okay
+ elif itest.s "xlg1280x800" == "x$lvds1_panel" ; then
+ echo "configure LVDS1 for 1280x800 panel"
+ fdt rm hannstar_2;
+ fdt rm okaya1024x600_2;
+ fdt set lvds_display_2 status okay
+ else
+ fdt rm lvds_display_2 ; # ignore errors on boards != 6_max
+ fi
+fi
+
+# ------------------- LCD detection
+setenv have_lcd '';
+if i2c probe 0x48 ; then
+ setenv have_lcd 1;
+ echo "------- found TSC2004 touch controller";
+ if itest.s "x" -eq "x$tsc_calibration" ; then
+ setenv bootargs $bootargs tsc2004.calibration=-67247,-764,272499173,324,69283,-8653010,65536
+ else
+ setenv bootargs $bootargs tsc2004.calibration=$tsc_calibration
+ fi
+elif i2c probe 0x4d ; then
+ setenv have_lcd 1;
+ echo "------- found AR1020 touch controller";
+fi
+
+if itest.s "x" != "x$ignore_lcd" ; then
+ echo "------ ignoring LCD display";
+ setenv have_lcd '';
+fi
+
+if itest.s "x" != "x$have_lcd" ; then
+ echo "----- found LCD display";
+else
+ fdt rm lcd_display;
+fi
+
+setenv bootargs "$bootargs console=ttymxc1,115200 vmalloc=400M consoleblank=0 rootwait fixrtc"
+
+setenv bpart "$bootpart"
+
+if itest.s "$bpart" == a ; then
+ setenv bpart 10
+elif itest.s "$bpart" == b ; then
+ setenv bpart 11
+elif itest.s "$bpart" == c ; then
+ setenv bpart 12
+elif itest.s "$bpart" == d ; then
+ setenv bpart 13
+fi
+
+if test "sata" = "${dtype}" ; then
+ setenv bootargs "$bootargs root=/dev/sda$bpart" ;
+else
+ if test "usb" = "${dtype}" ; then
+ setenv bootargs "$bootargs root=/dev/sda$bpart" ;
+ elif itest 0 -eq ${disk}; then
+ setenv bootargs "$bootargs root=/dev/disk/by-path/platform-2198000.usdhc-part1" ;
+ else
+ setenv bootargs "$bootargs root=/dev/disk/by-path/platform-219c000.usdhc-part1" ;
+ fi
+fi
+
+if itest.s "x" != "x${disable_giga}" ; then
+ setenv bootargs $bootargs fec.disable_giga=1
+fi
+
+if itest.s "x" != "x$wlmac" ; then
+ setenv bootargs $bootargs wlcore.mac=$wlmac
+fi
+
+if itest.s "x" != "x$gpumem" ; then
+ setenv bootargs $bootargs galcore.contiguousSize=$gpumem
+fi
+
+if itest.s "no" != "$dosplash" ; then
+ setenv bootargs $bootargs splash quiet plymouth.ignore-serial-consoles
+fi
+
+if itest.s "x" != "x$overlayfs" ; then
+ setenv bootargs $bootargs overlayfs=${overlayfs}
+ if itest.s "x" != "x${ofs-size}" ; then
+ setenv bootargs $bootargs ofs-size=${ofs-size}
+ fi
+fi
+
+if itest.s "x" != "x$show_fdt" ; then
+ fdt print /
+fi
+
+if itest.s "x" != "x$show_env" ; then
+ printenv
+fi
+
+if kbd ; then
+ if itest.s "xv" == "x$keybd" ; then
+ ${fs}load ${dtype} ${disk}:${bootpart} 0x10800000 ${bootdir}/uImage-recovery &&
+ ${fs}load ${dtype} ${disk}:${bootpart} 0x12800000 ${bootdir}/uramdisk-recovery.img &&
+ bootm 10800000 12800000;
+ echo "--- error launching recovery!"
+ exit;
+ fi
+fi
+
+setenv initrd_high 0xffffffff
+setenv initrd_addr 0x12a00000
+echo "----------- trying to load /initrd.img";
+if ${fs}load ${dtype} ${disk}:${bootpart} ${initrd_addr} /initrd.img ; then
+ haverd=1;
+ setenv initrd_size ${filesize}
+else
+ haverd=
+fi
+
+if itest.s x$haverd == x ; then
+ if ${fs}load ${dtype} ${disk}:${bootpart} 0x10800000 /vmlinuz ; then
+ bootz 0x10800000 - ${fdt_addr}
+ fi
+else
+ if ${fs}load ${dtype} ${disk}:${bootpart} 0x10800000 /vmlinuz ; then
+ bootz 0x10800000 ${initrd_addr}:${initrd_size} ${fdt_addr} ;
+ fi
+fi
+echo "Error loading kernel image"
diff --git a/board/boundary/nitrogen6x/6x_bootscript-ubuntu-3.14.txt b/board/boundary/nitrogen6x/6x_bootscript-ubuntu-3.14.txt
new file mode 100644
index 0000000000000000000000000000000000000000..29786c2716e76a6210847f976516b323244099a0
--- /dev/null
+++ b/board/boundary/nitrogen6x/6x_bootscript-ubuntu-3.14.txt
@@ -0,0 +1,212 @@
+setenv bootargs ''
+
+setenv initrd_high 0xffffffff
+m4=''
+a_base=0x10000000
+if itest.s x51 == "x${cpu}" ; then
+ a_base=0x90000000
+elif itest.s x53 == "x${cpu}"; then
+ a_base=0x70000000
+elif itest.s x6SX == "x${cpu}" || itest.s x7D == "x${cpu}"; then
+ a_base=0x80000000
+ if itest.s "x1" == "x$m4enabled" ; then
+ run m4boot;
+ m4='-m4';
+ fi
+fi
+
+setexpr a_script ${a_base} + 0x00800000
+setexpr a_zImage ${a_base} + 0x00800000
+setexpr a_fdt ${a_base} + 0x03000000
+setexpr a_ramdisk ${a_base} + 0x03800000
+setexpr a_initrd ${a_base} + 0x03a00000
+setexpr a_reset_cause_marker ${a_base} + 0x80
+setexpr a_reset_cause ${a_base} + 0x84
+
+if itest.s "x" == "x${board}" ; then
+ echo "!!!! Error: Your u-boot is outdated. Please upgrade.";
+ exit;
+fi
+
+if itest.s "x" == "x${dtbname}" ; then
+ if itest.s x6SOLO == "x${cpu}" ; then
+ dtbname=imx6dl-${board}.dtb;
+ elif itest.s x6DL == "x${cpu}" ; then
+ dtbname=imx6dl-${board}.dtb;
+ elif itest.s x6QP == "x${cpu}" ; then
+ dtbname=imx6qp-${board}.dtb;
+ elif itest.s x6SX == "x${cpu}" ; then
+ dtbname=imx6sx-${board}${m4}.dtb;
+ elif itest.s x7D == "x${cpu}" ; then
+ dtbname=imx7d-${board}${m4}.dtb;
+ elif itest.s x51 == "x${cpu}" ; then
+ dtbname=imx51-${board}${m4}.dtb;
+ elif itest.s x53 == "x${cpu}" ; then
+ dtbname=imx53-${board}${m4}.dtb;
+ else
+ dtbname=imx6q-${board}.dtb;
+ fi
+fi
+
+if itest.s x${bootpart} == x ; then
+ bootpart=1
+fi
+
+if load ${dtype} ${disk}:${bootpart} ${a_script} uEnv.txt ; then
+ env import -t ${a_script} ${filesize}
+fi
+setenv bootargs ${bootargs} console=${console},115200 vmalloc=400M consoleblank=0 rootwait fixrtc cpu=${cpu} board=${board}
+
+if itest.s x == x${bootdir} ; then
+ bootdir=/boot/
+fi
+
+if load ${dtype} ${disk}:${bootpart} ${a_fdt} ${bootdir}${dtbname} ; then
+ fdt addr ${a_fdt}
+ setenv fdt_high 0xffffffff
+else
+ echo "!!!! Error loading ${bootdir}${dtbname}";
+ exit;
+fi
+
+cmd_xxx_present=
+fdt resize
+if itest.s "x" != "x${cmd_custom}" ; then
+ run cmd_custom
+ cmd_xxx_present=1;
+fi
+
+if itest.s "x" != "x${cmd_hdmi}" ; then
+ run cmd_hdmi
+ cmd_xxx_present=1;
+ if itest.s x == x${allow_noncea} ; then
+ setenv bootargs ${bootargs} mxc_hdmi.only_cea=1;
+ echo "only CEA modes allowed on HDMI port";
+ else
+ setenv bootargs ${bootargs} mxc_hdmi.only_cea=0;
+ echo "non-CEA modes allowed on HDMI, audio may be affected";
+ fi
+fi
+
+if itest.s "x" != "x${cmd_lcd}" ; then
+ run cmd_lcd
+ cmd_xxx_present=1;
+fi
+if itest.s "x" != "x${cmd_lcd2}" ; then
+ run cmd_lcd2
+ cmd_xxx_present=1;
+fi
+if itest.s "x" != "x${cmd_lvds}" ; then
+ run cmd_lvds
+ cmd_xxx_present=1;
+fi
+if itest.s "x" != "x${cmd_lvds2}" ; then
+ run cmd_lvds2
+ cmd_xxx_present=1;
+fi
+
+if itest.s "x" == "x${cmd_xxx_present}" ; then
+ echo "!!!!!!!!!!!!!!!!"
+ echo "warning: your u-boot may be outdated, please upgrade"
+ echo "!!!!!!!!!!!!!!!!"
+fi
+
+setexpr b0 ${bootpart} % 0x0a;
+setexpr b1 ${bootpart} / 0x0a;
+#this is to show a decimal number when really hex is output
+setexpr bpart ${b1} * 0x10
+setexpr bpart ${bpart} + ${b0};
+
+if test "sata" = "${dtype}" ; then
+ setenv bootargs "${bootargs} root=/dev/sda${bpart}" ;
+elif test "usb" = "${dtype}" ; then
+ setenv bootargs "${bootargs} root=/dev/sda${bpart}" ;
+else
+ setenv bootargs "${bootargs} root=/dev/mmcblk${disk}p${bpart}"
+fi
+
+if itest.s "x" != "x${disable_msi}" ; then
+ setenv bootargs ${bootargs} pci=nomsi
+fi;
+
+if itest.s "x" != "x${disable_giga}" ; then
+ setenv bootargs ${bootargs} fec.disable_giga=1
+fi
+
+if itest.s "x" != "x${wlmac}" ; then
+ setenv bootargs ${bootargs} wlan.mac=${wlmac} wlcore.mac=${wlmac}
+fi
+
+if itest.s "x" != "x${bd_addr}" ; then
+ setenv bootargs ${bootargs} bd_addr=${bd_addr}
+fi
+
+if itest.s "x" != "x${gpumem}" ; then
+ setenv bootargs ${bootargs} galcore.contiguousSize=${gpumem}
+fi
+
+
+if itest.s "no" != "${dosplash}" ; then
+ if itest.s "x" == "x${loglevel}" ; then
+ loglevel=4
+ fi
+ setenv bootargs ${bootargs} splash plymouth.ignore-serial-consoles
+fi
+
+if itest.s "x" != "x${loglevel}" ; then
+ setenv bootargs ${bootargs} loglevel=${loglevel}
+fi
+
+if itest *${a_reset_cause_marker} == 12345678 ; then
+ setexpr.l reset_cause *${a_reset_cause}
+ setenv bootargs $bootargs reset_cause=0x${reset_cause}
+fi
+
+if itest.s "x" != "x${overlayfs}" ; then
+ setenv bootargs ${bootargs} overlayfs=${overlayfs}
+ if itest.s "x" != "x${ofs-size}" ; then
+ setenv bootargs ${bootargs} ofs-size=${ofs-size}
+ fi
+fi
+
+if itest.s "x" != "x${cma}" ; then
+ setenv bootargs ${bootargs} cma=${cma}
+fi
+
+if itest.s "x" != "x${show_fdt}" ; then
+ fdt print /
+fi
+
+if itest.s "x" != "x${show_env}" ; then
+ printenv
+fi
+
+if kbd ; then
+ if itest.s "xv" == "x${keybd}" ; then
+ load ${dtype} ${disk}:${bootpart} ${a_zImage} ${bootdir}/uImage-recovery &&
+ load ${dtype} ${disk}:${bootpart} ${a_ramdisk} ${bootdir}/uramdisk-recovery.img &&
+ bootm ${a_zImage} ${a_ramdisk};
+ echo "--- error launching recovery!"
+ exit;
+ fi
+fi
+
+echo "----------- trying to load /initrd.img";
+if load ${dtype} ${disk}:${bootpart} ${a_initrd} /initrd.img ; then
+ haverd=1;
+ setenv initrd_size ${filesize}
+else
+ haverd=
+fi
+
+if itest.s x${haverd} == x ; then
+ if load ${dtype} ${disk}:${bootpart} ${a_zImage} /vmlinuz ; then
+ setenv bootargs ${bootargs} rw
+ bootz ${a_zImage} - ${a_fdt}
+ fi
+else
+ if load ${dtype} ${disk}:${bootpart} ${a_zImage} /vmlinuz ; then
+ bootz ${a_zImage} ${a_initrd}:${initrd_size} ${a_fdt} ;
+ fi
+fi
+echo "Error loading kernel image"
diff --git a/board/boundary/nitrogen6x/6x_bootscript-yocto-3.14.txt b/board/boundary/nitrogen6x/6x_bootscript-yocto-3.14.txt
new file mode 100644
index 0000000000000000000000000000000000000000..ad30e80c465f14a7d3397c4df05b8d599f62f811
--- /dev/null
+++ b/board/boundary/nitrogen6x/6x_bootscript-yocto-3.14.txt
@@ -0,0 +1,168 @@
+setenv bootargs ''
+
+setenv initrd_high 0xffffffff
+m4=''
+a_base=0x10000000
+if itest.s x51 == "x${cpu}" ; then
+ a_base=0x90000000
+elif itest.s x53 == "x${cpu}"; then
+ a_base=0x70000000
+elif itest.s x6SX == "x${cpu}" || itest.s x7D == "x${cpu}"; then
+ a_base=0x80000000
+ if itest.s "x1" == "x$m4enabled" ; then
+ run m4boot;
+ m4='-m4';
+ fi
+fi
+
+setexpr a_script ${a_base} + 0x00800000
+setexpr a_zImage ${a_base} + 0x00800000
+setexpr a_fdt ${a_base} + 0x03000000
+setexpr a_ramdisk ${a_base} + 0x03800000
+setexpr a_initrd ${a_base} + 0x03a00000
+setexpr a_reset_cause_marker ${a_base} + 0x80
+setexpr a_reset_cause ${a_base} + 0x84
+
+if itest.s "x" == "x${board}" ; then
+ echo "!!!! Error: Your u-boot is outdated. Please upgrade.";
+ exit;
+fi
+
+if itest.s "x" == "x${dtbname}" ; then
+ if itest.s x6SOLO == "x${cpu}" ; then
+ dtbname=imx6dl-${board}.dtb;
+ elif itest.s x6DL == "x${cpu}" ; then
+ dtbname=imx6dl-${board}.dtb;
+ elif itest.s x6QP == "x${cpu}" ; then
+ dtbname=imx6qp-${board}.dtb;
+ elif itest.s x6SX == "x${cpu}" ; then
+ dtbname=imx6sx-${board}${m4}.dtb;
+ elif itest.s x7D == "x${cpu}" ; then
+ dtbname=imx7d-${board}${m4}.dtb;
+ elif itest.s x51 == "x${cpu}" ; then
+ dtbname=imx51-${board}${m4}.dtb;
+ elif itest.s x53 == "x${cpu}" ; then
+ dtbname=imx53-${board}${m4}.dtb;
+ else
+ dtbname=imx6q-${board}.dtb;
+ fi
+fi
+
+if itest.s x${bootpart} == x ; then
+ bootpart=1
+fi
+
+if load ${dtype} ${disk}:${bootpart} ${a_script} uEnv.txt ; then
+ env import -t ${a_script} ${filesize}
+fi
+setenv bootargs ${bootargs} console=${console},115200 vmalloc=400M consoleblank=0 rootwait fixrtc cpu=${cpu} board=${board}
+
+if itest.s x == x${bootdir} ; then
+ bootdir=/
+fi
+
+if load ${dtype} ${disk}:${bootpart} ${a_fdt} ${bootdir}${dtbname} ; then
+ fdt addr ${a_fdt}
+ setenv fdt_high 0xffffffff
+else
+ echo "!!!! Error loading ${bootdir}${dtbname}";
+ exit;
+fi
+
+cmd_xxx_present=
+fdt resize
+if itest.s "x" != "x${cmd_custom}" ; then
+ run cmd_custom
+ cmd_xxx_present=1;
+fi
+
+if itest.s "x" != "x${cmd_hdmi}" ; then
+ run cmd_hdmi
+ cmd_xxx_present=1;
+ if itest.s x == x${allow_noncea} ; then
+ setenv bootargs ${bootargs} mxc_hdmi.only_cea=1;
+ echo "only CEA modes allowed on HDMI port";
+ else
+ setenv bootargs ${bootargs} mxc_hdmi.only_cea=0;
+ echo "non-CEA modes allowed on HDMI, audio may be affected";
+ fi
+fi
+
+if itest.s "x" != "x${cmd_lcd}" ; then
+ run cmd_lcd
+ cmd_xxx_present=1;
+fi
+if itest.s "x" != "x${cmd_lcd2}" ; then
+ run cmd_lcd2
+ cmd_xxx_present=1;
+fi
+if itest.s "x" != "x${cmd_lvds}" ; then
+ run cmd_lvds
+ cmd_xxx_present=1;
+fi
+if itest.s "x" != "x${cmd_lvds2}" ; then
+ run cmd_lvds2
+ cmd_xxx_present=1;
+fi
+
+if itest.s "x" == "x${cmd_xxx_present}" ; then
+ echo "!!!!!!!!!!!!!!!!"
+ echo "warning: your u-boot may be outdated, please upgrade"
+ echo "!!!!!!!!!!!!!!!!"
+fi
+
+bpart=2
+
+if test "sata" = "${dtype}" ; then
+ setenv bootargs "${bootargs} root=/dev/sda${bpart}" ;
+elif test "usb" = "${dtype}" ; then
+ setenv bootargs "${bootargs} root=/dev/sda${bpart}" ;
+else
+ setenv bootargs "${bootargs} root=/dev/mmcblk${disk}p${bpart}"
+fi
+
+if itest.s "x" != "x${disable_msi}" ; then
+ setenv bootargs ${bootargs} pci=nomsi
+fi;
+
+if itest.s "x" != "x${disable_giga}" ; then
+ setenv bootargs ${bootargs} fec.disable_giga=1
+fi
+
+if itest.s "x" != "x${wlmac}" ; then
+ setenv bootargs ${bootargs} wlan.mac=${wlmac} wlcore.mac=${wlmac}
+fi
+
+if itest.s "x" != "x${bd_addr}" ; then
+ setenv bootargs ${bootargs} bd_addr=${bd_addr}
+fi
+
+if itest.s "x" != "x${gpumem}" ; then
+ setenv bootargs ${bootargs} galcore.contiguousSize=${gpumem}
+fi
+
+if itest.s "x" != "x${cma}" ; then
+ setenv bootargs ${bootargs} cma=${cma}
+fi
+
+if itest.s "x" != "x${loglevel}" ; then
+ setenv bootargs ${bootargs} loglevel=${loglevel}
+fi
+
+if itest *${a_reset_cause_marker} == 12345678 ; then
+ setexpr.l reset_cause *${a_reset_cause}
+ setenv bootargs $bootargs reset_cause=0x${reset_cause}
+fi
+
+if itest.s "x" != "x${show_fdt}" ; then
+ fdt print /
+fi
+
+if itest.s "x" != "x${show_env}" ; then
+ printenv
+fi
+
+if load ${dtype} ${disk}:${bootpart} ${a_zImage} /zImage ; then
+ bootz ${a_zImage} - ${a_fdt}
+fi
+echo "Error loading kernel image"
diff --git a/board/boundary/nitrogen6x/6x_bootscript.txt b/board/boundary/nitrogen6x/6x_bootscript.txt
index 061b3a44b5ad306d39980068be0a14c541aa04d1..a1fd0da6821bff5bf108c1cd15496ad71b8a8db9 100644
--- a/board/boundary/nitrogen6x/6x_bootscript.txt
+++ b/board/boundary/nitrogen6x/6x_bootscript.txt
@@ -1,7 +1,13 @@
-setenv bootargs enable_wait_mode=off
+if ${fs}load ${dtype} ${disk}:1 10800000 uEnv.txt ; then
+ env import -t 10800000 $filesize
+else
+ setenv bootargs enable_wait_mode=off
+fi
+
setenv nextcon 0;
-if hdmidet ; then
+i2c dev 1 ;
+if i2c probe 0x50 ; then
setenv bootargs $bootargs video=mxcfb${nextcon}:dev=hdmi,1280x720M@60,if=RGB24
setenv fbmem "fbmem=28M";
setexpr nextcon $nextcon + 1
@@ -23,7 +29,29 @@ else
fi
if i2c probe 0x38 ; then
- setenv bootargs $bootargs video=mxcfb${nextcon}:dev=ldb,1024x600M@60,if=RGB666
+ if itest.s "xLDB-WXGA" == "x$panel"; then
+ setenv bootargs $bootargs video=mxcfb${nextcon}:dev=ldb,1280x800MR@60,if=RGB666
+ screenres=1280,800
+ else
+ setenv bootargs $bootargs video=mxcfb${nextcon}:dev=ldb,1024x600M@60,if=RGB666
+ screenres=1024,600
+ fi
+ if test "0" -eq $nextcon; then
+ setenv fbmem "fbmem=10M";
+ else
+ setenv fbmem ${fbmem},10M
+ fi
+ setexpr nextcon $nextcon + 1
+ setenv bootargs $bootargs ft5x06_ts.screenres=$screenres
+ if itest.s "x" -ne "x$calibration" ; then
+ setenv bootargs $bootargs ft5x06_ts.calibration=$calibration
+ fi
+else
+ echo "------ no ft5x06 touch controller";
+fi
+
+if i2c probe 0x41 ; then
+ setenv bootargs $bootargs video=mxcfb${nextcon}:dev=ldb,1024x600M@60,if=RGB666
if test "0" -eq $nextcon; then
setenv fbmem "fbmem=10M";
else
@@ -31,11 +59,16 @@ if i2c probe 0x38 ; then
fi
setexpr nextcon $nextcon + 1
else
- echo "------ no 1024x600 display";
+ echo "------ no ILI210x touch controller";
fi
if i2c probe 0x48 ; then
- setenv bootargs $bootargs video=mxcfb${nextcon}:dev=lcd,CLAA-WVGA,if=RGB666
+ if itest.s "xqvga" == "x$panel" ; then
+ display="320x240MR@60,if=RGB24";
+ else
+ display="CLAA-WVGA,if=RGB666";
+ fi
+ setenv bootargs $bootargs video=mxcfb${nextcon}:dev=lcd,$display
if test "0" -eq $nextcon; then
setenv fbmem "fbmem=10M";
else
@@ -46,7 +79,7 @@ else
echo "------ no 800x480 display";
fi
-while test "3" -ne $nextcon ; do
+while test "4" -ne $nextcon ; do
setenv bootargs $bootargs video=mxcfb${nextcon}:off ;
setexpr nextcon $nextcon + 1 ;
done
@@ -54,10 +87,71 @@ done
setenv bootargs $bootargs $fbmem
setenv bootargs "$bootargs console=ttymxc1,115200 vmalloc=400M consoleblank=0 rootwait"
+if itest.s x$bootpart == x ; then
+ bootpart=1
+fi
+
if test "sata" = "${dtype}" ; then
- setenv bootargs "$bootargs root=/dev/sda1" ;
+ setenv bootargs "$bootargs root=/dev/sda$bootpart" ;
+else
+ if test "usb" = "${dtype}" ; then
+ setenv bootargs "$bootargs root=/dev/sda$bootpart" ;
+ elif itest.s "x" == "x$sdphys" ; then
+ setenv bootargs "$bootargs root=/dev/mmcblk0p$bootpart" ;
+ elif itest 0 -eq ${disk}; then
+ setenv bootargs "$bootargs root=/dev/mmcblk2p$bootpart" ;
+ else
+ setenv bootargs "$bootargs root=/dev/mmcblk3p$bootpart" ;
+ fi
+fi
+
+dtbname="imx6";
+if itest.s x6SOLO == "x$cpu" ; then
+ dtbname=${dtbname}dl-;
+elif itest.s x6DL == "x$cpu" ; then
+ dtbname=${dtbname}dl-;
+else
+ dtbname=${dtbname}q-;
+fi
+
+if itest.s x == "x$board" ; then
+ board=sabrelite
+fi
+dtbname=${dtbname}${board}.dtb;
+
+if itest.s x == x${bootdir} ; then
+ bootdir=/boot/
+fi
+
+if ${fs}load ${dtype} ${disk}:1 12000000 ${bootdir}$dtbname ; then
+ havedtb=1;
+ setenv fdt_addr 0x11000000
+ setenv fdt_high 0xffffffff
+else
+ havedtb=
+fi
+
+if itest.s x == x$allow_noncea ; then
+ setenv bootargs $bootargs mxc_hdmi.only_cea=1;
+ echo "only CEA modes allowed on HDMI port";
else
- setenv "bootargs $bootargs root=/dev/mmcblk0p1" ;
+ setenv bootargs $bootargs mxc_hdmi.only_cea=0;
+ echo "non-CEA modes allowed on HDMI, audio may be affected";
+fi
+
+if itest.s "x" != "x$disable_giga" ; then
+ setenv bootargs $bootargs fec.disable_giga=1
+fi
+
+if itest.s "x" != "x$wlmac" ; then
+ setenv bootargs $bootargs wlcore.mac=$wlmac
+fi
+
+if ${fs}load ${dtype} ${disk}:1 10800000 ${bootdir}uImage ; then
+ if itest.s x$havedtb == x ; then
+ bootm 10800000 ;
+ else
+ bootm 10800000 - 12000000
+ fi
fi
-${fs}load ${dtype} ${disk}:1 10800000 /boot/uImage && bootm 10800000 ;
echo "Error loading kernel image"
diff --git a/board/boundary/nitrogen6x/6x_bootscript_android.txt b/board/boundary/nitrogen6x/6x_bootscript_android.txt
index 0982cf8054350381fb5332590c48c2b209ab8107..088f83020952fb75760d6d023b74ec19d0265762 100644
--- a/board/boundary/nitrogen6x/6x_bootscript_android.txt
+++ b/board/boundary/nitrogen6x/6x_bootscript_android.txt
@@ -9,9 +9,9 @@ i2c dev 2
if i2c probe 0x04 ; then
setenv bootargs $bootargs video=mxcfb${nextcon}:dev=ldb,LDB-XGA,if=RGB666
if test "0" -eq $nextcon; then
- setenv fbcon "fbcon=10M";
+ setenv fbmem "fbmem=10M";
else
- setenv fbcon ${fbcon},10M
+ setenv fbmem ${fbmem},10M
fi
setexpr nextcon $nextcon + 1
else
@@ -21,9 +21,9 @@ fi
if i2c probe 0x38 ; then
setenv bootargs $bootargs video=mxcfb${nextcon}:dev=ldb,1024x600M@60,if=RGB666
if test "0" -eq $nextcon; then
- setenv fbcon "fbcon=10M";
+ setenv fbmem "fbmem=10M";
else
- setenv fbcon ${fbcon},10M
+ setenv fbmem ${fbmem},10M
fi
setexpr nextcon $nextcon + 1
else
@@ -33,9 +33,9 @@ fi
if i2c probe 0x48 ; then
setenv bootargs $bootargs video=mxcfb${nextcon}:dev=lcd,CLAA-WVGA,if=RGB666 tsdev=tsc2004 calibration
if test "0" -eq $nextcon; then
- setenv fbcon "fbcon=10M";
+ setenv fbmem "fbmem=10M";
else
- setenv fbcon ${fbcon},10M
+ setenv fbmem ${fbmem},10M
fi
setexpr nextcon $nextcon + 1
else
@@ -45,9 +45,9 @@ fi
if hdmidet ; then
setenv bootargs $bootargs video=mxcfb${nextcon}:dev=hdmi,1280x720M@60,if=RGB24
if test "0" -eq $nextcon; then
- setenv fbcon "fbcon=28M";
+ setenv fbmem "fbmem=28M";
else
- setenv fbcon ${fbcon},28M
+ setenv fbmem ${fbmem},28M
fi
setexpr nextcon $nextcon + 1
else
@@ -59,6 +59,6 @@ while test "3" -ne $nextcon ; do
setexpr nextcon $nextcon + 1 ;
done
-setenv bootargs $bootargs fbcon=$fbcon
+setenv bootargs $bootargs $fbmem
${fs}load ${dtype} ${disk}:1 10800000 uImage && ${fs}load ${dtype} ${disk}:1 12800000 uramdisk.img && bootm 10800000 12800000
echo "Error loading kernel image"
diff --git a/board/boundary/nitrogen6x/6x_upgrade.txt b/board/boundary/nitrogen6x/6x_upgrade.txt
index 1a62bbf12ef3a06e1ddea0b2ade16d8af6b980e4..86520e887fb6cfd112de525b91fa7ca84686ddc9 100644
--- a/board/boundary/nitrogen6x/6x_upgrade.txt
+++ b/board/boundary/nitrogen6x/6x_upgrade.txt
@@ -1,45 +1,154 @@
+if itest.s a$uboot_defconfig == a; then
+ echo "Please set uboot_defconfig to the appropriate value"
+ exit
+fi
+
+offset=0x400
+erase_size=0xC0000
+qspi_offset=0x0
+a_base=0x12000000
+
+if itest.s x51 == "x${cpu}"; then
+ a_base=0x92000000
+elif itest.s x53 == "x${cpu}"; then
+ a_base=0x72000000
+elif itest.s x6SX == "x${cpu}" || itest.s x7D == "x${cpu}"; then
+ a_base=0x82000000
+fi
+
+qspi_match=1
+setexpr a_qspi1 ${a_base}
+setexpr a_qspi2 ${a_qspi1} + 0x400000
+setexpr a_uImage1 ${a_qspi1} + 0x400
+setexpr a_uImage2 ${a_qspi2} + 0x400
+setexpr a_script ${a_base}
+
setenv stdout serial,vga
+
+if sf probe || sf probe || sf probe 1 27000000 || sf probe 1 27000000 ; then
+ echo "probed SPI ROM" ;
+else
+ echo "Error initializing EEPROM"
+ exit
+fi
+
+if itest.s x7D == "x${cpu}"; then
+ echo "check qspi parameter block" ;
+ if ${fs}load ${dtype} ${disk}:1 ${a_qspi1} qspi-${sfname}.${uboot_defconfig} ; then
+ else
+ echo "parameter file qspi-${sfname}.${uboot_defconfig} not found on SD card"
+ exit
+ fi
+ if itest ${filesize} != 0x200 ; then
+ echo "------- qspi-${sfname}.${uboot_defconfig} 0x${filesize} != 0x200 bytes" ;
+ exit
+ fi
+ setexpr a_marker ${a_qspi1} + 0x1fc
+ if itest *${a_marker} != c0ffee01 ; then
+ echo "------- qspi-${sfname}.${uboot_defconfig} c0ffee01 marker missing" ;
+ exit
+ fi
+ if sf read ${a_qspi2} ${qspi_offset} 0x200 ; then
+ else
+ echo "Error reading qspi parameter from EEPROM"
+ exit
+ fi
+ if cmp.b ${a_qspi1} ${a_qspi2} 0x200 ; then
+ echo "------- qspi parameters match"
+ else
+ echo "------- qspi parameters mismatch"
+ qspi_match=0
+ fi
+fi
+
echo "check U-Boot" ;
-setenv offset 0x400
-if ${fs}load ${dtype} ${disk}:1 12000000 u-boot.imx || ${fs}load ${dtype} ${disk}:1 12000000 u-boot.nopadding ; then
- echo "read $filesize bytes from SD card" ;
- if sf probe || sf probe || \
- sf probe 1 27000000 || sf probe 1 27000000 ; then
- echo "probed SPI ROM" ;
- if sf read 0x12400000 $offset $filesize ; then
- if cmp.b 0x12000000 0x12400000 $filesize ; then
- echo "------- U-Boot versions match" ;
- else
- echo "Need U-Boot upgrade" ;
- echo "Program in 5 seconds" ;
- for n in 5 4 3 2 1 ; do
- echo $n ;
- sleep 1 ;
- done
- echo "erasing" ;
- sf erase 0 0xC0000 ;
- # two steps to prevent bricking
- echo "programming" ;
- sf write 0x12000000 $offset $filesize ;
- echo "verifying" ;
- if sf read 0x12400000 $offset $filesize ; then
- if cmp.b 0x12000000 0x12400000 $filesize ; then
- while echo "---- U-Boot upgraded. reset" ; do
- sleep 120
- done
- else
- echo "Read verification error" ;
- fi
- else
- echo "Error re-reading EEPROM" ;
- fi
- fi
- else
- echo "Error reading boot loader from EEPROM" ;
- fi
- else
- echo "Error initializing EEPROM" ;
- fi ;
+
+if ${fs}load ${dtype} ${disk}:1 ${a_uImage1} u-boot.$uboot_defconfig ; then
+else
+ echo "File u-boot.$uboot_defconfig not found on SD card" ;
+ exit
+fi
+echo "read $filesize bytes from SD card" ;
+if sf read ${a_uImage2} $offset $filesize ; then
else
- echo "No U-Boot image found on SD card" ;
+ echo "Error reading boot loader from EEPROM" ;
+ exit
+fi
+
+if cmp.b ${a_uImage1} ${a_uImage2} $filesize ; then
+ echo "------- U-Boot versions match" ;
+ if itest.s "${qspi_match}" == "1" ; then
+ echo "------- upgrade not needed" ;
+ if itest.s "x" != "x${next}" ; then
+ if ${fs}load ${dtype} ${disk}:1 ${a_script} ${next} ; then
+ source ${a_script}
+ else
+ echo "${next} not found on SD card"
+ fi
+ fi
+ exit
+ fi
+ erase_size=0x1000
+ if itest.s xMX25L6405D == "x${sfname}"; then
+ erase_size=0x10000
+ fi
+ setexpr filesize ${erase_size} - ${offset}
+fi
+
+echo "Need U-Boot upgrade" ;
+echo "Program in 5 seconds" ;
+for n in 5 4 3 2 1 ; do
+ echo $n ;
+ sleep 1 ;
+done
+echo "erasing" ;
+sf erase 0 ${erase_size} ;
+
+# two steps to prevent bricking
+echo "programming" ;
+setexpr a1 ${a_uImage1} + 0x400
+setexpr o1 ${offset} + 0x400
+setexpr s1 ${filesize} - 0x400
+sf write ${a1} ${o1} ${s1} ;
+sf write ${a_uImage1} $offset 0x400 ;
+
+if itest.s x7D == "x${cpu}"; then
+ sf write ${a_qspi1} ${qspi_offset} 0x200
+fi
+
+echo "verifying" ;
+if sf read ${a_uImage2} $offset $filesize ; then
+else
+ echo "Error re-reading EEPROM" ;
+ exit
+fi
+if cmp.b ${a_uImage1} ${a_uImage2} $filesize ; then
+else
+ echo "Read verification error" ;
+ exit
+fi
+
+if itest.s x7D == "x${cpu}"; then
+ if sf read ${a_qspi2} ${qspi_offset} 0x200 ; then
+ else
+ echo "Error re-reading qspi" ;
+ exit
+ fi
+ if cmp.b ${a_qspi1} ${a_qspi2} 0x200 ; then
+ else
+ echo "qspi parameter block verification error" ;
+ exit
+ fi
+fi
+
+if itest.s "x" != "x${next}" ; then
+ if ${fs}load ${dtype} ${disk}:1 ${a_script} ${next} ; then
+ source ${a_script}
+ else
+ echo "${next} not found on ${dtype} ${disk}"
+ fi
fi
+
+while echo "---- U-Boot upgraded. reset" ; do
+ sleep 120
+done
diff --git a/board/boundary/nitrogen6x/800mhz_2x128mx16.cfg b/board/boundary/nitrogen6x/800mhz_2x128mx16.cfg
deleted file mode 100644
index cb04832c50f7adfb1cbc7a46992c86ee4d486762..0000000000000000000000000000000000000000
--- a/board/boundary/nitrogen6x/800mhz_2x128mx16.cfg
+++ /dev/null
@@ -1,41 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2013 Boundary Devices
- */
-
-DATA 4, MX6_MMDC_P0_MDPDC, 0x0002002D
-DATA 4, MX6_MMDC_P0_MDCFG0, 0x40435323
-DATA 4, MX6_MMDC_P0_MDCFG1, 0xB66E8D63
-DATA 4, MX6_MMDC_P0_MDCFG2, 0x01FF00DB
-DATA 4, MX6_MMDC_P0_MDRWD, 0x000026D2
-DATA 4, MX6_MMDC_P0_MDOR, 0x00431023
-DATA 4, MX6_MMDC_P0_MDOTC, 0x00333030
-DATA 4, MX6_MMDC_P0_MDPDC, 0x0002556D
-DATA 4, MX6_MMDC_P0_MDASP, 0x00000017
-DATA 4, MX6_MMDC_P0_MDCTL, 0x83190000
-DATA 4, MX6_MMDC_P0_MDSCR, 0x04008032
-DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033
-DATA 4, MX6_MMDC_P0_MDSCR, 0x00048031
-DATA 4, MX6_MMDC_P0_MDSCR, 0x13208030
-DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040
-DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003
-DATA 4, MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003
-DATA 4, MX6_MMDC_P0_MDREF, 0x00005800
-DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00022227
-DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00022227
-DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x42350231
-DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x42350231
-DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x021A0218
-DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x021A0218
-DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x4B4B4E49
-DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x4B4B4E49
-DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x3F3F3035
-DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x3F3F3035
-DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x0040003C
-DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x0032003E
-DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x0040003C
-DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x0032003E
-DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800
-DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800
-DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000
-DATA 4, MX6_MMDC_P0_MAPSR, 0x00011006
diff --git a/board/boundary/nitrogen6x/800mhz_2x256mx16.cfg b/board/boundary/nitrogen6x/800mhz_2x256mx16.cfg
deleted file mode 100644
index d85466f2fd143fe1545bb4f90492d84ce7636a1e..0000000000000000000000000000000000000000
--- a/board/boundary/nitrogen6x/800mhz_2x256mx16.cfg
+++ /dev/null
@@ -1,41 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2013 Boundary Devices
- */
-
-DATA 4, MX6_MMDC_P0_MDPDC, 0x0002002D
-DATA 4, MX6_MMDC_P0_MDCFG0, 0x696C5323
-DATA 4, MX6_MMDC_P0_MDCFG1, 0xB66E8D63
-DATA 4, MX6_MMDC_P0_MDCFG2, 0x01FF00DB
-DATA 4, MX6_MMDC_P0_MDRWD, 0x000026D2
-DATA 4, MX6_MMDC_P0_MDOR, 0x006C1023
-DATA 4, MX6_MMDC_P0_MDOTC, 0x00333030
-DATA 4, MX6_MMDC_P0_MDPDC, 0x0002556D
-DATA 4, MX6_MMDC_P0_MDASP, 0x00000027
-DATA 4, MX6_MMDC_P0_MDCTL, 0x84190000
-DATA 4, MX6_MMDC_P0_MDSCR, 0x04008032
-DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033
-DATA 4, MX6_MMDC_P0_MDSCR, 0x00048031
-DATA 4, MX6_MMDC_P0_MDSCR, 0x13208030
-DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040
-DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003
-DATA 4, MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003
-DATA 4, MX6_MMDC_P0_MDREF, 0x00007800
-DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00022227
-DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00022227
-DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x42350231
-DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x021A0218
-DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x42350231
-DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x021A0218
-DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x4B4B4E49
-DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x4B4B4E49
-DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x3F3F3035
-DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x3F3F3035
-DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x0040003C
-DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x0032003E
-DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x0040003C
-DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x0032003E
-DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800
-DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800
-DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000
-DATA 4, MX6_MMDC_P0_MAPSR, 0x00011006
diff --git a/board/boundary/nitrogen6x/800mhz_4x128mx16.cfg b/board/boundary/nitrogen6x/800mhz_4x128mx16.cfg
deleted file mode 100644
index 417af645005f16f219e7d84f55e94c6a6b12d505..0000000000000000000000000000000000000000
--- a/board/boundary/nitrogen6x/800mhz_4x128mx16.cfg
+++ /dev/null
@@ -1,41 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2013 Boundary Devices
- */
-
-DATA 4, MX6_MMDC_P0_MDPDC, 0x0002002D
-DATA 4, MX6_MMDC_P0_MDCFG0, 0x40435323
-DATA 4, MX6_MMDC_P0_MDCFG1, 0xB66E8D63
-DATA 4, MX6_MMDC_P0_MDCFG2, 0x01FF00DB
-DATA 4, MX6_MMDC_P0_MDRWD, 0x000026D2
-DATA 4, MX6_MMDC_P0_MDOR, 0x00431023
-DATA 4, MX6_MMDC_P0_MDOTC, 0x00333030
-DATA 4, MX6_MMDC_P0_MDPDC, 0x0002556D
-DATA 4, MX6_MMDC_P0_MDASP, 0x00000027
-DATA 4, MX6_MMDC_P0_MDCTL, 0x831A0000
-DATA 4, MX6_MMDC_P0_MDSCR, 0x04008032
-DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033
-DATA 4, MX6_MMDC_P0_MDSCR, 0x00048031
-DATA 4, MX6_MMDC_P0_MDSCR, 0x13208030
-DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040
-DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003
-DATA 4, MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003
-DATA 4, MX6_MMDC_P0_MDREF, 0x00005800
-DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00022227
-DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00022227
-DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x420F020F
-DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x01760175
-DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x41640171
-DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x015E0160
-DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x45464B4A
-DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x49484A46
-DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x40402E32
-DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x3A3A3231
-DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x003A003A
-DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x0030002F
-DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x002F0038
-DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x00270039
-DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800
-DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800
-DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000
-DATA 4, MX6_MMDC_P0_MAPSR, 0x00011006
diff --git a/board/boundary/nitrogen6x/800mhz_4x256mx16.cfg b/board/boundary/nitrogen6x/800mhz_4x256mx16.cfg
deleted file mode 100644
index 6f75ea27740dd7d40a5ffff296c4c3e1e9640053..0000000000000000000000000000000000000000
--- a/board/boundary/nitrogen6x/800mhz_4x256mx16.cfg
+++ /dev/null
@@ -1,41 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2013 Boundary Devices
- */
-
-DATA 4, MX6_MMDC_P0_MDPDC, 0x0002002D
-DATA 4, MX6_MMDC_P0_MDCFG0, 0x696C5323
-DATA 4, MX6_MMDC_P0_MDCFG1, 0xB66E8D63
-DATA 4, MX6_MMDC_P0_MDCFG2, 0x01FF00DB
-DATA 4, MX6_MMDC_P0_MDRWD, 0x000026D2
-DATA 4, MX6_MMDC_P0_MDOR, 0x006C1023
-DATA 4, MX6_MMDC_P0_MDOTC, 0x00333030
-DATA 4, MX6_MMDC_P0_MDPDC, 0x0002556D
-DATA 4, MX6_MMDC_P0_MDASP, 0x00000047
-DATA 4, MX6_MMDC_P0_MDCTL, 0x841A0000
-DATA 4, MX6_MMDC_P0_MDSCR, 0x04008032
-DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033
-DATA 4, MX6_MMDC_P0_MDSCR, 0x00048031
-DATA 4, MX6_MMDC_P0_MDSCR, 0x13208030
-DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040
-DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003
-DATA 4, MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003
-DATA 4, MX6_MMDC_P0_MDREF, 0x00007800
-DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00022227
-DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00022227
-DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x42350231
-DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x021A0218
-DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x42350231
-DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x021A0218
-DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x4B4B4E49
-DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x4B4B4E49
-DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x3F3F3035
-DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x3F3F3035
-DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x0040003C
-DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x0032003E
-DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x0040003C
-DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x0032003E
-DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800
-DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800
-DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000
-DATA 4, MX6_MMDC_P0_MAPSR, 0x00011006
diff --git a/board/boundary/nitrogen6x/Kconfig b/board/boundary/nitrogen6x/Kconfig
index f4db56d49601c933ddec48605468f67a35231cb8..e2fd37f221861c69806ca441fdd4f207c32d2887 100644
--- a/board/boundary/nitrogen6x/Kconfig
+++ b/board/boundary/nitrogen6x/Kconfig
@@ -9,4 +9,10 @@ config SYS_VENDOR
config SYS_CONFIG_NAME
default "nitrogen6x"
+config ENV_WLMAC
+ bool
+ default y
+
+source "board/boundary/common/Kconfig"
+
endif
diff --git a/board/boundary/nitrogen6x/Makefile b/board/boundary/nitrogen6x/Makefile
index c8433bd74888c46fd6046fc9096b219f079f7f73..3b310c6265e72b4354f8dd696e7557cf45c10eb2 100644
--- a/board/boundary/nitrogen6x/Makefile
+++ b/board/boundary/nitrogen6x/Makefile
@@ -5,3 +5,4 @@
# Copyright (C) 2013, Boundary Devices <info@boundarydevices.com>
obj-y := nitrogen6x.o
+obj-$(CONFIG_MXC_SPI_DISPLAY) += spi_display.o
\ No newline at end of file
diff --git a/board/boundary/nitrogen6x/clocks.cfg b/board/boundary/nitrogen6x/clocks.cfg
deleted file mode 100644
index d78e0fdbbd25d50fcb6768a8614d9d3155f8a033..0000000000000000000000000000000000000000
--- a/board/boundary/nitrogen6x/clocks.cfg
+++ /dev/null
@@ -1,40 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2013 Boundary Devices
- *
- * Device Configuration Data (DCD)
- *
- * Each entry must have the format:
- * Addr-type Address Value
- *
- * where:
- * Addr-type register length (1,2 or 4 bytes)
- * Address absolute address of the register
- * value value to be stored in the register
- */
-
-/* set the default clock gate to save power */
-DATA 4, CCM_CCGR0, 0x00C03F3F
-DATA 4, CCM_CCGR1, 0x0030FC03
-DATA 4, CCM_CCGR2, 0x0FFFC000
-DATA 4, CCM_CCGR3, 0x3FF00000
-DATA 4, CCM_CCGR4, 0x00FFF300
-DATA 4, CCM_CCGR5, 0x0F0000C3
-DATA 4, CCM_CCGR6, 0x000003FF
-
-/* enable AXI cache for VDOA/VPU/IPU */
-DATA 4, MX6_IOMUXC_GPR4, 0xF00000CF
-/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
-DATA 4, MX6_IOMUXC_GPR6, 0x007F007F
-DATA 4, MX6_IOMUXC_GPR7, 0x007F007F
-
-/*
- * Setup CCM_CCOSR register as follows:
- *
- * cko1_en = 1 --> CKO1 enabled
- * cko1_div = 111 --> divide by 8
- * cko1_sel = 1011 --> ahb_clk_root
- *
- * This sets CKO1 at ahb_clk_root/8 = 132/8 = 16.5 MHz
- */
-DATA 4, CCM_CCOSR, 0x000000fb
diff --git a/board/boundary/nitrogen6x/ddr-setup.cfg b/board/boundary/nitrogen6x/ddr-setup.cfg
deleted file mode 100644
index 99b449c2942405b834b9da1a5168ecba49ef940e..0000000000000000000000000000000000000000
--- a/board/boundary/nitrogen6x/ddr-setup.cfg
+++ /dev/null
@@ -1,95 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2013 Boundary Devices
- *
- * Device Configuration Data (DCD)
- *
- * Each entry must have the format:
- * Addr-type Address Value
- *
- * where:
- * Addr-type register length (1,2 or 4 bytes)
- * Address absolute address of the register
- * value value to be stored in the register
- */
-
-/*
- * DDR3 settings
- * MX6Q ddr is limited to 1066 Mhz currently 1056 MHz(528 MHz clock),
- * memory bus width: 64 bits x16/x32/x64
- * MX6DL ddr is limited to 800 MHz(400 MHz clock)
- * memory bus width: 64 bits x16/x32/x64
- * MX6SOLO ddr is limited to 800 MHz(400 MHz clock)
- * memory bus width: 32 bits x16/x32
- */
-DATA 4, MX6_IOM_DRAM_SDQS0, 0x00000030
-DATA 4, MX6_IOM_DRAM_SDQS1, 0x00000030
-DATA 4, MX6_IOM_DRAM_SDQS2, 0x00000030
-DATA 4, MX6_IOM_DRAM_SDQS3, 0x00000030
-DATA 4, MX6_IOM_DRAM_SDQS4, 0x00000030
-DATA 4, MX6_IOM_DRAM_SDQS5, 0x00000030
-DATA 4, MX6_IOM_DRAM_SDQS6, 0x00000030
-DATA 4, MX6_IOM_DRAM_SDQS7, 0x00000030
-
-DATA 4, MX6_IOM_GRP_B0DS, 0x00000030
-DATA 4, MX6_IOM_GRP_B1DS, 0x00000030
-DATA 4, MX6_IOM_GRP_B2DS, 0x00000030
-DATA 4, MX6_IOM_GRP_B3DS, 0x00000030
-DATA 4, MX6_IOM_GRP_B4DS, 0x00000030
-DATA 4, MX6_IOM_GRP_B5DS, 0x00000030
-DATA 4, MX6_IOM_GRP_B6DS, 0x00000030
-DATA 4, MX6_IOM_GRP_B7DS, 0x00000030
-DATA 4, MX6_IOM_GRP_ADDDS, 0x00000030
-/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
-DATA 4, MX6_IOM_GRP_CTLDS, 0x00000030
-
-DATA 4, MX6_IOM_DRAM_DQM0, 0x00020030
-DATA 4, MX6_IOM_DRAM_DQM1, 0x00020030
-DATA 4, MX6_IOM_DRAM_DQM2, 0x00020030
-DATA 4, MX6_IOM_DRAM_DQM3, 0x00020030
-DATA 4, MX6_IOM_DRAM_DQM4, 0x00020030
-DATA 4, MX6_IOM_DRAM_DQM5, 0x00020030
-DATA 4, MX6_IOM_DRAM_DQM6, 0x00020030
-DATA 4, MX6_IOM_DRAM_DQM7, 0x00020030
-
-DATA 4, MX6_IOM_DRAM_CAS, 0x00020030
-DATA 4, MX6_IOM_DRAM_RAS, 0x00020030
-DATA 4, MX6_IOM_DRAM_SDCLK_0, 0x00020030
-DATA 4, MX6_IOM_DRAM_SDCLK_1, 0x00020030
-
-DATA 4, MX6_IOM_DRAM_RESET, 0x00020030
-DATA 4, MX6_IOM_DRAM_SDCKE0, 0x00003000
-DATA 4, MX6_IOM_DRAM_SDCKE1, 0x00003000
-
-DATA 4, MX6_IOM_DRAM_SDODT0, 0x00003030
-DATA 4, MX6_IOM_DRAM_SDODT1, 0x00003030
-
-/* (differential input) */
-DATA 4, MX6_IOM_DDRMODE_CTL, 0x00020000
-/* (differential input) */
-DATA 4, MX6_IOM_GRP_DDRMODE, 0x00020000
-/* disable ddr pullups */
-DATA 4, MX6_IOM_GRP_DDRPKE, 0x00000000
-DATA 4, MX6_IOM_DRAM_SDBA2, 0x00000000
-/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
-DATA 4, MX6_IOM_GRP_DDR_TYPE, 0x000C0000
-
-/* Read data DQ Byte0-3 delay */
-DATA 4, MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333
-DATA 4, MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333
-DATA 4, MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333
-DATA 4, MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333
-DATA 4, MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333
-DATA 4, MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333
-DATA 4, MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333
-DATA 4, MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333
-
-/*
- * MDMISC mirroring interleaved (row/bank/col)
- */
-DATA 4, MX6_MMDC_P0_MDMISC, 0x00081740
-
-/*
- * MDSCR con_req
- */
-DATA 4, MX6_MMDC_P0_MDSCR, 0x00008000
diff --git a/board/boundary/nitrogen6x/nitrogen6dl.cfg b/board/boundary/nitrogen6x/nitrogen6dl.cfg
index b1e3c0fe45c39951d2083e81b4bffe8ec8256abf..3e998b855e169bfe7699c7675700cdc5fdf71f70 100644
--- a/board/boundary/nitrogen6x/nitrogen6dl.cfg
+++ b/board/boundary/nitrogen6x/nitrogen6dl.cfg
@@ -26,6 +26,25 @@ CSF CONFIG_CSF_SIZE
#include "asm/arch/iomux.h"
#include "asm/arch/crm_regs.h"
-#include "ddr-setup.cfg"
-#include "800mhz_4x128mx16.cfg"
-#include "clocks.cfg"
+/* unknow sample size */
+#define MX6_MMDC_P0_MPDGCTRL0_VAL 0x420F020F
+#define MX6_MMDC_P0_MPDGCTRL1_VAL 0x01760175
+#define MX6_MMDC_P1_MPDGCTRL0_VAL 0x41640171
+#define MX6_MMDC_P1_MPDGCTRL1_VAL 0x015E0160
+#define MX6_MMDC_P0_MPRDDLCTL_VAL 0x45464B4A
+#define MX6_MMDC_P1_MPRDDLCTL_VAL 0x49484A46
+#define MX6_MMDC_P0_MPWRDLCTL_VAL 0x40402E32
+#define MX6_MMDC_P1_MPWRDLCTL_VAL 0x3A3A3231
+#define MX6_MMDC_P0_MPWLDECTRL0_VAL 0x003A003A
+#define MX6_MMDC_P0_MPWLDECTRL1_VAL 0x0030002F
+#define MX6_MMDC_P1_MPWLDECTRL0_VAL 0x002F0038
+#define MX6_MMDC_P1_MPWLDECTRL1_VAL 0x00270039
+#define WALAT 1
+
+#include "../common/mx6/ddr-setup.cfg"
+#define RANK 0
+#define BUS_WIDTH 64
+/* H5TC2G63FFR-PBA */
+/* MT41K128M16JT-125 IT:K */
+#include "../common/mx6/800mhz_128mx16.cfg"
+#include "../common/mx6/clocks.cfg"
diff --git a/board/boundary/nitrogen6x/nitrogen6dl2g.cfg b/board/boundary/nitrogen6x/nitrogen6dl2g.cfg
index 3e7d605bf5ebc6072e5fcbc76164262acfc3d6ad..6e13815050edfc44a9acc4a2fbaec3db8e6ecabb 100644
--- a/board/boundary/nitrogen6x/nitrogen6dl2g.cfg
+++ b/board/boundary/nitrogen6x/nitrogen6dl2g.cfg
@@ -26,6 +26,24 @@ CSF CONFIG_CSF_SIZE
#include "asm/arch/iomux.h"
#include "asm/arch/crm_regs.h"
-#include "ddr-setup.cfg"
-#include "800mhz_4x256mx16.cfg"
-#include "clocks.cfg"
+/* NC YET */
+#define MX6_MMDC_P0_MPDGCTRL0_VAL 0x42350231
+#define MX6_MMDC_P0_MPDGCTRL1_VAL 0x021a0218
+#define MX6_MMDC_P1_MPDGCTRL0_VAL 0x42350231
+#define MX6_MMDC_P1_MPDGCTRL1_VAL 0x021a0218
+#define MX6_MMDC_P0_MPRDDLCTL_VAL 0x4b4b4e49
+#define MX6_MMDC_P1_MPRDDLCTL_VAL 0x4b4b4e49
+#define MX6_MMDC_P0_MPWRDLCTL_VAL 0x3f3f3035
+#define MX6_MMDC_P1_MPWRDLCTL_VAL 0x3f3f3035
+#define MX6_MMDC_P0_MPWLDECTRL0_VAL 0x0040003c
+#define MX6_MMDC_P0_MPWLDECTRL1_VAL 0x0032003e
+#define MX6_MMDC_P1_MPWLDECTRL0_VAL 0x0040003c
+#define MX6_MMDC_P1_MPWLDECTRL1_VAL 0x0032003e
+#define WALAT 1
+
+#include "../common/mx6/ddr-setup.cfg"
+#define RANK 0
+#define BUS_WIDTH 64
+/* D2516EC4BXGGB-U */
+#include "../common/mx6/800mhz_256mx16.cfg"
+#include "../common/mx6/clocks.cfg"
diff --git a/board/boundary/nitrogen6x/nitrogen6q.cfg b/board/boundary/nitrogen6x/nitrogen6q.cfg
index 26bb6451a28963b078121f43c6fd81ec1e28ec38..4cf9fc318013aa92cbf86e7f9d691e885c0c13f8 100644
--- a/board/boundary/nitrogen6x/nitrogen6q.cfg
+++ b/board/boundary/nitrogen6x/nitrogen6q.cfg
@@ -26,6 +26,25 @@ CSF CONFIG_CSF_SIZE
#include "asm/arch/iomux.h"
#include "asm/arch/crm_regs.h"
-#include "ddr-setup.cfg"
-#include "1066mhz_4x128mx16.cfg"
-#include "clocks.cfg"
+/* ? board sample */
+#define MX6_MMDC_P0_MPDGCTRL0_VAL 0x42720306
+#define MX6_MMDC_P0_MPDGCTRL1_VAL 0x026F0266
+#define MX6_MMDC_P1_MPDGCTRL0_VAL 0x4273030A
+#define MX6_MMDC_P1_MPDGCTRL1_VAL 0x02740240
+#define MX6_MMDC_P0_MPRDDLCTL_VAL 0x45393B3E
+#define MX6_MMDC_P1_MPRDDLCTL_VAL 0x403A3747
+#define MX6_MMDC_P0_MPWRDLCTL_VAL 0x40434541
+#define MX6_MMDC_P1_MPWRDLCTL_VAL 0x473E4A3B
+#define MX6_MMDC_P0_MPWLDECTRL0_VAL 0x0011000E
+#define MX6_MMDC_P0_MPWLDECTRL1_VAL 0x000E001B
+#define MX6_MMDC_P1_MPWLDECTRL0_VAL 0x00190015
+#define MX6_MMDC_P1_MPWLDECTRL1_VAL 0x00070018
+#define WALAT 0
+
+#include "../common/mx6/ddr-setup.cfg"
+#define RANK 0
+#define BUS_WIDTH 64
+/* H5TC2G63FFR-PBA */
+/* MT41K128M16JT-125 IT:K */
+#include "../common/mx6/1066mhz_128mx16.cfg"
+#include "../common/mx6/clocks.cfg"
diff --git a/board/boundary/nitrogen6x/nitrogen6q2g.cfg b/board/boundary/nitrogen6x/nitrogen6q2g.cfg
index 5ff3eedc195bc5cd18e80c88cd6658e8e6451f1b..98003aa60bfc7a880419a6535f3ac8f3770f040d 100644
--- a/board/boundary/nitrogen6x/nitrogen6q2g.cfg
+++ b/board/boundary/nitrogen6x/nitrogen6q2g.cfg
@@ -26,6 +26,24 @@ CSF CONFIG_CSF_SIZE
#include "asm/arch/iomux.h"
#include "asm/arch/crm_regs.h"
-#include "ddr-setup.cfg"
-#include "1066mhz_4x256mx16.cfg"
-#include "clocks.cfg"
+#define MX6_MMDC_P0_MPDGCTRL0_VAL 0x42740304
+#define MX6_MMDC_P0_MPDGCTRL1_VAL 0x026e0265
+#define MX6_MMDC_P1_MPDGCTRL0_VAL 0x02750306
+#define MX6_MMDC_P1_MPDGCTRL1_VAL 0x02720244
+#define MX6_MMDC_P0_MPRDDLCTL_VAL 0x463d4041
+#define MX6_MMDC_P1_MPRDDLCTL_VAL 0x42413c47
+#define MX6_MMDC_P0_MPWRDLCTL_VAL 0x37414441
+#define MX6_MMDC_P1_MPWRDLCTL_VAL 0x4633473b
+#define MX6_MMDC_P0_MPWLDECTRL0_VAL 0x0025001f
+#define MX6_MMDC_P0_MPWLDECTRL1_VAL 0x00290027
+#define MX6_MMDC_P1_MPWLDECTRL0_VAL 0x001f002b
+#define MX6_MMDC_P1_MPWLDECTRL1_VAL 0x000f0029
+#define WALAT 1
+
+#include "../common/mx6/ddr-setup.cfg"
+#define RANK 0
+#define BUS_WIDTH 64
+/* D2516EC4BXGGB-U */
+/* D2516EC4BXGGBI-U */
+#include "../common/mx6/1066mhz_256mx16.cfg"
+#include "../common/mx6/clocks.cfg"
diff --git a/board/boundary/nitrogen6x/nitrogen6s.cfg b/board/boundary/nitrogen6x/nitrogen6s.cfg
index 5482656e8f5f18750c301adff536759fc9729a48..c4716b272960983f099e577c6a2b60559bd9e3e7 100644
--- a/board/boundary/nitrogen6x/nitrogen6s.cfg
+++ b/board/boundary/nitrogen6x/nitrogen6s.cfg
@@ -26,6 +26,19 @@ CSF CONFIG_CSF_SIZE
#include "asm/arch/iomux.h"
#include "asm/arch/crm_regs.h"
-#include "ddr-setup.cfg"
-#include "800mhz_2x128mx16.cfg"
-#include "clocks.cfg"
+/* NC YET */
+#define MX6_MMDC_P0_MPDGCTRL0_VAL 0x42350231
+#define MX6_MMDC_P0_MPDGCTRL1_VAL 0x021A0218
+#define MX6_MMDC_P0_MPRDDLCTL_VAL 0x4B4B4E49
+#define MX6_MMDC_P0_MPWRDLCTL_VAL 0x3F3F3035
+#define MX6_MMDC_P0_MPWLDECTRL0_VAL 0x0040003C
+#define MX6_MMDC_P0_MPWLDECTRL1_VAL 0x0032003E
+#define WALAT 1
+
+#include "../common/mx6/ddr-setup.cfg"
+#define RANK 0
+#define BUS_WIDTH 32
+/* H5TC2G63FFR-PBA */
+/* MT41K128M16JT-125 IT:K */
+#include "../common/mx6/800mhz_128mx16.cfg"
+#include "../common/mx6/clocks.cfg"
diff --git a/board/boundary/nitrogen6x/nitrogen6s1g.cfg b/board/boundary/nitrogen6x/nitrogen6s1g.cfg
index dd30ca943956fa2fe0cb8ee188323b7b8ebbfc06..3e8f17325edda4559be7cbf4aa31b28dcdcb5490 100644
--- a/board/boundary/nitrogen6x/nitrogen6s1g.cfg
+++ b/board/boundary/nitrogen6x/nitrogen6s1g.cfg
@@ -26,6 +26,18 @@ CSF CONFIG_CSF_SIZE
#include "asm/arch/iomux.h"
#include "asm/arch/crm_regs.h"
-#include "ddr-setup.cfg"
-#include "800mhz_2x256mx16.cfg"
-#include "clocks.cfg"
+/* NC YET */
+#define MX6_MMDC_P0_MPDGCTRL0_VAL 0x42350231
+#define MX6_MMDC_P0_MPDGCTRL1_VAL 0x021A0218
+#define MX6_MMDC_P0_MPRDDLCTL_VAL 0x4B4B4E49
+#define MX6_MMDC_P0_MPWRDLCTL_VAL 0x3F3F3035
+#define MX6_MMDC_P0_MPWLDECTRL0_VAL 0x0040003C
+#define MX6_MMDC_P0_MPWLDECTRL1_VAL 0x0032003E
+#define WALAT 1
+
+#include "../common/mx6/ddr-setup.cfg"
+#define RANK 0
+#define BUS_WIDTH 32
+/* D2516EC4BXGGB-U */
+#include "../common/mx6/800mhz_256mx16.cfg"
+#include "../common/mx6/clocks.cfg"
diff --git a/board/boundary/nitrogen6x/nitrogen6x.c b/board/boundary/nitrogen6x/nitrogen6x.c
index 84d7cee740d6f6d7505b4bc325aa4210084ebd41..8d94db777fb530025c71586a8bb81a315ed0a3e9 100644
--- a/board/boundary/nitrogen6x/nitrogen6x.c
+++ b/board/boundary/nitrogen6x/nitrogen6x.c
@@ -14,6 +14,7 @@
#include <asm/arch/mx6-pins.h>
#include <linux/errno.h>
#include <asm/gpio.h>
+#include <asm/mach-imx/fbpanel.h>
#include <asm/mach-imx/iomux-v3.h>
#include <asm/mach-imx/mxc_i2c.h>
#include <asm/mach-imx/sata.h>
@@ -22,253 +23,275 @@
#include <asm/mach-imx/video.h>
#include <mmc.h>
#include <fsl_esdhc.h>
-#include <micrel.h>
-#include <miiphy.h>
-#include <netdev.h>
+#include <splash.h>
#include <asm/arch/crm_regs.h>
#include <asm/arch/mxc_hdmi.h>
#include <i2c.h>
#include <input.h>
-#include <netdev.h>
#include <usb/ehci-ci.h>
+#include "spi_display.h"
+#include "../common/bd_common.h"
+#include "../common/padctrl.h"
DECLARE_GLOBAL_DATA_PTR;
-#define GP_USB_OTG_PWR IMX_GPIO_NR(3, 22)
-#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
- PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
- PAD_CTL_SRE_FAST | PAD_CTL_HYS)
-
-#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
- PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
- PAD_CTL_SRE_FAST | PAD_CTL_HYS)
-
-#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
- PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
-
-#define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
- PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
-
-#define BUTTON_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
+#define BUTTON_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
PAD_CTL_ODE | PAD_CTL_SRE_FAST)
-#define WEAK_PULLUP (PAD_CTL_PUS_100K_UP | \
- PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
- PAD_CTL_SRE_SLOW)
-
-#define WEAK_PULLDOWN (PAD_CTL_PUS_100K_DOWN | \
- PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
- PAD_CTL_HYS | PAD_CTL_SRE_SLOW)
-
-#define OUTPUT_40OHM (PAD_CTL_SPEED_MED|PAD_CTL_DSE_40ohm)
-
-int dram_init(void)
-{
- gd->ram_size = ((ulong)CONFIG_DDR_MB * 1024 * 1024);
-
- return 0;
-}
-
-static iomux_v3_cfg_t const uart1_pads[] = {
- MX6_PAD_SD3_DAT6__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
- MX6_PAD_SD3_DAT7__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
-};
-
-static iomux_v3_cfg_t const uart2_pads[] = {
- MX6_PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
- MX6_PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
-};
-
-#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
+#define RGB_PAD_CTRL PAD_CTL_DSE_120ohm
-/* I2C1, SGTL5000 */
-static struct i2c_pads_info i2c_pad_info0 = {
- .scl = {
- .i2c_mode = MX6_PAD_EIM_D21__I2C1_SCL | PC,
- .gpio_mode = MX6_PAD_EIM_D21__GPIO3_IO21 | PC,
- .gp = IMX_GPIO_NR(3, 21)
- },
- .sda = {
- .i2c_mode = MX6_PAD_EIM_D28__I2C1_SDA | PC,
- .gpio_mode = MX6_PAD_EIM_D28__GPIO3_IO28 | PC,
- .gp = IMX_GPIO_NR(3, 28)
- }
-};
-
-/* I2C2 Camera, MIPI */
-static struct i2c_pads_info i2c_pad_info1 = {
- .scl = {
- .i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | PC,
- .gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12 | PC,
- .gp = IMX_GPIO_NR(4, 12)
- },
- .sda = {
- .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | PC,
- .gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | PC,
- .gp = IMX_GPIO_NR(4, 13)
- }
-};
+#define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
+ PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
-/* I2C3, J15 - RGB connector */
-static struct i2c_pads_info i2c_pad_info2 = {
- .scl = {
- .i2c_mode = MX6_PAD_GPIO_5__I2C3_SCL | PC,
- .gpio_mode = MX6_PAD_GPIO_5__GPIO1_IO05 | PC,
- .gp = IMX_GPIO_NR(1, 5)
- },
- .sda = {
- .i2c_mode = MX6_PAD_GPIO_16__I2C3_SDA | PC,
- .gpio_mode = MX6_PAD_GPIO_16__GPIO7_IO11 | PC,
- .gp = IMX_GPIO_NR(7, 11)
- }
-};
-
-static iomux_v3_cfg_t const usdhc2_pads[] = {
- MX6_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-};
-
-static iomux_v3_cfg_t const usdhc3_pads[] = {
- MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_DAT5__GPIO7_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
-};
-
-static iomux_v3_cfg_t const usdhc4_pads[] = {
- MX6_PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_NANDF_D6__GPIO2_IO06 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
-};
+#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
+ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
+ PAD_CTL_HYS | PAD_CTL_SRE_FAST)
-static iomux_v3_cfg_t const enet_pads1[] = {
- MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
- /* pin 35 - 1 (PHY_AD2) on reset */
- MX6_PAD_RGMII_RXC__GPIO6_IO30 | MUX_PAD_CTRL(NO_PAD_CTRL),
- /* pin 32 - 1 - (MODE0) all */
- MX6_PAD_RGMII_RD0__GPIO6_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL),
- /* pin 31 - 1 - (MODE1) all */
- MX6_PAD_RGMII_RD1__GPIO6_IO27 | MUX_PAD_CTRL(NO_PAD_CTRL),
- /* pin 28 - 1 - (MODE2) all */
- MX6_PAD_RGMII_RD2__GPIO6_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL),
- /* pin 27 - 1 - (MODE3) all */
- MX6_PAD_RGMII_RD3__GPIO6_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL),
- /* pin 33 - 1 - (CLK125_EN) 125Mhz clockout enabled */
- MX6_PAD_RGMII_RX_CTL__GPIO6_IO24 | MUX_PAD_CTRL(NO_PAD_CTRL),
+#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
+ PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
+ PAD_CTL_HYS | PAD_CTL_SRE_FAST)
+
+static const iomux_v3_cfg_t init_pads[] = {
+ /* bt_rfkill */
+#define GP_BT_RFKILL_RESET IMX_GPIO_NR(6, 16)
+ IOMUX_PAD_CTRL(NANDF_CS3__GPIO6_IO16, WEAK_PULLDN),
+
+ /* ECSPI1 */
+ IOMUX_PAD_CTRL(EIM_D17__ECSPI1_MISO, SPI_PAD_CTRL),
+ IOMUX_PAD_CTRL(EIM_D18__ECSPI1_MOSI, SPI_PAD_CTRL),
+ IOMUX_PAD_CTRL(EIM_D16__ECSPI1_SCLK, SPI_PAD_CTRL),
+#define GP_ECSPI1_NOR_CS IMX_GPIO_NR(3, 19)
+ IOMUX_PAD_CTRL(EIM_D19__GPIO3_IO19, WEAK_PULLUP),
+
+ /* ECSPI2 */
+ IOMUX_PAD_CTRL(CSI0_DAT10__ECSPI2_MISO, SPI_PAD_CTRL),
+ IOMUX_PAD_CTRL(CSI0_DAT9__ECSPI2_MOSI, SPI_PAD_CTRL),
+ IOMUX_PAD_CTRL(CSI0_DAT8__ECSPI2_SCLK, SPI_PAD_CTRL),
+#define GP_ECSPI2_CS IMX_GPIO_NR(5, 29)
+ IOMUX_PAD_CTRL(CSI0_DAT11__GPIO5_IO29, WEAK_PULLUP), /* for spi displays */
+#define GP_SPI_DISPLAY_RESET IMX_GPIO_NR(4, 20)
+ IOMUX_PAD_CTRL(DI0_PIN4__GPIO4_IO20, WEAK_PULLUP),
+
+ /* ENET pads that don't change for PHY reset */
+ IOMUX_PAD_CTRL(ENET_MDIO__ENET_MDIO, PAD_CTRL_ENET_MDIO),
+ IOMUX_PAD_CTRL(ENET_MDC__ENET_MDC, PAD_CTRL_ENET_MDC),
+ IOMUX_PAD_CTRL(RGMII_TXC__RGMII_TXC, PAD_CTRL_ENET_TX),
+ IOMUX_PAD_CTRL(RGMII_TD0__RGMII_TD0, PAD_CTRL_ENET_TX),
+ IOMUX_PAD_CTRL(RGMII_TD1__RGMII_TD1, PAD_CTRL_ENET_TX),
+ IOMUX_PAD_CTRL(RGMII_TD2__RGMII_TD2, PAD_CTRL_ENET_TX),
+ IOMUX_PAD_CTRL(RGMII_TD3__RGMII_TD3, PAD_CTRL_ENET_TX),
+ IOMUX_PAD_CTRL(RGMII_TX_CTL__RGMII_TX_CTL, PAD_CTRL_ENET_TX),
+ IOMUX_PAD_CTRL(ENET_REF_CLK__ENET_TX_CLK, PAD_CTRL_ENET_TX),
/* pin 42 PHY nRST */
- MX6_PAD_EIM_D23__GPIO3_IO23 | MUX_PAD_CTRL(NO_PAD_CTRL),
- MX6_PAD_ENET_RXD0__GPIO1_IO27 | MUX_PAD_CTRL(NO_PAD_CTRL),
-};
+ /* Sabrelite has different reset pin*/
+#define GP_RGMII2_PHY_RESET IMX_GPIO_NR(3, 23)
+ IOMUX_PAD_CTRL(EIM_D23__GPIO3_IO23, WEAK_PULLUP),
+#define GP_RGMII_PHY_RESET IMX_GPIO_NR(1, 27)
+ IOMUX_PAD_CTRL(ENET_RXD0__GPIO1_IO27, WEAK_PULLUP),
+#define GPIRQ_ENET_PHY IMX_GPIO_NR(1, 28)
+ IOMUX_PAD_CTRL(ENET_TX_EN__GPIO1_IO28, WEAK_PULLUP),
+
+ /* gpio_Keys - Button assignments for J14 */
+#define GP_GPIOKEY_BACK IMX_GPIO_NR(2, 2)
+ IOMUX_PAD_CTRL(NANDF_D2__GPIO2_IO02, BUTTON_PAD_CTRL),
+#define GP_GPIOKEY_HOME IMX_GPIO_NR(2, 4)
+ IOMUX_PAD_CTRL(NANDF_D4__GPIO2_IO04, BUTTON_PAD_CTRL),
+#define GP_GPIOKEY_MENU IMX_GPIO_NR(2, 1)
+ IOMUX_PAD_CTRL(NANDF_D1__GPIO2_IO01, BUTTON_PAD_CTRL),
+ /* Labeled Search (mapped to Power under Android) */
+#define GP_GPIOKEY_POWER IMX_GPIO_NR(2, 3)
+ IOMUX_PAD_CTRL(NANDF_D3__GPIO2_IO03, BUTTON_PAD_CTRL),
+#define GP_GPIOKEY_VOL_DOWN IMX_GPIO_NR(4, 5)
+ IOMUX_PAD_CTRL(GPIO_19__GPIO4_IO05, BUTTON_PAD_CTRL),
+#define GP_GPIOKEY_VOL_UP IMX_GPIO_NR(7, 13)
+ IOMUX_PAD_CTRL(GPIO_18__GPIO7_IO13, BUTTON_PAD_CTRL),
+
+ /* i2c1_isl1208 */
+#define GPIRQ_RTC_ISL1208 IMX_GPIO_NR(6, 7)
+ IOMUX_PAD_CTRL(NANDF_CLE__GPIO6_IO07, WEAK_PULLUP),
+
+ /* i2c1_SGTL5000 sys_mclk */
+ IOMUX_PAD_CTRL(GPIO_0__CCM_CLKO1, OUTPUT_40OHM),
+ /* Needed if inappropriately used with SOM2 carrier board */
+#define GP_SGTL5000_HP_MUTE IMX_GPIO_NR(3, 29) /* Low is muted */
+ IOMUX_PAD_CTRL(EIM_D29__GPIO3_IO29, WEAK_PULLUP),
+
+ /* i2c2 ov5640 mipi Camera controls */
+#define GP_OV5640_MIPI_POWER_DOWN IMX_GPIO_NR(6, 9)
+ IOMUX_PAD_CTRL(NANDF_WP_B__GPIO6_IO09, WEAK_PULLUP),
+
+ /* i2c2 TC358743 interrupt */
+#define GPIRQ_TC3587 IMX_GPIO_NR(2, 5)
+ IOMUX_PAD_CTRL(NANDF_D5__GPIO2_IO05, WEAK_PULLDN),
+
+ /* i2c2 ov5642 Camera controls, J5 */
+ IOMUX_PAD_CTRL(GPIO_3__CCM_CLKO2, OUTPUT_40OHM), /* mclk */
+#define GP_OV5642_POWER_DOWN IMX_GPIO_NR(1, 6)
+ IOMUX_PAD_CTRL(GPIO_6__GPIO1_IO06, WEAK_PULLUP),
+#define GP_OV5642_RESET IMX_GPIO_NR(1, 8)
+ IOMUX_PAD_CTRL(GPIO_8__GPIO1_IO08, WEAK_PULLDN),
+
+ /* PWM1 - Backlight on RGB connector: J15 */
+#define GP_BACKLIGHT_RGB IMX_GPIO_NR(1, 21)
+ IOMUX_PAD_CTRL(SD1_DAT3__GPIO1_IO21, WEAK_PULLDN),
+
+ /* PWM4 - Backlight on LVDS connector: J6 */
+#define GP_BACKLIGHT_LVDS IMX_GPIO_NR(1, 18)
+ IOMUX_PAD_CTRL(SD1_CMD__GPIO1_IO18, WEAK_PULLDN),
+
+ /* reg_usbotg_vbus */
+#define GP_REG_USBOTG IMX_GPIO_NR(3, 22)
+ IOMUX_PAD_CTRL(EIM_D22__GPIO3_IO22, WEAK_PULLDN),
+
+ /* reg_wlan_en */
+#define GP_REG_WLAN_EN IMX_GPIO_NR(6, 15)
+ IOMUX_PAD_CTRL(NANDF_CS2__GPIO6_IO15, WEAK_PULLDN),
+
+ /* UART1 */
+ IOMUX_PAD_CTRL(SD3_DAT6__UART1_RX_DATA, UART_PAD_CTRL),
+ IOMUX_PAD_CTRL(SD3_DAT7__UART1_TX_DATA, UART_PAD_CTRL),
+
+ /* UART2 */
+#ifndef CONFIG_SILENT_UART
+ IOMUX_PAD_CTRL(EIM_D26__UART2_TX_DATA, UART_PAD_CTRL),
+ IOMUX_PAD_CTRL(EIM_D27__UART2_RX_DATA, UART_PAD_CTRL),
+#else
+ IOMUX_PAD_CTRL(EIM_D26__GPIO3_IO26, UART_PAD_CTRL),
+ IOMUX_PAD_CTRL(EIM_D27__GPIO3_IO27, UART_PAD_CTRL),
+#endif
-static iomux_v3_cfg_t const enet_pads2[] = {
- MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ /* USBH1 */
+ IOMUX_PAD_CTRL(EIM_D30__USB_H1_OC, WEAK_PULLUP),
+#define GP_USB_HUB_RESET IMX_GPIO_NR(7, 12)
+ IOMUX_PAD_CTRL(GPIO_17__GPIO7_IO12, WEAK_PULLDN),
+
+ /* USBOTG */
+ IOMUX_PAD_CTRL(GPIO_1__USB_OTG_ID, WEAK_PULLUP),
+ IOMUX_PAD_CTRL(KEY_COL4__USB_OTG_OC, WEAK_PULLUP),
+
+ /* USDHC2 - TiWi wl1271 */
+ IOMUX_PAD_CTRL(SD2_CLK__SD2_CLK, USDHC_PAD_CTRL),
+ IOMUX_PAD_CTRL(SD2_CMD__SD2_CMD, USDHC_PAD_CTRL),
+ IOMUX_PAD_CTRL(SD2_DAT0__SD2_DATA0, USDHC_PAD_CTRL),
+ IOMUX_PAD_CTRL(SD2_DAT1__SD2_DATA1, USDHC_PAD_CTRL),
+ IOMUX_PAD_CTRL(SD2_DAT2__SD2_DATA2, USDHC_PAD_CTRL),
+ IOMUX_PAD_CTRL(SD2_DAT3__SD2_DATA3, USDHC_PAD_CTRL),
+
+ /* USDHC3 - sdcard */
+ IOMUX_PAD_CTRL(SD3_CLK__SD3_CLK, USDHC_PAD_CTRL),
+ IOMUX_PAD_CTRL(SD3_CMD__SD3_CMD, USDHC_PAD_CTRL),
+ IOMUX_PAD_CTRL(SD3_DAT0__SD3_DATA0, USDHC_PAD_CTRL),
+ IOMUX_PAD_CTRL(SD3_DAT1__SD3_DATA1, USDHC_PAD_CTRL),
+ IOMUX_PAD_CTRL(SD3_DAT2__SD3_DATA2, USDHC_PAD_CTRL),
+ IOMUX_PAD_CTRL(SD3_DAT3__SD3_DATA3, USDHC_PAD_CTRL),
+#define GP_USDHC3_CD IMX_GPIO_NR(7, 0)
+ IOMUX_PAD_CTRL(SD3_DAT5__GPIO7_IO00, WEAK_PULLUP),
+
+ /* USDHC4 - sdcard */
+ IOMUX_PAD_CTRL(SD4_CLK__SD4_CLK, USDHC_PAD_CTRL),
+ IOMUX_PAD_CTRL(SD4_CMD__SD4_CMD, USDHC_PAD_CTRL),
+ IOMUX_PAD_CTRL(SD4_DAT0__SD4_DATA0, USDHC_PAD_CTRL),
+ IOMUX_PAD_CTRL(SD4_DAT1__SD4_DATA1, USDHC_PAD_CTRL),
+ IOMUX_PAD_CTRL(SD4_DAT2__SD4_DATA2, USDHC_PAD_CTRL),
+ IOMUX_PAD_CTRL(SD4_DAT3__SD4_DATA3, USDHC_PAD_CTRL),
+#define GP_USDHC4_CD IMX_GPIO_NR(2, 6)
+ IOMUX_PAD_CTRL(NANDF_D6__GPIO2_IO06, WEAK_PULLUP),
+
+ /* wl1271 */
+#define GPIRQ_WL1271_WL IMX_GPIO_NR(6, 14)
+ IOMUX_PAD_CTRL(NANDF_CS1__GPIO6_IO14, WEAK_PULLDN),
};
-static iomux_v3_cfg_t const misc_pads[] = {
- MX6_PAD_GPIO_1__USB_OTG_ID | MUX_PAD_CTRL(WEAK_PULLUP),
- MX6_PAD_KEY_COL4__USB_OTG_OC | MUX_PAD_CTRL(WEAK_PULLUP),
- MX6_PAD_EIM_D30__USB_H1_OC | MUX_PAD_CTRL(WEAK_PULLUP),
- /* OTG Power enable */
- MX6_PAD_EIM_D22__GPIO3_IO22 | MUX_PAD_CTRL(OUTPUT_40OHM),
+#ifdef CONFIG_CMD_FBPANEL
+static const iomux_v3_cfg_t rgb666_pads[] = {
+ IOMUX_PAD_CTRL(DI0_DISP_CLK__IPU1_DI0_DISP_CLK, RGB_PAD_CTRL),
+ IOMUX_PAD_CTRL(DI0_PIN15__IPU1_DI0_PIN15, RGB_PAD_CTRL), /* DRDY */
+ IOMUX_PAD_CTRL(DI0_PIN2__IPU1_DI0_PIN02, RGB_PAD_CTRL), /* HSYNC */
+ IOMUX_PAD_CTRL(DI0_PIN3__IPU1_DI0_PIN03, RGB_PAD_CTRL), /* VSYNC */
+ IOMUX_PAD_CTRL(DISP0_DAT0__IPU1_DISP0_DATA00, RGB_PAD_CTRL),
+ IOMUX_PAD_CTRL(DISP0_DAT1__IPU1_DISP0_DATA01, RGB_PAD_CTRL),
+ IOMUX_PAD_CTRL(DISP0_DAT2__IPU1_DISP0_DATA02, RGB_PAD_CTRL),
+ IOMUX_PAD_CTRL(DISP0_DAT3__IPU1_DISP0_DATA03, RGB_PAD_CTRL),
+ IOMUX_PAD_CTRL(DISP0_DAT4__IPU1_DISP0_DATA04, RGB_PAD_CTRL),
+ IOMUX_PAD_CTRL(DISP0_DAT5__IPU1_DISP0_DATA05, RGB_PAD_CTRL),
+ IOMUX_PAD_CTRL(DISP0_DAT6__IPU1_DISP0_DATA06, RGB_PAD_CTRL),
+ IOMUX_PAD_CTRL(DISP0_DAT7__IPU1_DISP0_DATA07, RGB_PAD_CTRL),
+ IOMUX_PAD_CTRL(DISP0_DAT8__IPU1_DISP0_DATA08, RGB_PAD_CTRL),
+ IOMUX_PAD_CTRL(DISP0_DAT9__IPU1_DISP0_DATA09, RGB_PAD_CTRL),
+ IOMUX_PAD_CTRL(DISP0_DAT10__IPU1_DISP0_DATA10, RGB_PAD_CTRL),
+ IOMUX_PAD_CTRL(DISP0_DAT11__IPU1_DISP0_DATA11, RGB_PAD_CTRL),
+ IOMUX_PAD_CTRL(DISP0_DAT12__IPU1_DISP0_DATA12, RGB_PAD_CTRL),
+ IOMUX_PAD_CTRL(DISP0_DAT13__IPU1_DISP0_DATA13, RGB_PAD_CTRL),
+ IOMUX_PAD_CTRL(DISP0_DAT14__IPU1_DISP0_DATA14, RGB_PAD_CTRL),
+ IOMUX_PAD_CTRL(DISP0_DAT15__IPU1_DISP0_DATA15, RGB_PAD_CTRL),
+ IOMUX_PAD_CTRL(DISP0_DAT16__IPU1_DISP0_DATA16, RGB_PAD_CTRL),
+ IOMUX_PAD_CTRL(DISP0_DAT17__IPU1_DISP0_DATA17, RGB_PAD_CTRL),
};
-/* wl1271 pads on nitrogen6x */
-static iomux_v3_cfg_t const wl12xx_pads[] = {
- (MX6_PAD_NANDF_CS1__GPIO6_IO14 & ~MUX_PAD_CTRL_MASK)
- | MUX_PAD_CTRL(WEAK_PULLDOWN),
- (MX6_PAD_NANDF_CS2__GPIO6_IO15 & ~MUX_PAD_CTRL_MASK)
- | MUX_PAD_CTRL(OUTPUT_40OHM),
- (MX6_PAD_NANDF_CS3__GPIO6_IO16 & ~MUX_PAD_CTRL_MASK)
- | MUX_PAD_CTRL(OUTPUT_40OHM),
+static const iomux_v3_cfg_t rgb24_pads[] = {
+ IOMUX_PAD_CTRL(DISP0_DAT18__IPU1_DISP0_DATA18, RGB_PAD_CTRL),
+ IOMUX_PAD_CTRL(DISP0_DAT19__IPU1_DISP0_DATA19, RGB_PAD_CTRL),
+ IOMUX_PAD_CTRL(DISP0_DAT20__IPU1_DISP0_DATA20, RGB_PAD_CTRL),
+ IOMUX_PAD_CTRL(DISP0_DAT21__IPU1_DISP0_DATA21, RGB_PAD_CTRL),
+ IOMUX_PAD_CTRL(DISP0_DAT22__IPU1_DISP0_DATA22, RGB_PAD_CTRL),
+ IOMUX_PAD_CTRL(DISP0_DAT23__IPU1_DISP0_DATA23, RGB_PAD_CTRL),
};
-#define WL12XX_WL_IRQ_GP IMX_GPIO_NR(6, 14)
-#define WL12XX_WL_ENABLE_GP IMX_GPIO_NR(6, 15)
-#define WL12XX_BT_ENABLE_GP IMX_GPIO_NR(6, 16)
+#endif
-/* Button assignments for J14 */
-static iomux_v3_cfg_t const button_pads[] = {
- /* Menu */
- MX6_PAD_NANDF_D1__GPIO2_IO01 | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
- /* Back */
- MX6_PAD_NANDF_D2__GPIO2_IO02 | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
- /* Labelled Search (mapped to Power under Android) */
- MX6_PAD_NANDF_D3__GPIO2_IO03 | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
- /* Home */
- MX6_PAD_NANDF_D4__GPIO2_IO04 | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
- /* Volume Down */
- MX6_PAD_GPIO_19__GPIO4_IO05 | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
- /* Volume Up */
- MX6_PAD_GPIO_18__GPIO7_IO13 | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
+static const iomux_v3_cfg_t rgb_gpio_pads[] = {
+ IOMUX_PAD_CTRL(DI0_DISP_CLK__GPIO4_IO16, WEAK_PULLUP),
+ IOMUX_PAD_CTRL(DI0_PIN15__GPIO4_IO17, WEAK_PULLUP),
+ IOMUX_PAD_CTRL(DI0_PIN2__GPIO4_IO18, WEAK_PULLUP),
+ IOMUX_PAD_CTRL(DI0_PIN3__GPIO4_IO19, WEAK_PULLUP),
+ IOMUX_PAD_CTRL(DISP0_DAT0__GPIO4_IO21, WEAK_PULLUP),
+ IOMUX_PAD_CTRL(DISP0_DAT1__GPIO4_IO22, WEAK_PULLUP),
+ IOMUX_PAD_CTRL(DISP0_DAT2__GPIO4_IO23, WEAK_PULLUP),
+ IOMUX_PAD_CTRL(DISP0_DAT3__GPIO4_IO24, WEAK_PULLUP),
+ IOMUX_PAD_CTRL(DISP0_DAT4__GPIO4_IO25, WEAK_PULLUP),
+ IOMUX_PAD_CTRL(DISP0_DAT5__GPIO4_IO26, WEAK_PULLUP),
+ IOMUX_PAD_CTRL(DISP0_DAT6__GPIO4_IO27, WEAK_PULLUP),
+ IOMUX_PAD_CTRL(DISP0_DAT7__GPIO4_IO28, WEAK_PULLUP),
+ IOMUX_PAD_CTRL(DISP0_DAT8__GPIO4_IO29, WEAK_PULLUP),
+ IOMUX_PAD_CTRL(DISP0_DAT9__GPIO4_IO30, WEAK_PULLUP),
+ IOMUX_PAD_CTRL(DISP0_DAT10__GPIO4_IO31, WEAK_PULLUP),
+ IOMUX_PAD_CTRL(DISP0_DAT11__GPIO5_IO05, WEAK_PULLUP),
+ IOMUX_PAD_CTRL(DISP0_DAT12__GPIO5_IO06, WEAK_PULLUP),
+ IOMUX_PAD_CTRL(DISP0_DAT13__GPIO5_IO07, WEAK_PULLUP),
+ IOMUX_PAD_CTRL(DISP0_DAT14__GPIO5_IO08, WEAK_PULLUP),
+ IOMUX_PAD_CTRL(DISP0_DAT15__GPIO5_IO09, WEAK_PULLUP),
+ IOMUX_PAD_CTRL(DISP0_DAT16__GPIO5_IO10, WEAK_PULLUP),
+ IOMUX_PAD_CTRL(DISP0_DAT17__GPIO5_IO11, WEAK_PULLUP),
+ IOMUX_PAD_CTRL(DISP0_DAT18__GPIO5_IO12, WEAK_PULLUP),
+ IOMUX_PAD_CTRL(DISP0_DAT19__GPIO5_IO13, WEAK_PULLUP),
+ IOMUX_PAD_CTRL(DISP0_DAT20__GPIO5_IO14, WEAK_PULLUP),
+ IOMUX_PAD_CTRL(DISP0_DAT21__GPIO5_IO15, WEAK_PULLUP),
+ IOMUX_PAD_CTRL(DISP0_DAT22__GPIO5_IO16, WEAK_PULLUP),
+ IOMUX_PAD_CTRL(DISP0_DAT23__GPIO5_IO17, WEAK_PULLUP),
};
-static void setup_iomux_enet(void)
-{
- gpio_direction_output(IMX_GPIO_NR(3, 23), 0); /* SABRE Lite PHY rst */
- gpio_direction_output(IMX_GPIO_NR(1, 27), 0); /* Nitrogen6X PHY rst */
- gpio_direction_output(IMX_GPIO_NR(6, 30), 1);
- gpio_direction_output(IMX_GPIO_NR(6, 25), 1);
- gpio_direction_output(IMX_GPIO_NR(6, 27), 1);
- gpio_direction_output(IMX_GPIO_NR(6, 28), 1);
- gpio_direction_output(IMX_GPIO_NR(6, 29), 1);
- imx_iomux_v3_setup_multiple_pads(enet_pads1, ARRAY_SIZE(enet_pads1));
- gpio_direction_output(IMX_GPIO_NR(6, 24), 1);
-
- /* Need delay 10ms according to KSZ9021 spec */
- udelay(1000 * 10);
- gpio_set_value(IMX_GPIO_NR(3, 23), 1); /* SABRE Lite PHY reset */
- gpio_set_value(IMX_GPIO_NR(1, 27), 1); /* Nitrogen6X PHY reset */
-
- imx_iomux_v3_setup_multiple_pads(enet_pads2, ARRAY_SIZE(enet_pads2));
- udelay(100); /* Wait 100 us before using mii interface */
-}
-
-static iomux_v3_cfg_t const usb_pads[] = {
- MX6_PAD_GPIO_17__GPIO7_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL),
+static const struct i2c_pads_info i2c_pads[] = {
+ /* I2C1, SGTL5000 */
+ I2C_PADS_INFO_ENTRY(I2C1, EIM_D21, 3, 21, EIM_D28, 3, 28, I2C_PAD_CTRL),
+ /* I2C2 Camera, MIPI */
+ I2C_PADS_INFO_ENTRY(I2C2, KEY_COL3, 4, 12, KEY_ROW3, 4, 13, I2C_PAD_CTRL),
+ /* I2C3, J15 - RGB connector */
+ I2C_PADS_INFO_ENTRY(I2C3, GPIO_5, 1, 05, GPIO_16, 7, 11, I2C_PAD_CTRL),
};
-
-static void setup_iomux_uart(void)
-{
- imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
- imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads));
-}
+#define I2C_BUS_CNT 3
#ifdef CONFIG_USB_EHCI_MX6
int board_ehci_hcd_init(int port)
{
- imx_iomux_v3_setup_multiple_pads(usb_pads, ARRAY_SIZE(usb_pads));
-
- /* Reset USB hub */
- gpio_direction_output(IMX_GPIO_NR(7, 12), 0);
- mdelay(2);
- gpio_set_value(IMX_GPIO_NR(7, 12), 1);
+ if (port) {
+ /* Reset USB hub */
+ gpio_set_value(GP_USB_HUB_RESET, 0);
+ mdelay(2);
+ gpio_set_value(GP_USB_HUB_RESET, 1);
+ }
return 0;
}
@@ -277,749 +300,197 @@ int board_ehci_power(int port, int on)
{
if (port)
return 0;
- gpio_set_value(GP_USB_OTG_PWR, on);
+ gpio_set_value(GP_REG_USBOTG, on);
return 0;
}
#endif
#ifdef CONFIG_FSL_ESDHC
-static struct fsl_esdhc_cfg usdhc_cfg[2] = {
- {USDHC3_BASE_ADDR},
- {USDHC4_BASE_ADDR},
+struct fsl_esdhc_cfg board_usdhc_cfg[] = {
+ {.esdhc_base = USDHC3_BASE_ADDR, .bus_width = 4,
+ .gp_cd = GP_USDHC3_CD},
+ {.esdhc_base = USDHC4_BASE_ADDR, .bus_width = 4,
+ .gp_cd = GP_USDHC4_CD},
};
-
-int board_mmc_getcd(struct mmc *mmc)
-{
- struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
- int gp_cd = (cfg->esdhc_base == USDHC3_BASE_ADDR) ? IMX_GPIO_NR(7, 0) :
- IMX_GPIO_NR(2, 6);
-
- gpio_direction_input(gp_cd);
- return !gpio_get_value(gp_cd);
-}
-
-int board_mmc_init(bd_t *bis)
-{
- int ret;
- u32 index = 0;
-
- usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
- usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
-
- usdhc_cfg[0].max_bus_width = 4;
- usdhc_cfg[1].max_bus_width = 4;
-
- for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) {
- switch (index) {
- case 0:
- imx_iomux_v3_setup_multiple_pads(
- usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
- break;
- case 1:
- imx_iomux_v3_setup_multiple_pads(
- usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
- break;
- default:
- printf("Warning: you configured more USDHC controllers"
- "(%d) then supported by the board (%d)\n",
- index + 1, CONFIG_SYS_FSL_USDHC_NUM);
- return -EINVAL;
- }
-
- ret = fsl_esdhc_initialize(bis, &usdhc_cfg[index]);
- if (ret)
- return ret;
- }
-
- return 0;
-}
#endif
#ifdef CONFIG_MXC_SPI
int board_spi_cs_gpio(unsigned bus, unsigned cs)
{
- return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(3, 19)) : -1;
-}
-
-static iomux_v3_cfg_t const ecspi1_pads[] = {
- /* SS1 */
- MX6_PAD_EIM_D19__GPIO3_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL),
- MX6_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
- MX6_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
- MX6_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
-};
-
-static void setup_spi(void)
-{
- imx_iomux_v3_setup_multiple_pads(ecspi1_pads,
- ARRAY_SIZE(ecspi1_pads));
+ if (bus == 0 && cs == 0)
+ return GP_ECSPI1_NOR_CS;
+ if (bus == 1 && cs == 0)
+ return GP_ECSPI2_CS;
+ if (cs >> 8)
+ return (cs >> 8);
+ return -1;
}
#endif
-int board_phy_config(struct phy_device *phydev)
+#ifdef CONFIG_CMD_FBPANEL
+void board_enable_lvds(const struct display_info_t *di, int enable)
{
- /* min rx data delay */
- ksz9021_phy_extended_write(phydev,
- MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW, 0x0);
- /* min tx data delay */
- ksz9021_phy_extended_write(phydev,
- MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW, 0x0);
- /* max rx/tx clock delay, min rx/tx control */
- ksz9021_phy_extended_write(phydev,
- MII_KSZ9021_EXT_RGMII_CLOCK_SKEW, 0xf0f0);
- if (phydev->drv->config)
- phydev->drv->config(phydev);
-
- return 0;
+ gpio_direction_output(GP_BACKLIGHT_LVDS, enable);
}
-int board_eth_init(bd_t *bis)
+void board_enable_lcd(const struct display_info_t *di, int enable)
{
- uint32_t base = IMX_FEC_BASE;
- struct mii_dev *bus = NULL;
- struct phy_device *phydev = NULL;
- int ret;
-
- setup_iomux_enet();
-
-#ifdef CONFIG_FEC_MXC
- bus = fec_get_miibus(base, -1);
- if (!bus)
- return -EINVAL;
- /* scan phy 4,5,6,7 */
- phydev = phy_find_by_mask(bus, (0xf << 4), PHY_INTERFACE_MODE_RGMII);
- if (!phydev) {
- ret = -EINVAL;
- goto free_bus;
- }
- printf("using phy at %d\n", phydev->addr);
- ret = fec_probe(bis, -1, base, bus, phydev);
- if (ret)
- goto free_phydev;
+ if (enable) {
+ SETUP_IOMUX_PADS(rgb666_pads);
+ if ((di->pixfmt == IPU_PIX_FMT_RGB24) ||
+ (di->pixfmt == IPU_PIX_FMT_BGR24))
+ SETUP_IOMUX_PADS(rgb24_pads);
+#ifdef CONFIG_MXC_SPI_DISPLAY
+ if (di->fbflags & FBF_SPI)
+ enable_spi_rgb(di);
#endif
-
-#ifdef CONFIG_CI_UDC
- /* For otg ethernet*/
- usb_eth_initialize(bis);
-#endif
- return 0;
-
-free_phydev:
- free(phydev);
-free_bus:
- free(bus);
- return ret;
-}
-
-static void setup_buttons(void)
-{
- imx_iomux_v3_setup_multiple_pads(button_pads,
- ARRAY_SIZE(button_pads));
-}
-
-#if defined(CONFIG_VIDEO_IPUV3)
-
-static iomux_v3_cfg_t const backlight_pads[] = {
- /* Backlight on RGB connector: J15 */
- MX6_PAD_SD1_DAT3__GPIO1_IO21 | MUX_PAD_CTRL(NO_PAD_CTRL),
-#define RGB_BACKLIGHT_GP IMX_GPIO_NR(1, 21)
-
- /* Backlight on LVDS connector: J6 */
- MX6_PAD_SD1_CMD__GPIO1_IO18 | MUX_PAD_CTRL(NO_PAD_CTRL),
-#define LVDS_BACKLIGHT_GP IMX_GPIO_NR(1, 18)
-};
-
-static iomux_v3_cfg_t const rgb_pads[] = {
- MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK,
- MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15,
- MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02,
- MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03,
- MX6_PAD_DI0_PIN4__GPIO4_IO20,
- MX6_PAD_DISP0_DAT0__IPU1_DISP0_DATA00,
- MX6_PAD_DISP0_DAT1__IPU1_DISP0_DATA01,
- MX6_PAD_DISP0_DAT2__IPU1_DISP0_DATA02,
- MX6_PAD_DISP0_DAT3__IPU1_DISP0_DATA03,
- MX6_PAD_DISP0_DAT4__IPU1_DISP0_DATA04,
- MX6_PAD_DISP0_DAT5__IPU1_DISP0_DATA05,
- MX6_PAD_DISP0_DAT6__IPU1_DISP0_DATA06,
- MX6_PAD_DISP0_DAT7__IPU1_DISP0_DATA07,
- MX6_PAD_DISP0_DAT8__IPU1_DISP0_DATA08,
- MX6_PAD_DISP0_DAT9__IPU1_DISP0_DATA09,
- MX6_PAD_DISP0_DAT10__IPU1_DISP0_DATA10,
- MX6_PAD_DISP0_DAT11__IPU1_DISP0_DATA11,
- MX6_PAD_DISP0_DAT12__IPU1_DISP0_DATA12,
- MX6_PAD_DISP0_DAT13__IPU1_DISP0_DATA13,
- MX6_PAD_DISP0_DAT14__IPU1_DISP0_DATA14,
- MX6_PAD_DISP0_DAT15__IPU1_DISP0_DATA15,
- MX6_PAD_DISP0_DAT16__IPU1_DISP0_DATA16,
- MX6_PAD_DISP0_DAT17__IPU1_DISP0_DATA17,
- MX6_PAD_DISP0_DAT18__IPU1_DISP0_DATA18,
- MX6_PAD_DISP0_DAT19__IPU1_DISP0_DATA19,
- MX6_PAD_DISP0_DAT20__IPU1_DISP0_DATA20,
- MX6_PAD_DISP0_DAT21__IPU1_DISP0_DATA21,
- MX6_PAD_DISP0_DAT22__IPU1_DISP0_DATA22,
- MX6_PAD_DISP0_DAT23__IPU1_DISP0_DATA23,
-};
-
-static void do_enable_hdmi(struct display_info_t const *dev)
-{
- imx_enable_hdmi_phy();
-}
-
-static int detect_i2c(struct display_info_t const *dev)
-{
- return ((0 == i2c_set_bus_num(dev->bus))
- &&
- (0 == i2c_probe(dev->addr)));
-}
-
-static void enable_lvds(struct display_info_t const *dev)
-{
- struct iomuxc *iomux = (struct iomuxc *)
- IOMUXC_BASE_ADDR;
- u32 reg = readl(&iomux->gpr[2]);
- reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT;
- writel(reg, &iomux->gpr[2]);
- gpio_direction_output(LVDS_BACKLIGHT_GP, 1);
-}
-
-static void enable_lvds_jeida(struct display_info_t const *dev)
-{
- struct iomuxc *iomux = (struct iomuxc *)
- IOMUXC_BASE_ADDR;
- u32 reg = readl(&iomux->gpr[2]);
- reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT
- |IOMUXC_GPR2_BIT_MAPPING_CH0_JEIDA;
- writel(reg, &iomux->gpr[2]);
- gpio_direction_output(LVDS_BACKLIGHT_GP, 1);
-}
-
-static void enable_rgb(struct display_info_t const *dev)
-{
- imx_iomux_v3_setup_multiple_pads(
- rgb_pads,
- ARRAY_SIZE(rgb_pads));
- gpio_direction_output(RGB_BACKLIGHT_GP, 1);
+ mdelay(100); /* let panel sync up before enabling backlight */
+ gpio_direction_output(GP_BACKLIGHT_RGB, enable);
+ } else {
+ gpio_direction_output(GP_BACKLIGHT_RGB, enable);
+ SETUP_IOMUX_PADS(rgb_gpio_pads);
+ }
}
-struct display_info_t const displays[] = {{
- .bus = 1,
- .addr = 0x50,
- .pixfmt = IPU_PIX_FMT_RGB24,
- .detect = detect_i2c,
- .enable = do_enable_hdmi,
- .mode = {
- .name = "HDMI",
- .refresh = 60,
- .xres = 1024,
- .yres = 768,
- .pixclock = 15385,
- .left_margin = 220,
- .right_margin = 40,
- .upper_margin = 21,
- .lower_margin = 7,
- .hsync_len = 60,
- .vsync_len = 10,
- .sync = FB_SYNC_EXT,
- .vmode = FB_VMODE_NONINTERLACED
-} }, {
- .bus = 0,
- .addr = 0,
- .pixfmt = IPU_PIX_FMT_RGB24,
- .detect = NULL,
- .enable = enable_lvds_jeida,
- .mode = {
- .name = "LDB-WXGA",
- .refresh = 60,
- .xres = 1280,
- .yres = 800,
- .pixclock = 14065,
- .left_margin = 40,
- .right_margin = 40,
- .upper_margin = 3,
- .lower_margin = 80,
- .hsync_len = 10,
- .vsync_len = 10,
- .sync = FB_SYNC_EXT,
- .vmode = FB_VMODE_NONINTERLACED
-} }, {
- .bus = 0,
- .addr = 0,
- .pixfmt = IPU_PIX_FMT_RGB24,
- .detect = NULL,
- .enable = enable_lvds,
- .mode = {
- .name = "LDB-WXGA-S",
- .refresh = 60,
- .xres = 1280,
- .yres = 800,
- .pixclock = 14065,
- .left_margin = 40,
- .right_margin = 40,
- .upper_margin = 3,
- .lower_margin = 80,
- .hsync_len = 10,
- .vsync_len = 10,
- .sync = FB_SYNC_EXT,
- .vmode = FB_VMODE_NONINTERLACED
-} }, {
- .bus = 2,
- .addr = 0x4,
- .pixfmt = IPU_PIX_FMT_LVDS666,
- .detect = detect_i2c,
- .enable = enable_lvds,
- .mode = {
- .name = "Hannstar-XGA",
- .refresh = 60,
- .xres = 1024,
- .yres = 768,
- .pixclock = 15385,
- .left_margin = 220,
- .right_margin = 40,
- .upper_margin = 21,
- .lower_margin = 7,
- .hsync_len = 60,
- .vsync_len = 10,
- .sync = FB_SYNC_EXT,
- .vmode = FB_VMODE_NONINTERLACED
-} }, {
- .bus = 0,
- .addr = 0,
- .pixfmt = IPU_PIX_FMT_LVDS666,
- .detect = NULL,
- .enable = enable_lvds,
- .mode = {
- .name = "LG-9.7",
- .refresh = 60,
- .xres = 1024,
- .yres = 768,
- .pixclock = 15385, /* ~65MHz */
- .left_margin = 480,
- .right_margin = 260,
- .upper_margin = 16,
- .lower_margin = 6,
- .hsync_len = 250,
- .vsync_len = 10,
- .sync = FB_SYNC_EXT,
- .vmode = FB_VMODE_NONINTERLACED
-} }, {
- .bus = 2,
- .addr = 0x38,
- .pixfmt = IPU_PIX_FMT_LVDS666,
- .detect = detect_i2c,
- .enable = enable_lvds,
- .mode = {
- .name = "wsvga-lvds",
- .refresh = 60,
- .xres = 1024,
- .yres = 600,
- .pixclock = 15385,
- .left_margin = 220,
- .right_margin = 40,
- .upper_margin = 21,
- .lower_margin = 7,
- .hsync_len = 60,
- .vsync_len = 10,
- .sync = FB_SYNC_EXT,
- .vmode = FB_VMODE_NONINTERLACED
-} }, {
- .bus = 2,
- .addr = 0x10,
- .pixfmt = IPU_PIX_FMT_RGB666,
- .detect = detect_i2c,
- .enable = enable_rgb,
- .mode = {
- .name = "fusion7",
- .refresh = 60,
- .xres = 800,
- .yres = 480,
- .pixclock = 33898,
- .left_margin = 96,
- .right_margin = 24,
- .upper_margin = 3,
- .lower_margin = 10,
- .hsync_len = 72,
- .vsync_len = 7,
- .sync = 0x40000002,
- .vmode = FB_VMODE_NONINTERLACED
-} }, {
- .bus = 0,
- .addr = 0,
- .pixfmt = IPU_PIX_FMT_RGB666,
- .detect = NULL,
- .enable = enable_rgb,
- .mode = {
- .name = "svga",
- .refresh = 60,
- .xres = 800,
- .yres = 600,
- .pixclock = 15385,
- .left_margin = 220,
- .right_margin = 40,
- .upper_margin = 21,
- .lower_margin = 7,
- .hsync_len = 60,
- .vsync_len = 10,
- .sync = 0,
- .vmode = FB_VMODE_NONINTERLACED
-} }, {
- .bus = 2,
- .addr = 0x41,
- .pixfmt = IPU_PIX_FMT_LVDS666,
- .detect = detect_i2c,
- .enable = enable_lvds,
- .mode = {
- .name = "amp1024x600",
- .refresh = 60,
- .xres = 1024,
- .yres = 600,
- .pixclock = 15385,
- .left_margin = 220,
- .right_margin = 40,
- .upper_margin = 21,
- .lower_margin = 7,
- .hsync_len = 60,
- .vsync_len = 10,
- .sync = FB_SYNC_EXT,
- .vmode = FB_VMODE_NONINTERLACED
-} }, {
- .bus = 0,
- .addr = 0,
- .pixfmt = IPU_PIX_FMT_LVDS666,
- .detect = 0,
- .enable = enable_lvds,
- .mode = {
- .name = "wvga-lvds",
- .refresh = 57,
- .xres = 800,
- .yres = 480,
- .pixclock = 15385,
- .left_margin = 220,
- .right_margin = 40,
- .upper_margin = 21,
- .lower_margin = 7,
- .hsync_len = 60,
- .vsync_len = 10,
- .sync = FB_SYNC_EXT,
- .vmode = FB_VMODE_NONINTERLACED
-} }, {
- .bus = 2,
- .addr = 0x48,
- .pixfmt = IPU_PIX_FMT_RGB666,
- .detect = detect_i2c,
- .enable = enable_rgb,
- .mode = {
- .name = "wvga-rgb",
- .refresh = 57,
- .xres = 800,
- .yres = 480,
- .pixclock = 37037,
- .left_margin = 40,
- .right_margin = 60,
- .upper_margin = 10,
- .lower_margin = 10,
- .hsync_len = 20,
- .vsync_len = 10,
- .sync = 0,
- .vmode = FB_VMODE_NONINTERLACED
-} }, {
- .bus = 0,
- .addr = 0,
- .pixfmt = IPU_PIX_FMT_RGB24,
- .detect = NULL,
- .enable = enable_rgb,
- .mode = {
- .name = "qvga",
- .refresh = 60,
- .xres = 320,
- .yres = 240,
- .pixclock = 37037,
- .left_margin = 38,
- .right_margin = 37,
- .upper_margin = 16,
- .lower_margin = 15,
- .hsync_len = 30,
- .vsync_len = 3,
- .sync = 0,
- .vmode = FB_VMODE_NONINTERLACED
-} } };
-size_t display_count = ARRAY_SIZE(displays);
-
-int board_cfb_skip(void)
+void board_pre_enable(const struct display_info_t *di)
{
- return NULL != env_get("novideo");
+ SETUP_IOMUX_PADS(rgb666_pads);
+ enable_spi_rgb(di);
}
-static void setup_display(void)
-{
- struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
- struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
- int reg;
-
- enable_ipu_clock();
- imx_setup_hdmi();
- /* Turn on LDB0,IPU,IPU DI0 clocks */
- reg = __raw_readl(&mxc_ccm->CCGR3);
- reg |= MXC_CCM_CCGR3_LDB_DI0_MASK;
- writel(reg, &mxc_ccm->CCGR3);
-
- /* set LDB0, LDB1 clk select to 011/011 */
- reg = readl(&mxc_ccm->cs2cdr);
- reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
- |MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
- reg |= (3<<MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
- |(3<<MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
- writel(reg, &mxc_ccm->cs2cdr);
-
- reg = readl(&mxc_ccm->cscmr2);
- reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
- writel(reg, &mxc_ccm->cscmr2);
-
- reg = readl(&mxc_ccm->chsccdr);
- reg |= (CHSCCDR_CLK_SEL_LDB_DI0
- <<MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
- writel(reg, &mxc_ccm->chsccdr);
-
- reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
- |IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH
- |IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
- |IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
- |IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT
- |IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
- |IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT
- |IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED
- |IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
- writel(reg, &iomux->gpr[2]);
-
- reg = readl(&iomux->gpr[3]);
- reg = (reg & ~(IOMUXC_GPR3_LVDS0_MUX_CTL_MASK
- |IOMUXC_GPR3_HDMI_MUX_CTL_MASK))
- | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
- <<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
- writel(reg, &iomux->gpr[3]);
-
- /* backlights off until needed */
- imx_iomux_v3_setup_multiple_pads(backlight_pads,
- ARRAY_SIZE(backlight_pads));
- gpio_direction_input(LVDS_BACKLIGHT_GP);
- gpio_direction_input(RGB_BACKLIGHT_GP);
-}
+static const struct display_info_t displays[] = {
+ /* hdmi */
+ VD_1280_720M_60(HDMI, fbp_detect_i2c, 1, 0x50),
+ VD_1920_1080M_60(HDMI, NULL, 1, 0x50),
+ VD_1024_768M_60(HDMI, NULL, 1, 0x50),
+ VD_640_480M_60(HDMI, NULL, 1, 0x50),
+ VD_720_480M_60(HDMI, NULL, 1, 0x50),
+
+ /* ft5x06 */
+ VD_HANNSTAR7(LVDS, fbp_detect_i2c, 2, 0x38),
+ VD_AUO_B101EW05(LVDS, NULL, 2, 0x38),
+ VD_LG1280_800(LVDS, NULL, 2, 0x38),
+ VD_DT070BTFT(LVDS, NULL, 2, 0x38),
+ VD_WSVGA(LVDS, NULL, 2, 0x38),
+ VD_TM070JDHG30(LVDS, NULL, 2, 0x38),
+
+ /* ili210x */
+ VD_AMP1024_600(LVDS, fbp_detect_i2c, 2, 0x41),
+
+ /* egalax_ts */
+ VD_HANNSTAR(LVDS, fbp_detect_i2c, 2, 0x04),
+ VD_LG9_7(LVDS, NULL, 2, 0x04),
+
+ /* fusion7 specific touchscreen */
+ VD_FUSION7(LCD, fbp_detect_i2c, 2, 0x10),
+
+ VD_SHARP_LQ101K1LY04(LVDS, NULL, 0, 0x00),
+ VD_WXGA_J(LVDS, NULL, 0, 0x00),
+ VD_WXGA(LVDS, NULL, 0, 0x00),
+ VD_WVGA(LVDS, NULL, 0, 0x00),
+ VD_AA065VE11(LVDS, NULL, 0, 0x00),
+ VD_VGA(LVDS, NULL, 0, 0x00),
+
+ /* tsc2004 */
+ VD_CLAA_WVGA(LCD, fbp_detect_i2c, 2, 0x48),
+ VD_SHARP_WVGA(LCD, NULL, 2, 0x48),
+ VD_DC050WX(LCD, NULL, 2, 0x48),
+ VD_QVGA(LCD, NULL, 2, 0x48),
+ VD_DT035BTFT(LCD, NULL, 2, 0x48),
+ VD_AT035GT_07ET3(LCD, NULL, 2, 0x48),
+
+ VD_LSA40AT9001(LCD, NULL, 0, 0x00),
+#ifdef CONFIG_MXC_SPI_DISPLAY
+ VD_AUO_G050(LCD, NULL, 1, 0),
+ VD_A030JN01_UPS051(LCD, NULL, 1, 2),
+ VD_A030JN01_YUV720(LCD, NULL, 1, 1),
+ VD_KD024FM(LCD, NULL, 2, 3),
#endif
-
-static iomux_v3_cfg_t const init_pads[] = {
- /* SGTL5000 sys_mclk */
- NEW_PAD_CTRL(MX6_PAD_GPIO_0__CCM_CLKO1, OUTPUT_40OHM),
-
- /* J5 - Camera MCLK */
- NEW_PAD_CTRL(MX6_PAD_GPIO_3__CCM_CLKO2, OUTPUT_40OHM),
-
- /* wl1271 pads on nitrogen6x */
- /* WL12XX_WL_IRQ_GP */
- NEW_PAD_CTRL(MX6_PAD_NANDF_CS1__GPIO6_IO14, WEAK_PULLDOWN),
- /* WL12XX_WL_ENABLE_GP */
- NEW_PAD_CTRL(MX6_PAD_NANDF_CS2__GPIO6_IO15, OUTPUT_40OHM),
- /* WL12XX_BT_ENABLE_GP */
- NEW_PAD_CTRL(MX6_PAD_NANDF_CS3__GPIO6_IO16, OUTPUT_40OHM),
- /* USB otg power */
- NEW_PAD_CTRL(MX6_PAD_EIM_D22__GPIO3_IO22, OUTPUT_40OHM),
- NEW_PAD_CTRL(MX6_PAD_NANDF_D5__GPIO2_IO05, OUTPUT_40OHM),
- NEW_PAD_CTRL(MX6_PAD_NANDF_WP_B__GPIO6_IO09, OUTPUT_40OHM),
- NEW_PAD_CTRL(MX6_PAD_GPIO_8__GPIO1_IO08, OUTPUT_40OHM),
- NEW_PAD_CTRL(MX6_PAD_GPIO_6__GPIO1_IO06, OUTPUT_40OHM),
};
+#define display_cnt ARRAY_SIZE(displays)
+#else
+#define displays NULL
+#define display_cnt 0
+#endif
-#define WL12XX_WL_IRQ_GP IMX_GPIO_NR(6, 14)
-
-static unsigned gpios_out_low[] = {
+static const unsigned short gpios_out_low[] = {
+ GP_RGMII2_PHY_RESET,
+ GP_RGMII_PHY_RESET,
+ GP_BACKLIGHT_LVDS,
+ GP_BACKLIGHT_RGB,
/* Disable wl1271 */
- IMX_GPIO_NR(6, 15), /* disable wireless */
- IMX_GPIO_NR(6, 16), /* disable bluetooth */
- IMX_GPIO_NR(3, 22), /* disable USB otg power */
- IMX_GPIO_NR(2, 5), /* ov5640 mipi camera reset */
- IMX_GPIO_NR(1, 8), /* ov5642 reset */
+ GP_REG_WLAN_EN,
+ GP_BT_RFKILL_RESET,
+ GP_REG_USBOTG,
+ GP_OV5642_RESET,
+ GP_USB_HUB_RESET,
};
-static unsigned gpios_out_high[] = {
- IMX_GPIO_NR(1, 6), /* ov5642 powerdown */
- IMX_GPIO_NR(6, 9), /* ov5640 mipi camera power down */
+static const unsigned short gpios_out_high[] = {
+ GP_ECSPI1_NOR_CS,
+ GP_SGTL5000_HP_MUTE,
+ GP_OV5642_POWER_DOWN,
+ GP_OV5640_MIPI_POWER_DOWN,
};
-static void set_gpios(unsigned *p, int cnt, int val)
-{
- int i;
-
- for (i = 0; i < cnt; i++)
- gpio_direction_output(*p++, val);
-}
+static const unsigned short gpios_in[] = {
+ GP_GPIOKEY_BACK,
+ GP_GPIOKEY_HOME,
+ GP_GPIOKEY_MENU,
+ GP_GPIOKEY_POWER,
+ GP_GPIOKEY_VOL_DOWN,
+ GP_GPIOKEY_VOL_UP,
+ GPIRQ_ENET_PHY,
+ GPIRQ_RTC_ISL1208,
+ GPIRQ_TC3587,
+ GPIRQ_WL1271_WL,
+ GP_USDHC3_CD,
+ GP_USDHC4_CD,
+};
int board_early_init_f(void)
{
- setup_iomux_uart();
-
+ set_gpios_in(gpios_in, ARRAY_SIZE(gpios_in));
set_gpios(gpios_out_high, ARRAY_SIZE(gpios_out_high), 1);
set_gpios(gpios_out_low, ARRAY_SIZE(gpios_out_low), 0);
- gpio_direction_input(WL12XX_WL_IRQ_GP);
-
- imx_iomux_v3_setup_multiple_pads(wl12xx_pads, ARRAY_SIZE(wl12xx_pads));
- imx_iomux_v3_setup_multiple_pads(init_pads, ARRAY_SIZE(init_pads));
- setup_buttons();
-
-#if defined(CONFIG_VIDEO_IPUV3)
- setup_display();
-#endif
+ SETUP_IOMUX_PADS(init_pads);
+ SETUP_IOMUX_PADS(rgb_gpio_pads);
return 0;
}
-/*
- * Do not overwrite the console
- * Use always serial for U-Boot console
- */
-int overwrite_console(void)
-{
- return 1;
-}
-
int board_init(void)
{
- struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
-
- clrsetbits_le32(&iomuxc_regs->gpr[1],
- IOMUXC_GPR1_OTG_ID_MASK,
- IOMUXC_GPR1_OTG_ID_GPIO1);
-
- imx_iomux_v3_setup_multiple_pads(misc_pads, ARRAY_SIZE(misc_pads));
-
- /* address of boot parameters */
- gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
-
-#ifdef CONFIG_MXC_SPI
- setup_spi();
-#endif
- imx_iomux_v3_setup_multiple_pads(
- usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
- setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info0);
- setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
- setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
-
-#ifdef CONFIG_SATA
- setup_sata();
-#endif
-
+ common_board_init(i2c_pads, I2C_BUS_CNT, IOMUXC_GPR1_OTG_ID_GPIO1,
+ displays, display_cnt, 0);
return 0;
}
-int checkboard(void)
+#ifndef CONFIG_SYS_BOARD
+const char *board_get_board_type(void)
{
- if (gpio_get_value(WL12XX_WL_IRQ_GP))
- puts("Board: Nitrogen6X\n");
- else
- puts("Board: SABRE Lite\n");
-
- return 0;
+ if (gpio_get_value(GPIRQ_WL1271_WL))
+ return "nitrogen6x";
+ return "sabrelite";
}
+#endif
-struct button_key {
- char const *name;
- unsigned gpnum;
- char ident;
+const struct button_key board_buttons[] = {
+ {"back", GP_GPIOKEY_BACK, 'B', 1},
+ {"home", GP_GPIOKEY_HOME, 'H', 1},
+ {"menu", GP_GPIOKEY_MENU, 'M', 1},
+ {"search", GP_GPIOKEY_POWER, 'S', 1},
+ {"volup", GP_GPIOKEY_VOL_UP, 'V', 1},
+ {"voldown", GP_GPIOKEY_VOL_DOWN, 'v', 1},
+ {NULL, 0, 0, 0},
};
-static struct button_key const buttons[] = {
- {"back", IMX_GPIO_NR(2, 2), 'B'},
- {"home", IMX_GPIO_NR(2, 4), 'H'},
- {"menu", IMX_GPIO_NR(2, 1), 'M'},
- {"search", IMX_GPIO_NR(2, 3), 'S'},
- {"volup", IMX_GPIO_NR(7, 13), 'V'},
- {"voldown", IMX_GPIO_NR(4, 5), 'v'},
-};
-
-/*
- * generate a null-terminated string containing the buttons pressed
- * returns number of keys pressed
- */
-static int read_keys(char *buf)
-{
- int i, numpressed = 0;
- for (i = 0; i < ARRAY_SIZE(buttons); i++) {
- if (!gpio_get_value(buttons[i].gpnum))
- buf[numpressed++] = buttons[i].ident;
- }
- buf[numpressed] = '\0';
- return numpressed;
-}
-
-static int do_kbd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- char envvalue[ARRAY_SIZE(buttons)+1];
- int numpressed = read_keys(envvalue);
- env_set("keybd", envvalue);
- return numpressed == 0;
-}
-
-U_BOOT_CMD(
- kbd, 1, 1, do_kbd,
- "Tests for keypresses, sets 'keybd' environment variable",
- "Returns 0 (true) to shell if key is pressed."
-);
-
-#ifdef CONFIG_PREBOOT
-static char const kbd_magic_prefix[] = "key_magic";
-static char const kbd_command_prefix[] = "key_cmd";
-
-static void preboot_keys(void)
-{
- int numpressed;
- char keypress[ARRAY_SIZE(buttons)+1];
- numpressed = read_keys(keypress);
- if (numpressed) {
- char *kbd_magic_keys = env_get("magic_keys");
- char *suffix;
- /*
- * loop over all magic keys
- */
- for (suffix = kbd_magic_keys; *suffix; ++suffix) {
- char *keys;
- char magic[sizeof(kbd_magic_prefix) + 1];
- sprintf(magic, "%s%c", kbd_magic_prefix, *suffix);
- keys = env_get(magic);
- if (keys) {
- if (!strcmp(keys, keypress))
- break;
- }
- }
- if (*suffix) {
- char cmd_name[sizeof(kbd_command_prefix) + 1];
- char *cmd;
- sprintf(cmd_name, "%s%c", kbd_command_prefix, *suffix);
- cmd = env_get(cmd_name);
- if (cmd) {
- env_set("preboot", cmd);
- return;
- }
- }
- }
-}
-#endif
#ifdef CONFIG_CMD_BMODE
-static const struct boot_mode board_boot_modes[] = {
+const struct boot_mode board_boot_modes[] = {
/* 4 bit bus width */
{"mmc0", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
{"mmc1", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)},
{NULL, 0},
};
#endif
-
-int misc_init_r(void)
-{
-#ifdef CONFIG_PREBOOT
- preboot_keys();
-#endif
-
-#ifdef CONFIG_CMD_BMODE
- add_board_boot_modes(board_boot_modes);
-#endif
- env_set_hex("reset_cause", get_imx_reset_cause());
- return 0;
-}
diff --git a/board/boundary/nitrogen6x/spi_display.c b/board/boundary/nitrogen6x/spi_display.c
new file mode 100644
index 0000000000000000000000000000000000000000..89b05c1a50e20cb6c300d341e1368a01eef5efff
--- /dev/null
+++ b/board/boundary/nitrogen6x/spi_display.c
@@ -0,0 +1,664 @@
+/*
+ * Copyright (C) 2010-2013 Freescale Semiconductor, Inc.
+ * Copyright (C) 2013, Boundary Devices <info@boundarydevices.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/gpio.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/spi.h>
+#include <asm/mach-imx/video.h>
+#include <spi.h>
+#include "spi_display.h"
+
+#define RGB_PAD_CTRL PAD_CTL_DSE_120ohm
+
+#define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
+ PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
+
+#define SPI_MOSI_R_PAD_CTRL SPI_PAD_CTRL | PAD_CTL_ODE | PAD_CTL_PUS_22K_UP
+
+#define GP_SPI_DISPLAY_RESET IMX_GPIO_NR(4, 20)
+
+#define WEAK_PULLDN (PAD_CTL_PUS_100K_DOWN | \
+ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
+ PAD_CTL_HYS | PAD_CTL_SRE_SLOW)
+
+#define WEAK_PULLDN_OUTPUT (PAD_CTL_PUS_100K_DOWN | \
+ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
+ PAD_CTL_SRE_SLOW)
+
+#define WEAK_PULLUP (PAD_CTL_PUS_100K_UP | \
+ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
+ PAD_CTL_HYS | PAD_CTL_SRE_SLOW)
+
+struct spi_display_info {
+ int mode;
+ int speed_r;
+ int speed_w;
+ int reset_active_low;
+ int cs_gpio;
+ int reset_gpio;
+ u8 *init_cmds;
+ u8 *on_cmds;
+ const iomux_v3_cfg_t *spi_mosi_r_pads;
+ const iomux_v3_cfg_t *spi_mosi_w_pads;
+ const iomux_v3_cfg_t *spi_ss0_pad;
+ const iomux_v3_cfg_t *spi_ss0_gpio_pad;
+ int (*spi_write_rtn)(struct spi_slave *spi, u8 *cmds);
+ int (*spi_read_rtn)(struct spi_slave *spi, int reg);
+ int (*spi_setup_rtn)(struct spi_display_info *di);
+ int (*spi_exit_rtn)(struct spi_display_info *di);
+};
+
+static iomux_v3_cfg_t const spi_mosi_r_pads[] = {
+ IOMUX_PAD_CTRL(CSI0_DAT9__ECSPI2_MOSI, SPI_MOSI_R_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const spi_mosi_w_pads[] = {
+ IOMUX_PAD_CTRL(CSI0_DAT9__ECSPI2_MOSI, SPI_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const spi_ss0_pad[] = {
+ IOMUX_PAD_CTRL(CSI0_DAT11__ECSPI2_SS0, SPI_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const spi_ss0_gpio_pad[] = {
+#define GP_ECSPI2_CS IMX_GPIO_NR(5, 29)
+ IOMUX_PAD_CTRL(CSI0_DAT11__GPIO5_IO29, SPI_PAD_CTRL),
+};
+
+static int AUO_G050_spi_write_rtn(struct spi_slave *spi, u8 *cmds)
+{
+ u8 buf[4];
+ int ret = 0;
+
+ debug("%s\n", __func__);
+ while (1) {
+ uint reg = (cmds[0] << 8) | cmds[1];
+ uint len = cmds[2];
+
+ if (!len && !reg)
+ break;
+ cmds += 3;
+ do {
+ buf[0] = 0x20;
+ buf[1] = reg >> 8;
+ ret = spi_xfer(spi, 2 * 8, buf, NULL, SPI_XFER_BEGIN | SPI_XFER_END);
+ if (ret) {
+ debug("%s: Failed to select reg1 0x%x, %d\n", __func__, reg, ret);
+ return ret;
+ }
+ udelay(2);
+ buf[0] = 0;
+ buf[1] = reg;
+ ret = spi_xfer(spi, 2 * 8, buf, NULL, SPI_XFER_BEGIN | SPI_XFER_END);
+ if (ret) {
+ debug("%s: Failed to select reg2 0x%x, %d\n", __func__, reg, ret);
+ return ret;
+ }
+ udelay(2);
+ if (!len) {
+ debug("spi: reg:%04x\n", reg);
+ break;
+ }
+ buf[0] = 0x40;
+ buf[1] = *cmds++;
+ ret = spi_xfer(spi, 2 * 8, buf, NULL, SPI_XFER_BEGIN | SPI_XFER_END);
+ if (ret) {
+ debug("%s: Failed to select reg3 0x%x, %d\n", __func__, reg, ret);
+ return ret;
+ }
+ debug("spi: reg:%04x %02x\n", reg, buf[1]);
+ udelay(2);
+ reg++;
+ } while (--len);
+ }
+ return ret;
+}
+
+static int AUO_G050_spi_read_rtn(struct spi_slave *spi, int reg)
+{
+ u8 buf[4];
+ u8 rbuf[4];
+ int ret = 0;
+
+ buf[0] = 0x20;
+ buf[1] = reg >> 8;
+ ret = spi_xfer(spi, 2 * 8, buf, NULL, SPI_XFER_BEGIN | SPI_XFER_END);
+ if (ret) {
+ debug("%s: Failed to select reg1 0x%x, %d\n", __func__, reg, ret);
+ return ret;
+ }
+ udelay(2);
+ buf[0] = 0;
+ buf[1] = reg;
+ ret = spi_xfer(spi, 2 * 8, buf, NULL, SPI_XFER_BEGIN | SPI_XFER_END);
+ if (ret) {
+ debug("%s: Failed to select reg2 0x%x, %d\n", __func__, reg, ret);
+ return ret;
+ }
+ udelay(2);
+ buf[0] = 0xC0;
+ buf[1] = 0xff;
+ ret = spi_xfer(spi, 2 * 8, buf, rbuf, SPI_XFER_BEGIN | SPI_XFER_END);
+ if (ret) {
+ debug("%s: Failed to select reg3 0x%x, %d\n", __func__, reg, ret);
+ return ret;
+ }
+ debug("spi: reg:0x%04x: %02x %02x\n", reg, rbuf[0], rbuf[1]);
+ udelay(2);
+ return rbuf[1];
+}
+
+#define A(reg, cnt) (reg >> 8), (reg & 0xff), cnt
+
+static u8 AUO_G050_display_init_cmds[] = {
+/* Display Mode Setting */
+ A(0xf000, 5), 0x55, 0xaa, 0x52, 0x08, 0x00,
+ A(0xb100, 2), 0x0c, 0x00,
+ A(0xbc00, 3), 0x05, 0x05, 0x05,
+ A(0xb700, 2), 0x22, 0x22,
+ A(0xb800, 4), 0x01, 0x03, 0x03, 0x03,
+ A(0xc803, 1), 0x96,
+ A(0xc805, 1), 0x96,
+ A(0xc807, 1), 0x96,
+ A(0xc809, 1), 0x96,
+ A(0xc80b, 1), 0x2a,
+ A(0xc80c, 1), 0x2a,
+ A(0xc80f, 1), 0x2a,
+ A(0xc810, 1), 0x2a,
+ A(0xf000, 5), 0x55, 0xaa, 0x52, 0x08, 0x01,
+ A(0xb900, 3), 0x34, 0x34, 0x34,
+ A(0xba00, 3), 0x14, 0x14, 0x14,
+ A(0xbe00, 2), 0x00, 0x8c,
+ A(0xb000, 3), 0x00, 0x00, 0x00,
+ A(0xb800, 3), 0x24, 0x24, 0x24,
+ A(0xbc00, 3), 0x00, 0x88, 0x01,
+ A(0xbd00, 3), 0x00, 0x88, 0x01,
+ A(0xd100, 52), 0x00, 0x00, 0x00, 0x10, 0x00, 0x31, 0x00, 0x5a, 0x00, 0x78, 0x00, 0x9b, 0x00, 0xbe, 0x00, 0xe6, 0x01, 0x04,
+ 0x01, 0x36, 0x01, 0x59, 0x01, 0x90, 0x01, 0xbd, 0x01, 0xbe, 0x01, 0xe5, 0x02, 0x0d, 0x02, 0x29, 0x02, 0x44,
+ 0x02, 0x5d, 0x02, 0xbc, 0x02, 0xe9, 0x03, 0x16, 0x03, 0x48, 0x03, 0xac, 0x03, 0xe8, 0x03, 0xff,
+ A(0xd200, 52), 0x00, 0x00, 0x00, 0x10, 0x00, 0x31, 0x00, 0x5a, 0x00, 0x78, 0x00, 0x9b, 0x00, 0xbe, 0x00, 0xe6, 0x01, 0x04,
+ 0x01, 0x36, 0x01, 0x59, 0x01, 0x90, 0x01, 0xbd, 0x01, 0xbe, 0x01, 0xe5, 0x02, 0x0d, 0x02, 0x29, 0x02, 0x44,
+ 0x02, 0x5d, 0x02, 0xbc, 0x02, 0xe9, 0x03, 0x16, 0x03, 0x48, 0x03, 0xac, 0x03, 0xe8, 0x03, 0xff,
+ A(0xd300, 52), 0x00, 0x00, 0x00, 0x10, 0x00, 0x31, 0x00, 0x5a, 0x00, 0x78, 0x00, 0x9b, 0x00, 0xbe, 0x00, 0xe6, 0x01, 0x04,
+ 0x01, 0x36, 0x01, 0x59, 0x01, 0x90, 0x01, 0xbd, 0x01, 0xbe, 0x01, 0xe5, 0x02, 0x0d, 0x02, 0x29, 0x02, 0x44,
+ 0x02, 0x5d, 0x02, 0xbc, 0x02, 0xe9, 0x03, 0x16, 0x03, 0x48, 0x03, 0xac, 0x03, 0xe8, 0x03, 0xff,
+ A(0xd400, 52), 0x00, 0x00, 0x00, 0x10, 0x00, 0x31, 0x00, 0x5a, 0x00, 0x78, 0x00, 0x9b, 0x00, 0xbe, 0x00, 0xe6, 0x01, 0x04,
+ 0x01, 0x36, 0x01, 0x59, 0x01, 0x90, 0x01, 0xbd, 0x01, 0xbe, 0x01, 0xe5, 0x02, 0x0d, 0x02, 0x29, 0x02, 0x44,
+ 0x02, 0x5d, 0x02, 0xbc, 0x02, 0xe9, 0x03, 0x16, 0x03, 0x48, 0x03, 0xac, 0x03, 0xe8, 0x03, 0xff,
+ A(0xd500, 52), 0x00, 0x00, 0x00, 0x10, 0x00, 0x31, 0x00, 0x5a, 0x00, 0x78, 0x00, 0x9b, 0x00, 0xbe, 0x00, 0xe6, 0x01, 0x04,
+ 0x01, 0x36, 0x01, 0x59, 0x01, 0x90, 0x01, 0xbd, 0x01, 0xbe, 0x01, 0xe5, 0x02, 0x0d, 0x02, 0x29, 0x02, 0x44,
+ 0x02, 0x5d, 0x02, 0xbc, 0x02, 0xe9, 0x03, 0x16, 0x03, 0x48, 0x03, 0xac, 0x03, 0xe8, 0x03, 0xff,
+ A(0xd600, 52), 0x00, 0x00, 0x00, 0x10, 0x00, 0x31, 0x00, 0x5a, 0x00, 0x78, 0x00, 0x9b, 0x00, 0xbe, 0x00, 0xe6, 0x01, 0x04,
+ 0x01, 0x36, 0x01, 0x59, 0x01, 0x90, 0x01, 0xbd, 0x01, 0xbe, 0x01, 0xe5, 0x02, 0x0d, 0x02, 0x29, 0x02, 0x44,
+ 0x02, 0x5d, 0x02, 0xbc, 0x02, 0xe9, 0x03, 0x16, 0x03, 0x48, 0x03, 0xac, 0x03, 0xe8, 0x03, 0xff,
+ A(0x1100, 0), /* exit sleep mode, wait 120 ms */
+ A(0, 0)
+};
+
+static u8 AUO_G050_display_on_cmds[] = {
+ A(0x2900, 0),
+ A(0, 0)
+};
+
+/* *************************************************** */
+
+static int A030JN01_spi_write_rtn(struct spi_slave *spi, u8 *cmds)
+{
+ u8 buf[4];
+ int ret = 0;
+
+ while (1) {
+ uint reg = (cmds[0] << 8) | cmds[1];
+ uint len = cmds[2];
+
+ if (!len && !reg)
+ break;
+ cmds += 3;
+ do {
+ buf[0] = reg + (reg & 0x40);
+ buf[1] = *cmds++;
+ ret = spi_xfer(spi, 2 * 8, buf, NULL, SPI_XFER_BEGIN | SPI_XFER_END);
+ if (ret) {
+ debug("%s: Failed 0x%x, %d\n", __func__, reg, ret);
+ return ret;
+ }
+ debug("spi: reg:%02x %02x\n", reg, buf[1]);
+ udelay(2);
+ reg++;
+ } while (--len);
+ }
+ return ret;
+}
+
+static int A030JN01_spi_read_rtn(struct spi_slave *spi, int reg)
+{
+ u8 buf[4];
+ u8 rbuf[4];
+ int ret = 0;
+
+ buf[0] = (reg + (reg & 0x40)) | 0x40;
+ buf[1] = 0xff;
+ ret = spi_xfer(spi, 2 * 8, buf, rbuf, SPI_XFER_BEGIN | SPI_XFER_END);
+ if (ret) {
+ debug("%s: Failed 0x%x, %d\n", __func__, reg, ret);
+ return ret;
+ }
+ debug("spi: reg:0x%02x: %02x %02x\n", reg, rbuf[0], rbuf[1]);
+ return rbuf[1];
+}
+
+static u8 A030JN01_display_YUV720_init_cmds[] = {
+/* Display Mode Setting */
+ A(4, 2), 0x6b, 0x5f,
+ A(0, 0)
+};
+
+static u8 A030JN01_display_UPS051_init_cmds[] = {
+ A(5, 1), 0x5f,
+ A(0, 0)
+};
+
+static u8 A030JN01_display_on_cmds[] = {
+ A(0, 0)
+};
+
+/* *************************************************** */
+
+static iomux_v3_cfg_t const KD024FM_spi_pads[] = {
+#define GP_KD024FM_CS IMX_GPIO_NR(5, 13)
+ IOMUX_PAD_CTRL(DISP0_DAT19__GPIO5_IO13, WEAK_PULLUP), /* Pin 8 CS */
+#define GP_KD024FM_IM2 IMX_GPIO_NR(5, 17)
+ IOMUX_PAD_CTRL(DISP0_DAT23__GPIO5_IO17, WEAK_PULLUP),
+#define GP_KD024FM_IM1 IMX_GPIO_NR(5, 16)
+ IOMUX_PAD_CTRL(DISP0_DAT22__GPIO5_IO16, WEAK_PULLUP),
+#define GP_KD024FM_IM0 IMX_GPIO_NR(5, 15)
+ IOMUX_PAD_CTRL(DISP0_DAT21__GPIO5_IO15, WEAK_PULLDN),
+#define GP_KD024FM_RESET IMX_GPIO_NR(5, 14)
+ IOMUX_PAD_CTRL(DISP0_DAT20__GPIO5_IO14, WEAK_PULLDN),
+#define GP_KD024FM_RS IMX_GPIO_NR(4, 25)
+ IOMUX_PAD_CTRL(DISP0_DAT4__GPIO4_IO25, WEAK_PULLUP), /* Pin 10 RS ** */
+ IOMUX_PAD_CTRL(DISP0_DAT0__ECSPI3_SCLK, WEAK_PULLUP), /* Pin 9 SCL */
+ IOMUX_PAD_CTRL(DISP0_DAT1__ECSPI3_MOSI, WEAK_PULLUP), /* Pin 16 SDA1 */
+ IOMUX_PAD_CTRL(DISP0_DAT2__ECSPI3_MISO, WEAK_PULLUP), /* Pin 35 SDO */
+#define GP_KD024FM_PCLK IMX_GPIO_NR(4, 16)
+ IOMUX_PAD_CTRL(DI0_DISP_CLK__GPIO4_IO16, WEAK_PULLUP),
+#define GP_KD024FM_HSYNC IMX_GPIO_NR(4, 18)
+ IOMUX_PAD_CTRL(DI0_PIN2__GPIO4_IO18, WEAK_PULLUP), /* HSYNC */
+#define GP_KD024FM_VSYNC IMX_GPIO_NR(4, 19)
+ IOMUX_PAD_CTRL(DI0_PIN3__GPIO4_IO19, WEAK_PULLUP), /* VSYNC */
+#define GP_KD024FM_DRDY IMX_GPIO_NR(4, 17)
+ IOMUX_PAD_CTRL(DI0_PIN15__GPIO4_IO17, WEAK_PULLUP), /* DRDY */
+};
+
+static iomux_v3_cfg_t const KD024FM_display_pads[] = {
+ IOMUX_PAD_CTRL(DISP0_DAT0__IPU1_DISP0_DATA00, RGB_PAD_CTRL),
+ IOMUX_PAD_CTRL(DISP0_DAT1__IPU1_DISP0_DATA01, RGB_PAD_CTRL),
+ IOMUX_PAD_CTRL(DISP0_DAT2__IPU1_DISP0_DATA02, RGB_PAD_CTRL),
+ IOMUX_PAD_CTRL(DISP0_DAT3__IPU1_DISP0_DATA03, RGB_PAD_CTRL),
+ IOMUX_PAD_CTRL(DISP0_DAT4__IPU1_DISP0_DATA04, RGB_PAD_CTRL),
+ IOMUX_PAD_CTRL(DI0_DISP_CLK__IPU1_DI0_DISP_CLK, RGB_PAD_CTRL),
+ IOMUX_PAD_CTRL(DI0_PIN15__IPU1_DI0_PIN15, RGB_PAD_CTRL), /* DRDY */
+ IOMUX_PAD_CTRL(DI0_PIN2__IPU1_DI0_PIN02, RGB_PAD_CTRL), /* HSYNC */
+ IOMUX_PAD_CTRL(DI0_PIN3__IPU1_DI0_PIN03, RGB_PAD_CTRL), /* VSYNC */
+};
+
+static int KD024FM_spi_write_rtn(struct spi_slave *spi, u8 *cmds)
+{
+ u8 buf[4];
+ int ret = 0;
+
+ while (1) {
+ uint reg = cmds[1];
+ uint len = cmds[2];
+
+ if (!len && !reg)
+ break;
+ cmds += 3;
+ gpio_direction_output(GP_KD024FM_RS, 0);
+ buf[0] = reg;
+ ret = spi_xfer(spi, 1 * 8, buf, NULL, SPI_XFER_BEGIN | SPI_XFER_END);
+ if (ret) {
+ printf("%s: Failed 0x%x, %d\n", __func__, reg, ret);
+ return ret;
+ }
+ if (!len) {
+ debug("spi: reg:%02x\n", reg);
+ continue;
+ }
+
+ gpio_set_value(GP_KD024FM_RS, 1);
+ while (len--) {
+ buf[0] = *cmds++;
+ ret = spi_xfer(spi, 1 * 8, buf, NULL, SPI_XFER_BEGIN | SPI_XFER_END);
+ if (ret) {
+ printf("%s: Failed 0x%x, %d\n", __func__, reg, ret);
+ return ret;
+ }
+ debug("spi: reg:%02x %02x\n", reg, buf[0]);
+ udelay(2);
+ }
+ }
+ return ret;
+}
+
+static int KD024FM_spi_read_rtn(struct spi_slave *spi, int reg)
+{
+ printf("%s: undefined\n", __func__);
+ return 0;
+}
+
+static int KD024FM_spi_setup_rtn(struct spi_display_info *di)
+{
+ gpio_direction_output(di->cs_gpio, 1);
+ gpio_direction_output(GP_KD024FM_IM2, 1);
+ gpio_direction_output(GP_KD024FM_IM1, 1);
+ gpio_direction_output(GP_KD024FM_IM0, 0);
+ gpio_direction_output(di->reset_gpio, 1);
+ gpio_direction_output(GP_KD024FM_RS, 0);
+ gpio_direction_output(GP_KD024FM_HSYNC, 1);
+ gpio_direction_output(GP_KD024FM_VSYNC, 1);
+ gpio_direction_output(GP_KD024FM_DRDY, 1);
+ gpio_direction_output(GP_KD024FM_PCLK, 1);
+ SETUP_IOMUX_PADS(KD024FM_spi_pads);
+ return 0;
+}
+
+static int KD024FM_spi_exit_rtn(struct spi_display_info *di)
+{
+ SETUP_IOMUX_PADS(KD024FM_display_pads);
+ return 0;
+}
+
+
+static u8 KD024FM_display_init_cmds[] = {
+ A(0x3a, 1), 0x05, /* ST7789S Frame rate setting */
+ A(0x36, 1), 0x00,
+ A(0xb2, 5), 0x00, 0x00, 0x00, 0x33, 0x33,
+ A(0xb7, 1), 0x35,
+ A(0xb8, 3), 0x2f, 0x2b, 0x2f, /* ST7789S Power setting */
+ A(0xbb, 1), 0x24,
+ A(0xc0, 1), 0x2c,
+ A(0xc3, 1), 0x10,
+ A(0xc4, 1), 0x20,
+ A(0xc6, 1), 0x11,
+ A(0xd0, 2), 0xa4, 0xa1,
+ A(0xe8, 1), 0x03,
+ A(0xe9, 3), 0x0d, 0x12, 0x00,
+ /* ST7789S gamma setting */
+ A(0xe0, 14), 0xd0, 0x00, 0x00, 0x08, 0x11, 0x1a, 0x2b, 0x33, 0x42, 0x26, 0x12, 0x21, 0x2f, 0x11,
+ A(0xe1, 14), 0xd0, 0x02, 0x09, 0x0d, 0x0d, 0x27, 0x2b, 0x33, 0x42, 0x17, 0x12, 0x11, 0x2f, 0x31,
+ A(0x21, 0),
+ /* SET RGB Interface */
+ A(0xb0, 3), 0x11, 0x00, 0x00,
+ /* set DE mode ; SET Hs,Vs,DE,DOTCLK signal polarity */
+ A(0xb1, 3), 0xc0, 0x08, 0x14,
+ A(0x3a, 1), 0x88, /* 18 Bit RGB, 0x55 means 16 Bit RGB */
+ A(0x11, 0),
+ A(0, 0)
+};
+
+static u8 KD024FM_display_on_cmds[] = {
+ A(0x29, 0),
+ A(0x2c, 0),
+ A(0, 0)
+};
+
+struct spi_display_info spi_di[] = {
+ { .mode = SPI_MODE_0, .speed_r = 10000, .speed_w = 1000000, .reset_active_low = 1,
+ .cs_gpio = GP_ECSPI2_CS, .reset_gpio = GP_SPI_DISPLAY_RESET,
+ .init_cmds = AUO_G050_display_init_cmds, .on_cmds = AUO_G050_display_on_cmds,
+ .spi_mosi_r_pads = spi_mosi_r_pads,
+ .spi_mosi_w_pads = spi_mosi_w_pads,
+ .spi_ss0_pad = spi_ss0_pad,
+ .spi_ss0_gpio_pad = spi_ss0_gpio_pad,
+ .spi_write_rtn = AUO_G050_spi_write_rtn, .spi_read_rtn = AUO_G050_spi_read_rtn},
+ { .mode = SPI_MODE_3, .speed_r = 10000, .speed_w = 10000, .reset_active_low = 1,
+ .cs_gpio = GP_ECSPI2_CS, .reset_gpio = GP_SPI_DISPLAY_RESET,
+ .init_cmds = A030JN01_display_YUV720_init_cmds, .on_cmds = A030JN01_display_on_cmds,
+ .spi_mosi_r_pads = spi_mosi_r_pads,
+ .spi_mosi_w_pads = spi_mosi_w_pads,
+ .spi_ss0_pad = spi_ss0_pad,
+ .spi_ss0_gpio_pad = spi_ss0_gpio_pad,
+ .spi_write_rtn = A030JN01_spi_write_rtn, .spi_read_rtn = A030JN01_spi_read_rtn},
+ { .mode = SPI_MODE_3, .speed_r = 10000, .speed_w = 10000, .reset_active_low = 1,
+ .cs_gpio = GP_ECSPI2_CS, .reset_gpio = GP_SPI_DISPLAY_RESET,
+ .init_cmds = A030JN01_display_UPS051_init_cmds, .on_cmds = A030JN01_display_on_cmds,
+ .spi_mosi_r_pads = spi_mosi_r_pads,
+ .spi_mosi_w_pads = spi_mosi_w_pads,
+ .spi_ss0_pad = spi_ss0_pad,
+ .spi_ss0_gpio_pad = spi_ss0_gpio_pad,
+ .spi_write_rtn = A030JN01_spi_write_rtn, .spi_read_rtn = A030JN01_spi_read_rtn},
+ { .mode = SPI_MODE_0, .speed_r = 10000, .speed_w = 10000, .reset_active_low = 1,
+ .cs_gpio = GP_KD024FM_CS, .reset_gpio = GP_KD024FM_RESET,
+ .init_cmds = KD024FM_display_init_cmds, .on_cmds = KD024FM_display_on_cmds,
+ .spi_write_rtn = KD024FM_spi_write_rtn, .spi_read_rtn = KD024FM_spi_read_rtn,
+ .spi_setup_rtn = KD024FM_spi_setup_rtn, .spi_exit_rtn = KD024FM_spi_exit_rtn},
+};
+
+const struct display_info_t *g_dev;
+
+/*
+ * Return 1 for successful detection of display
+ */
+int detect_spi(struct display_info_t const *dev)
+{
+ return 1;
+}
+
+static void init_spi(struct display_info_t const *dev)
+{
+ struct spi_display_info *di = &spi_di[dev->addr];
+ unsigned reset_gpio = di->reset_gpio;
+ int reset_val = di->reset_active_low ? 0 : 1;
+
+ debug("%s\n", __func__);
+ gpio_direction_output(di->cs_gpio, 1);
+ gpio_direction_output(reset_gpio, reset_val ^ 1);
+ gpio_direction_output(reset_gpio, reset_val);
+ udelay(200);
+ gpio_direction_output(reset_gpio, reset_val ^ 1);
+ mdelay(200);
+}
+
+void enable_spi_rgb(struct display_info_t const *dev)
+{
+ struct spi_display_info *di = &spi_di[dev->addr];
+ struct spi_slave *spi;
+ int ret;
+
+ g_dev = dev;
+ if (di->spi_setup_rtn)
+ di->spi_setup_rtn(di);
+ init_spi(dev);
+ gpio_direction_output(di->cs_gpio, 1);
+ if (di->spi_mosi_w_pads)
+ SETUP_IOMUX_PADS(di->spi_mosi_w_pads);
+
+ enable_spi_clk(1, dev->bus);
+
+ /* Setup spi_slave */
+ spi = spi_setup_slave(dev->bus, di->spi_ss0_pad ? 0 : di->cs_gpio << 8,
+ di->speed_w, di->mode);
+ if (!spi) {
+ printf("%s: Failed to set up slave\n", __func__);
+ return;
+ }
+
+ /* Claim spi bus */
+ ret = spi_claim_bus(spi);
+ if (ret) {
+ debug("%s: Failed to claim SPI bus: %d\n", __func__, ret);
+ goto free_bus;
+ }
+
+ /*
+ * Initialization sequence
+ * 1. Display Mode Settings
+ * 2. Power Settings
+ * 3. Gamma Settings
+ * 4. Sleep Out
+ * 5. Wait >= 7 frame
+ * 6. Display on
+ */
+ if (di->spi_ss0_pad)
+ SETUP_IOMUX_PADS(di->spi_ss0_pad);
+ ret = di->spi_write_rtn(spi, di->init_cmds);
+ if (ret) {
+ printf("%s: Failed to display_init_cmds %d\n", __func__, ret);
+ goto release_bus;
+ }
+ mdelay(200);
+ ret = di->spi_write_rtn(spi, di->on_cmds);
+ if (ret) {
+ printf("%s: Failed to display_on_cmds %d\n", __func__, ret);
+ goto release_bus;
+ }
+ ret = 1;
+ if (di->spi_ss0_gpio_pad)
+ SETUP_IOMUX_PADS(di->spi_ss0_gpio_pad);
+
+ /* Release spi bus */
+release_bus:
+ spi_release_bus(spi);
+free_bus:
+ spi_free_slave(spi);
+ enable_spi_clk(0, dev->bus);
+ if (di->spi_exit_rtn)
+ di->spi_exit_rtn(di);
+ return;
+}
+
+static int do_spid(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ struct spi_slave *spi;
+ int display_index = g_dev ? g_dev->addr : 0;
+ int bus = g_dev ? g_dev->bus : 1;
+ struct spi_display_info *di = &spi_di[display_index];
+ int ret = 0;
+ int arg = 2;
+ uint reg;
+ u8 buf[80];
+
+ if (argc < 2)
+ return 1;
+ if (di->spi_setup_rtn)
+ di->spi_setup_rtn(di);
+ gpio_direction_output(di->cs_gpio, 1);
+ if (di->spi_mosi_w_pads)
+ SETUP_IOMUX_PADS(di->spi_mosi_w_pads);
+
+ enable_spi_clk(1, bus);
+
+ /* Setup spi_slave */
+ spi = spi_setup_slave(bus, di->spi_ss0_pad ? 0 : di->cs_gpio << 8,
+ di->speed_w, di->mode);
+ if (!spi) {
+ printf("%s: Failed to set up slave\n", __func__);
+ return 1;
+ }
+
+ /* Claim spi bus */
+ ret = spi_claim_bus(spi);
+ if (ret) {
+ debug("%s: Failed to claim SPI bus: %d\n", __func__, ret);
+ goto free_bus;
+ }
+
+ if (argc > ARRAY_SIZE(buf) - 3)
+ argc = ARRAY_SIZE(buf) - 3;
+
+ reg = simple_strtoul(argv[1], NULL, 16);
+ buf[0] = reg >> 8;
+ buf[1] = reg;
+ buf[2] = argc - arg;
+ while (arg < argc) {
+ buf[arg + 1] = simple_strtoul(argv[arg], NULL, 16);
+ arg++;
+ }
+ arg++;
+ buf[arg++] = 0;
+ buf[arg++] = 0;
+ buf[arg++] = 0;
+ if (di->spi_ss0_pad)
+ SETUP_IOMUX_PADS(di->spi_ss0_pad);
+ di->spi_write_rtn(spi, buf);
+ if (di->spi_ss0_gpio_pad)
+ SETUP_IOMUX_PADS(di->spi_ss0_gpio_pad);
+ spi_release_bus(spi);
+free_bus:
+ if (di->spi_exit_rtn)
+ di->spi_exit_rtn(di);
+ spi_free_slave(spi);
+ enable_spi_clk(0, bus);
+ return ret ? 1 : 0;
+}
+
+U_BOOT_CMD(
+ spid, 70, 0, do_spid,
+ "write cmd, data to spi display",
+ "reg16 [byte]"
+);
+
+static int do_spidr(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ struct spi_slave *spi;
+ int display_index = g_dev ? g_dev->addr : 0;
+ int bus = g_dev ? g_dev->bus : 1;
+ struct spi_display_info *di = &spi_di[display_index];
+ int ret = 0;
+ uint reg;
+ int val;
+
+ if (argc != 2)
+ return CMD_RET_USAGE;
+ if (di->spi_setup_rtn)
+ di->spi_setup_rtn(di);
+ gpio_direction_output(di->cs_gpio, 1);
+ if (di->spi_mosi_r_pads)
+ SETUP_IOMUX_PADS(di->spi_mosi_r_pads);
+
+ enable_spi_clk(1, bus);
+
+ /* Setup spi_slave */
+ spi = spi_setup_slave(bus, di->spi_ss0_pad ? 0 : di->cs_gpio << 8, di->speed_r, di->mode);
+ if (!spi) {
+ printf("%s: Failed to set up slave\n", __func__);
+ return 1;
+ }
+
+ /* Claim spi bus */
+ ret = spi_claim_bus(spi);
+ if (ret) {
+ debug("%s: Failed to claim SPI bus: %d\n", __func__, ret);
+ goto free_bus;
+ }
+
+ reg = simple_strtoul(argv[1], NULL, 16);
+ if (di->spi_ss0_pad)
+ SETUP_IOMUX_PADS(di->spi_ss0_pad);
+ val = di->spi_read_rtn(spi, reg);
+ if (di->spi_ss0_gpio_pad)
+ SETUP_IOMUX_PADS(di->spi_ss0_gpio_pad);
+ printf("spidr: reg:0x%x = 0x%x\n", reg, val);
+ spi_release_bus(spi);
+free_bus:
+ if (di->spi_exit_rtn)
+ di->spi_exit_rtn(di);
+ spi_free_slave(spi);
+ enable_spi_clk(0, bus);
+ return ret ? 1 : 0;
+}
+
+U_BOOT_CMD(
+ spidr, 70, 0, do_spidr,
+ "read spi display register",
+ "reg16"
+);
diff --git a/board/boundary/nitrogen6x/spi_display.h b/board/boundary/nitrogen6x/spi_display.h
new file mode 100644
index 0000000000000000000000000000000000000000..e59275d3f2cc16b030f729d1e3a1797917ca54c8
--- /dev/null
+++ b/board/boundary/nitrogen6x/spi_display.h
@@ -0,0 +1,2 @@
+int detect_spi(struct display_info_t const *dev);
+void enable_spi_rgb(struct display_info_t const *dev);
diff --git a/configs/mx6qsabrelite_defconfig b/configs/mx6qsabrelite_defconfig
index 380c1cd2b634a5c4108ff386af6811ecab5435c5..5adc2c434490e41d3ede54f9c98fc6eb1f3000e9 100644
--- a/configs/mx6qsabrelite_defconfig
+++ b/configs/mx6qsabrelite_defconfig
@@ -4,13 +4,14 @@ CONFIG_SYS_TEXT_BASE=0x17800000
CONFIG_TARGET_NITROGEN6X=y
CONFIG_CMD_HDMIDETECT=y
CONFIG_DISTRO_DEFAULTS=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q.cfg,MX6Q,DDR_MB=1024,SABRELITE"
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q.cfg,MX6Q,DDR_MB=1024,SABRELITE,DEFCONFIG=\"mx6qsabrelite\""
CONFIG_BOOTDELAY=3
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_CMD_MEMTEST=y
CONFIG_SYS_ALT_MEMTEST=y
+CONFIG_CMD_DFU=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
@@ -26,18 +27,26 @@ CONFIG_CMD_CACHE=y
CONFIG_CMD_TIME=y
CONFIG_CMD_EXT4_WRITE=y
# CONFIG_ISO_PARTITION is not set
+CONFIG_PARTITION_TYPE_GUID=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_DM=y
CONFIG_DWC_AHSATA=y
CONFIG_USB_FUNCTION_FASTBOOT=y
CONFIG_FASTBOOT_BUF_ADDR=0x12000000
+CONFIG_FASTBOOT_BUF_SIZE=0x26000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=1
CONFIG_FSL_ESDHC=y
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_SST=y
CONFIG_PHYLIB=y
+CONFIG_PHY_ATHEROS=y
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
CONFIG_NETDEVICES=y
+CONFIG_FEC_MXC=y
CONFIG_SPI=y
CONFIG_MXC_SPI=y
CONFIG_DM_THERMAL=y
diff --git a/configs/nitrogen6_lum_dl1_defconfig b/configs/nitrogen6_lum_dl1_defconfig
new file mode 100644
index 0000000000000000000000000000000000000000..0b4ab8b71e2630d7ef9efc3215e8159ae9280020
--- /dev/null
+++ b/configs/nitrogen6_lum_dl1_defconfig
@@ -0,0 +1,71 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_SYS_TEXT_BASE=0x17800000
+CONFIG_TARGET_NITROGEN6X=y
+CONFIG_CMD_HDMIDETECT=y
+CONFIG_ENV_VARS_UBOOT_CONFIG=y
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6dl.cfg,MX6DL,DDR_MB=1024,BOARD_TYPE=\"nitrogen6x\",DEFCONFIG=\"nitrogen6_lum_dl1\""
+CONFIG_BOOTDELAY=3
+CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
+CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_SYS_ALT_MEMTEST=y
+CONFIG_CMD_DFU=y
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+# CONFIG_RANDOM_UUID is not set
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PART=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_BMP=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_PARTITION_TYPE_GUID=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x12000000
+CONFIG_FASTBOOT_BUF_SIZE=0x26000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=1
+CONFIG_FSL_ESDHC=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_SST=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_PHY_MICREL=y
+CONFIG_PHY_MICREL_KSZ90X1=y
+CONFIG_NETDEVICES=y
+CONFIG_FEC_MXC=y
+CONFIG_SPI=y
+CONFIG_MXC_SPI=y
+CONFIG_USB=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_KEYBOARD=y
+CONFIG_SYS_USB_EVENT_POLL_VIA_CONTROL_EP=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="Boundary"
+CONFIG_USB_GADGET_VENDOR_NUM=0x0525
+CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
+CONFIG_CI_UDC=y
+CONFIG_USB_ETHER=y
+CONFIG_USB_ETH_CDC=y
+CONFIG_VIDEO=y
+# CONFIG_VIDEO_SW_CURSOR is not set
+CONFIG_OF_LIBFDT=y
diff --git a/configs/nitrogen6dl2g_defconfig b/configs/nitrogen6dl2g_defconfig
index 378fc245de502af4eefcb065df67192a693d8ce1..694a26af5bcde965c850df255c553191df79c6f4 100644
--- a/configs/nitrogen6dl2g_defconfig
+++ b/configs/nitrogen6dl2g_defconfig
@@ -3,7 +3,8 @@ CONFIG_ARCH_MX6=y
CONFIG_SYS_TEXT_BASE=0x17800000
CONFIG_TARGET_NITROGEN6X=y
CONFIG_CMD_HDMIDETECT=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6dl2g.cfg,MX6DL,DDR_MB=2048"
+CONFIG_ENV_VARS_UBOOT_CONFIG=y
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6dl2g.cfg,MX6DL,DDR_MB=2048,DEFCONFIG=\"nitrogen6dl2g\""
CONFIG_BOOTDELAY=3
CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
CONFIG_SUPPORT_RAW_INITRD=y
@@ -12,10 +13,14 @@ CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_MEMTEST=y
CONFIG_SYS_ALT_MEMTEST=y
+CONFIG_CMD_DFU=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+# CONFIG_RANDOM_UUID is not set
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_PART=y
CONFIG_CMD_SF=y
CONFIG_CMD_USB=y
CONFIG_CMD_USB_MASS_STORAGE=y
@@ -30,16 +35,24 @@ CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_PARTITION_TYPE_GUID=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_USB_FUNCTION_FASTBOOT=y
CONFIG_FASTBOOT_BUF_ADDR=0x12000000
+CONFIG_FASTBOOT_BUF_SIZE=0x26000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=1
CONFIG_FSL_ESDHC=y
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_SST=y
CONFIG_PHYLIB=y
+CONFIG_PHY_ATHEROS=y
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
CONFIG_NETDEVICES=y
+CONFIG_FEC_MXC=y
CONFIG_SPI=y
CONFIG_MXC_SPI=y
CONFIG_USB=y
diff --git a/configs/nitrogen6dl_defconfig b/configs/nitrogen6dl_defconfig
index 306bf2e90c64029383f36538a2bbb5214bf09b74..3024830071620e50915d6141cca4574cd856bd08 100644
--- a/configs/nitrogen6dl_defconfig
+++ b/configs/nitrogen6dl_defconfig
@@ -3,7 +3,8 @@ CONFIG_ARCH_MX6=y
CONFIG_SYS_TEXT_BASE=0x17800000
CONFIG_TARGET_NITROGEN6X=y
CONFIG_CMD_HDMIDETECT=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6dl.cfg,MX6DL,DDR_MB=1024"
+CONFIG_ENV_VARS_UBOOT_CONFIG=y
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6dl.cfg,MX6DL,DDR_MB=1024,DEFCONFIG=\"nitrogen6dl\""
CONFIG_BOOTDELAY=3
CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
CONFIG_SUPPORT_RAW_INITRD=y
@@ -12,10 +13,14 @@ CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_MEMTEST=y
CONFIG_SYS_ALT_MEMTEST=y
+CONFIG_CMD_DFU=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+# CONFIG_RANDOM_UUID is not set
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_PART=y
CONFIG_CMD_SF=y
CONFIG_CMD_USB=y
CONFIG_CMD_USB_MASS_STORAGE=y
@@ -30,16 +35,24 @@ CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_PARTITION_TYPE_GUID=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_USB_FUNCTION_FASTBOOT=y
CONFIG_FASTBOOT_BUF_ADDR=0x12000000
+CONFIG_FASTBOOT_BUF_SIZE=0x26000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=1
CONFIG_FSL_ESDHC=y
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_SST=y
CONFIG_PHYLIB=y
+CONFIG_PHY_ATHEROS=y
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
CONFIG_NETDEVICES=y
+CONFIG_FEC_MXC=y
CONFIG_SPI=y
CONFIG_MXC_SPI=y
CONFIG_USB=y
diff --git a/configs/nitrogen6q2g_defconfig b/configs/nitrogen6q2g_defconfig
index ec4e38f000576a9c6779717e5e9aade4df819603..1676ee1742320c7a95fc457c1d0486b022ac8f7c 100644
--- a/configs/nitrogen6q2g_defconfig
+++ b/configs/nitrogen6q2g_defconfig
@@ -3,7 +3,8 @@ CONFIG_ARCH_MX6=y
CONFIG_SYS_TEXT_BASE=0x17800000
CONFIG_TARGET_NITROGEN6X=y
CONFIG_CMD_HDMIDETECT=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q2g.cfg,MX6Q,DDR_MB=2048"
+CONFIG_ENV_VARS_UBOOT_CONFIG=y
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q2g.cfg,MX6Q,DDR_MB=2048,DEFCONFIG=\"nitrogen6q2g\""
CONFIG_BOOTDELAY=3
CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
CONFIG_SUPPORT_RAW_INITRD=y
@@ -12,10 +13,14 @@ CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_MEMTEST=y
CONFIG_SYS_ALT_MEMTEST=y
+CONFIG_CMD_DFU=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+# CONFIG_RANDOM_UUID is not set
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_PART=y
CONFIG_CMD_SATA=y
CONFIG_CMD_SF=y
CONFIG_CMD_USB=y
@@ -31,17 +36,25 @@ CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_PARTITION_TYPE_GUID=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_DWC_AHSATA=y
CONFIG_USB_FUNCTION_FASTBOOT=y
CONFIG_FASTBOOT_BUF_ADDR=0x12000000
+CONFIG_FASTBOOT_BUF_SIZE=0x26000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=1
CONFIG_FSL_ESDHC=y
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_SST=y
CONFIG_PHYLIB=y
+CONFIG_PHY_ATHEROS=y
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
CONFIG_NETDEVICES=y
+CONFIG_FEC_MXC=y
CONFIG_SPI=y
CONFIG_MXC_SPI=y
CONFIG_USB=y
diff --git a/configs/nitrogen6q_defconfig b/configs/nitrogen6q_defconfig
index c8da96e1f5744ac283c3efc156950952bbd8c062..6a11486c2a7ef938ec6261ed915b145bc1dffdb2 100644
--- a/configs/nitrogen6q_defconfig
+++ b/configs/nitrogen6q_defconfig
@@ -3,7 +3,8 @@ CONFIG_ARCH_MX6=y
CONFIG_SYS_TEXT_BASE=0x17800000
CONFIG_TARGET_NITROGEN6X=y
CONFIG_CMD_HDMIDETECT=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q.cfg,MX6Q,DDR_MB=1024"
+CONFIG_ENV_VARS_UBOOT_CONFIG=y
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q.cfg,MX6Q,DDR_MB=1024,DEFCONFIG=\"nitrogen6q\""
CONFIG_BOOTDELAY=3
CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
CONFIG_SUPPORT_RAW_INITRD=y
@@ -12,10 +13,14 @@ CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_MEMTEST=y
CONFIG_SYS_ALT_MEMTEST=y
+CONFIG_CMD_DFU=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+# CONFIG_RANDOM_UUID is not set
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_PART=y
CONFIG_CMD_SATA=y
CONFIG_CMD_SF=y
CONFIG_CMD_USB=y
@@ -31,17 +36,25 @@ CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_PARTITION_TYPE_GUID=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_DWC_AHSATA=y
CONFIG_USB_FUNCTION_FASTBOOT=y
CONFIG_FASTBOOT_BUF_ADDR=0x12000000
+CONFIG_FASTBOOT_BUF_SIZE=0x26000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=1
CONFIG_FSL_ESDHC=y
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_SST=y
CONFIG_PHYLIB=y
+CONFIG_PHY_ATHEROS=y
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
CONFIG_NETDEVICES=y
+CONFIG_FEC_MXC=y
CONFIG_SPI=y
CONFIG_MXC_SPI=y
CONFIG_USB=y
diff --git a/configs/nitrogen6q_fl_defconfig b/configs/nitrogen6q_fl_defconfig
new file mode 100644
index 0000000000000000000000000000000000000000..fc7f7e1512f3a9ab3ed92482f80a42fbc1ff7bce
--- /dev/null
+++ b/configs/nitrogen6q_fl_defconfig
@@ -0,0 +1,73 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_SYS_TEXT_BASE=0x17800000
+CONFIG_TARGET_NITROGEN6X=y
+CONFIG_CMD_HDMIDETECT=y
+CONFIG_ENV_VARS_UBOOT_CONFIG=y
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q.cfg,MX6Q,DDR_MB=1024,BOARD_TYPE=\"nitrogen6x_fl\",DEFCONFIG=\"nitrogen6q_fl\""
+CONFIG_BOOTDELAY=3
+CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
+CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_SYS_ALT_MEMTEST=y
+CONFIG_CMD_DFU=y
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+# CONFIG_RANDOM_UUID is not set
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PART=y
+CONFIG_CMD_SATA=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_BMP=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_PARTITION_TYPE_GUID=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_DWC_AHSATA=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x12000000
+CONFIG_FASTBOOT_BUF_SIZE=0x26000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=1
+CONFIG_FSL_ESDHC=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_SST=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_PHY_MICREL=y
+CONFIG_PHY_MICREL_KSZ90X1=y
+CONFIG_NETDEVICES=y
+CONFIG_FEC_MXC=y
+CONFIG_SPI=y
+CONFIG_MXC_SPI=y
+CONFIG_USB=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_KEYBOARD=y
+CONFIG_SYS_USB_EVENT_POLL_VIA_CONTROL_EP=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="Boundary"
+CONFIG_USB_GADGET_VENDOR_NUM=0x0525
+CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
+CONFIG_CI_UDC=y
+CONFIG_USB_ETHER=y
+CONFIG_USB_ETH_CDC=y
+CONFIG_VIDEO=y
+# CONFIG_VIDEO_SW_CURSOR is not set
+CONFIG_OF_LIBFDT=y
diff --git a/configs/nitrogen6s1g_defconfig b/configs/nitrogen6s1g_defconfig
index 70ffc9d7974cf00fe3a45c5b6bbc4d42e498e531..ec55017bf088ced774cafd5037314f472c48453c 100644
--- a/configs/nitrogen6s1g_defconfig
+++ b/configs/nitrogen6s1g_defconfig
@@ -3,7 +3,8 @@ CONFIG_ARCH_MX6=y
CONFIG_SYS_TEXT_BASE=0x17800000
CONFIG_TARGET_NITROGEN6X=y
CONFIG_CMD_HDMIDETECT=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6s1g.cfg,MX6S,DDR_MB=1024"
+CONFIG_ENV_VARS_UBOOT_CONFIG=y
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6s1g.cfg,MX6S,DDR_MB=1024,DEFCONFIG=\"nitrogen6s1g\""
CONFIG_BOOTDELAY=3
CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
CONFIG_SUPPORT_RAW_INITRD=y
@@ -12,10 +13,14 @@ CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_MEMTEST=y
CONFIG_SYS_ALT_MEMTEST=y
+CONFIG_CMD_DFU=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+# CONFIG_RANDOM_UUID is not set
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_PART=y
CONFIG_CMD_SF=y
CONFIG_CMD_USB=y
CONFIG_CMD_USB_MASS_STORAGE=y
@@ -30,16 +35,24 @@ CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_PARTITION_TYPE_GUID=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_USB_FUNCTION_FASTBOOT=y
CONFIG_FASTBOOT_BUF_ADDR=0x12000000
+CONFIG_FASTBOOT_BUF_SIZE=0x26000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=1
CONFIG_FSL_ESDHC=y
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_SST=y
CONFIG_PHYLIB=y
+CONFIG_PHY_ATHEROS=y
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
CONFIG_NETDEVICES=y
+CONFIG_FEC_MXC=y
CONFIG_SPI=y
CONFIG_MXC_SPI=y
CONFIG_USB=y
diff --git a/configs/nitrogen6s_defconfig b/configs/nitrogen6s_defconfig
index d3fdd6df9306dc151a0e2bb4d9b0451079c01bee..7467a9807c6bd75aa85d032d9e09ca942e30c5e1 100644
--- a/configs/nitrogen6s_defconfig
+++ b/configs/nitrogen6s_defconfig
@@ -3,7 +3,8 @@ CONFIG_ARCH_MX6=y
CONFIG_SYS_TEXT_BASE=0x17800000
CONFIG_TARGET_NITROGEN6X=y
CONFIG_CMD_HDMIDETECT=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6s.cfg,MX6S,DDR_MB=512"
+CONFIG_ENV_VARS_UBOOT_CONFIG=y
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6s.cfg,MX6S,DDR_MB=512,DEFCONFIG=\"nitrogen6s\""
CONFIG_BOOTDELAY=3
CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
CONFIG_SUPPORT_RAW_INITRD=y
@@ -12,10 +13,14 @@ CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_MEMTEST=y
CONFIG_SYS_ALT_MEMTEST=y
+CONFIG_CMD_DFU=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+# CONFIG_RANDOM_UUID is not set
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_PART=y
CONFIG_CMD_SF=y
CONFIG_CMD_USB=y
CONFIG_CMD_USB_MASS_STORAGE=y
@@ -30,16 +35,24 @@ CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_PARTITION_TYPE_GUID=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_USB_FUNCTION_FASTBOOT=y
CONFIG_FASTBOOT_BUF_ADDR=0x12000000
+CONFIG_FASTBOOT_BUF_SIZE=0x26000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=1
CONFIG_FSL_ESDHC=y
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_SST=y
CONFIG_PHYLIB=y
+CONFIG_PHY_ATHEROS=y
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
CONFIG_NETDEVICES=y
+CONFIG_FEC_MXC=y
CONFIG_SPI=y
CONFIG_MXC_SPI=y
CONFIG_USB=y
diff --git a/include/configs/nitrogen6x.h b/include/configs/nitrogen6x.h
index 4e375d88d1dfb704640d11e951ffe69e993f1dfa..62708b839bda68788e526280a05e4f6068253ccf 100644
--- a/include/configs/nitrogen6x.h
+++ b/include/configs/nitrogen6x.h
@@ -10,122 +10,25 @@
#define __CONFIG_H
#include "mx6_common.h"
-
-#define CONFIG_MACH_TYPE 3769
-
-/* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
-
-#define CONFIG_MISC_INIT_R
-#define CONFIG_USBD_HS
-#define CONFIG_NETCONSOLE
-
-#define CONFIG_MXC_UART
-#define CONFIG_MXC_UART_BASE UART2_BASE
-
-#ifdef CONFIG_CMD_SF
-#define CONFIG_SF_DEFAULT_BUS 0
-#define CONFIG_SF_DEFAULT_CS 0
-#define CONFIG_SF_DEFAULT_SPEED 25000000
-#define CONFIG_SF_DEFAULT_MODE (SPI_MODE_0)
-#endif
-
-/* I2C Configs */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_MXC
-#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
-#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
-#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
-#define CONFIG_SYS_I2C_SPEED 100000
-#define CONFIG_I2C_EDID
-
-/* MMC Configs */
-#define CONFIG_SYS_FSL_ESDHC_ADDR 0
-#define CONFIG_SYS_FSL_USDHC_NUM 2
-
-/*
- * SATA Configs
- */
-#ifdef CONFIG_CMD_SATA
-#define CONFIG_SYS_SATA_MAX_DEVICE 1
-#define CONFIG_DWC_AHSATA_PORT_ID 0
-#define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR
-#define CONFIG_LBA48
+#ifndef CONFIG_BOARD_TYPE
+#undef CONFIG_SYS_BOARD
#endif
-#define CONFIG_FEC_MXC
-#define CONFIG_MII
-#define IMX_FEC_BASE ENET_BASE_ADDR
-#define CONFIG_FEC_XCV_TYPE RGMII
-#define CONFIG_ETHPRIME "FEC"
-#define CONFIG_FEC_MXC_PHYADDR 6
+#define CONFIG_MACH_TYPE 3769
-/* USB Configs */
-#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
-#define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* For OTG port */
-#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
-#define CONFIG_MXC_USB_FLAGS 0
+#define CONFIG_MXC_SPI_DISPLAY
-/* Framebuffer and LCD */
-#define CONFIG_VIDEO_IPUV3
-#define CONFIG_VIDEO_BMP_RLE8
-#define CONFIG_SPLASH_SCREEN
-#define CONFIG_SPLASH_SCREEN_ALIGN
-#define CONFIG_VIDEO_BMP_GZIP
-#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (6 * 1024 * 1024)
-#define CONFIG_BMP_16BPP
#define CONFIG_IMX_HDMI
-#define CONFIG_IMX_VIDEO_SKIP
-
-#define CONFIG_PREBOOT ""
-
-#ifdef CONFIG_CMD_MMC
-#define DISTRO_BOOT_DEV_MMC(func) func(MMC, mmc, 0) func(MMC, mmc, 1)
-#else
-#define DISTRO_BOOT_DEV_MMC(func)
-#endif
-
-#ifdef CONFIG_CMD_SATA
-#define DISTRO_BOOT_DEV_SATA(func) func(SATA, sata, 0)
-#else
-#define DISTRO_BOOT_DEV_SATA(func)
-#endif
-
-#ifdef CONFIG_USB_STORAGE
-#define DISTRO_BOOT_DEV_USB(func) func(USB, usb, 0)
-#else
-#define DISTRO_BOOT_DEV_USB(func)
-#endif
-
-#ifdef CONFIG_CMD_PXE
-#define DISTRO_BOOT_DEV_PXE(func) func(PXE, pxe, na)
-#else
-#define DISTRO_BOOT_DEV_PXE(func)
-#endif
+/* Sabrelite has different reset pin */
+#define GP_RGMII2_PHY_RESET IMX_GPIO_NR(3, 23)
-#ifdef CONFIG_CMD_DHCP
-#define DISTRO_BOOT_DEV_DHCP(func) func(DHCP, dhcp, na)
-#else
-#define DISTRO_BOOT_DEV_DHCP(func)
-#endif
+#define CONFIG_SYS_FSL_USDHC_NUM 2
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
+#define BD_I2C_MASK 7
#if defined(CONFIG_SABRELITE)
-#define FDTFILE "fdtfile=imx6q-sabrelite.dtb\0"
-#else
-/* FIXME: nitrogen6x covers multiple configs. Define fdtfile for each supported config. */
-#define FDTFILE
-#endif
-
-#define BOOT_TARGET_DEVICES(func) \
- DISTRO_BOOT_DEV_MMC(func) \
- DISTRO_BOOT_DEV_SATA(func) \
- DISTRO_BOOT_DEV_USB(func) \
- DISTRO_BOOT_DEV_PXE(func) \
- DISTRO_BOOT_DEV_DHCP(func)
-
-#include <config_distro_bootcmd.h>
-
+#include "boundary.h"
#define CONFIG_EXTRA_ENV_SETTINGS \
"console=ttymxc1\0" \
"fdt_high=0xffffffff\0" \
@@ -141,45 +44,10 @@
"usb_pgood_delay=2000\0" \
BOOTENV
-/* Miscellaneous configurable options */
-#define CONFIG_SYS_MEMTEST_START 0x10000000
-#define CONFIG_SYS_MEMTEST_END 0x10010000
-#define CONFIG_SYS_MEMTEST_SCRATCH 0x10800000
-
-/* Physical Memory Map */
-#define CONFIG_NR_DRAM_BANKS 1
-#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
-
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
-#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
-
-#define CONFIG_SYS_INIT_SP_OFFSET \
- (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_ADDR \
- (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
-
-/* Environment organization */
-#define CONFIG_ENV_SIZE (8 * 1024)
-
-#if defined(CONFIG_ENV_IS_IN_MMC)
-#define CONFIG_ENV_OFFSET (6 * 64 * 1024)
-#define CONFIG_SYS_MMC_ENV_DEV 0
-#elif defined(CONFIG_ENV_IS_IN_SPI_FLASH)
-#define CONFIG_ENV_OFFSET (768 * 1024)
-#define CONFIG_ENV_SECT_SIZE (8 * 1024)
-#define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS
-#define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS
-#define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE
-#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
-#endif
+#else
+#include "boundary.h"
+#define CONFIG_EXTRA_ENV_SETTINGS BD_BOUNDARY_ENV_SETTINGS \
-/*
- * PCI express
- */
-#ifdef CONFIG_CMD_PCI
-#define CONFIG_PCI_SCAN_SHOW
-#define CONFIG_PCIE_IMX
#endif
#endif /* __CONFIG_H */