From 4f9226b40379847339af8a7777be26f2db72e79b Mon Sep 17 00:00:00 2001 From: Paul Burton <paul.burton@imgtec.com> Date: Wed, 21 Sep 2016 11:18:50 +0100 Subject: [PATCH] MIPS: Preserve Config implementation-defined bits The coprocessor 0 Config register includes 9 implementation defined bits, which in some processors do things like enable write combining or other functionality. We ought not to wipe them to 0 during boot. Rather than doing so, preserve their value & only clear the bits standardised by the MIPS architecture. Signed-off-by: Paul Burton <paul.burton@imgtec.com> --- arch/mips/cpu/start.S | 5 +++-- arch/mips/include/asm/mipsregs.h | 1 + 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/mips/cpu/start.S b/arch/mips/cpu/start.S index 827a5449878..6aec430a670 100644 --- a/arch/mips/cpu/start.S +++ b/arch/mips/cpu/start.S @@ -123,8 +123,9 @@ reset: mtc0 zero, CP0_COMPARE #ifndef CONFIG_SKIP_LOWLEVEL_INIT - /* CONFIG0 register */ - li t0, CONF_CM_UNCACHED + mfc0 t0, CP0_CONFIG + and t0, t0, MIPS_CONF_IMPL + or t0, t0, CONF_CM_UNCACHED mtc0 t0, CP0_CONFIG #endif diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h index 3185dc7abf2..cd4f952df0a 100644 --- a/arch/mips/include/asm/mipsregs.h +++ b/arch/mips/include/asm/mipsregs.h @@ -450,6 +450,7 @@ #define MIPS_CONF_MT_FTLB (_ULCAST_(4) << 7) #define MIPS_CONF_AR (_ULCAST_(7) << 10) #define MIPS_CONF_AT (_ULCAST_(3) << 13) +#define MIPS_CONF_IMPL (_ULCAST_(0x1ff) << 16) #define MIPS_CONF_M (_ULCAST_(1) << 31) /* -- GitLab