diff --git a/arch/arm/include/asm/arch-mx5/iomux-mx51.h b/arch/arm/include/asm/arch-mx5/iomux-mx51.h
index 0090ee7ab12f3a10f470b86c6b304781a583a124..cdbf4f0c19a3a018f7aae4c469884fabbffeb72c 100644
--- a/arch/arm/include/asm/arch-mx5/iomux-mx51.h
+++ b/arch/arm/include/asm/arch-mx5/iomux-mx51.h
@@ -16,6 +16,8 @@
#include <asm/mach-imx/iomux-v3.h>
/* Pad control groupings */
+#define MX51_AUD_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_DSE_HIGH | \
+ PAD_CTL_HYS | PAD_CTL_SRE_FAST)
#define MX51_UART_PAD_CTRL (PAD_CTL_PUS_100K_DOWN | PAD_CTL_DSE_HIGH | \
PAD_CTL_HYS | PAD_CTL_SRE_FAST)
#define MX51_I2C_PAD_CTRL (PAD_CTL_SRE_FAST | PAD_CTL_ODE | \
@@ -42,6 +44,10 @@
* See also iomux-v3.h
*/
+#define IOMUX_P(mux_ctrl_ofs, pad_ctrl_ofs, sel_input_ofs, \
+ mux_mode, sel_input, pad_ctrl) \
+ IOMUX_PAD(pad_ctrl_ofs, mux_ctrl_ofs, mux_mode, \
+ sel_input_ofs, sel_input, pad_ctrl)
/* PAD MUX ALT INPSE PATH PADCTRL */
enum {
MX51_PAD_EIM_D16__GPIO2_0 = IOMUX_PAD(0x3f0, 0x05c, 1, __NA_, 0, MX51_GPIO_PAD_CTRL),
@@ -161,12 +167,58 @@ enum {
MX51_PAD_NANDF_D2__PATA_DATA2 = IOMUX_PAD(0x570, 0x188, 1, __NA_, 0, NO_PAD_CTRL),
MX51_PAD_NANDF_D1__PATA_DATA1 = IOMUX_PAD(0x574, 0x18c, 1, __NA_, 0, NO_PAD_CTRL),
MX51_PAD_NANDF_D0__PATA_DATA0 = IOMUX_PAD(0x578, 0x190, 1, __NA_, 0, NO_PAD_CTRL),
- MX51_PAD_CSI2_D12__GPIO4_9 = IOMUX_PAD(0x5bc, 0x1cc, 3, __NA_, 0, MX51_GPIO_PAD_CTRL),
- MX51_PAD_CSI2_D13__GPIO4_10 = IOMUX_PAD(0x5c0, 0x1d0, 3, __NA_, 0, MX51_GPIO_PAD_CTRL),
+ MX51_PAD_CSI1_D8__CSI1_D8 = IOMUX_P(0x194, 0x57c, __NA_, 0x0, 0x0, 0x0),
+ MX51_PAD_CSI1_D8__GPIO3_12 = IOMUX_P(0x194, 0x57c, 0x998, 0x3, 0x1, MX51_GPIO_PAD_CTRL),
+ MX51_PAD_CSI1_D9__CSI1_D9 = IOMUX_P(0x198, 0x580, __NA_, 0x0, 0x0, 0x0),
+ MX51_PAD_CSI1_D9__GPIO3_13 = IOMUX_P(0x198, 0x580, __NA_, 0x3, 0x0, MX51_GPIO_PAD_CTRL),
+ MX51_PAD_CSI1_D10__CSI1_D10 = IOMUX_P(0x19c, 0x584, __NA_, 0x0, 0x0, 0x0),
+ MX51_PAD_CSI1_D11__CSI1_D11 = IOMUX_P(0x1a0, 0x588, __NA_, 0x0, 0x0, 0x0),
+ MX51_PAD_CSI1_D12__CSI1_D12 = IOMUX_P(0x1a4, 0x58c, __NA_, 0x0, 0x0, 0x0),
+ MX51_PAD_CSI1_D13__CSI1_D13 = IOMUX_P(0x1a8, 0x590, __NA_, 0x0, 0x0, 0x0),
+ MX51_PAD_CSI1_D14__CSI1_D14 = IOMUX_P(0x1ac, 0x594, __NA_, 0x0, 0x0, 0x0),
+ MX51_PAD_CSI1_D15__CSI1_D15 = IOMUX_P(0x1b0, 0x598, __NA_, 0x0, 0x0, 0x0),
+ MX51_PAD_CSI1_D16__CSI1_D16 = IOMUX_P(0x1b4, 0x59c, __NA_, 0x0, 0x0, 0x0),
+ MX51_PAD_CSI1_D17__CSI1_D17 = IOMUX_P(0x1b8, 0x5a0, __NA_, 0x0, 0x0, 0x0),
+ MX51_PAD_CSI1_D18__CSI1_D18 = IOMUX_P(0x1bc, 0x5a4, __NA_, 0x0, 0x0, 0x0),
+ MX51_PAD_CSI1_D19__CSI1_D19 = IOMUX_P(0x1c0, 0x5a8, __NA_, 0x0, 0x0, 0x0),
+ MX51_PAD_CSI1_VSYNC__CSI1_VSYNC = IOMUX_P(0x1c4, 0x5ac, __NA_, 0x0, 0x0, 0x0),
+ MX51_PAD_CSI1_VSYNC__GPIO3_14 = IOMUX_P(0x1c4, 0x5ac, __NA_, 0x3, 0x0, 0x0),
+ MX51_PAD_CSI1_HSYNC__CSI1_HSYNC = IOMUX_P(0x1c8, 0x5b0, __NA_, 0x0, 0x0, 0x0),
+ MX51_PAD_CSI1_HSYNC__GPIO3_15 = IOMUX_P(0x1c8, 0x5b0, __NA_, 0x3, 0x0, 0x0),
+ MX51_PAD_CSI1_PIXCLK__CSI1_PIXCLK = IOMUX_P(__NA_, 0x5b4, __NA_, 0x0, 0x0, 0x0),
+ MX51_PAD_CSI1_MCLK__CSI1_MCLK = IOMUX_P(__NA_, 0x5b8, __NA_, 0x0, 0x0, 0x0),
+ MX51_PAD_CSI2_D12__CSI2_D12 = IOMUX_P(0x1cc, 0x5bc, __NA_, 0x0, 0x0, 0x0),
+ MX51_PAD_CSI2_D12__GPIO4_9 = IOMUX_P(0x1cc, 0x5bc, __NA_, 0x3, 0x0, MX51_GPIO_PAD_CTRL),
+ MX51_PAD_CSI2_D13__CSI2_D13 = IOMUX_P(0x1d0, 0x5c0, __NA_, 0x0, 0x0, 0x0),
+ MX51_PAD_CSI2_D13__GPIO4_10 = IOMUX_P(0x1d0, 0x5c0, __NA_, 0x3, 0x0, MX51_GPIO_PAD_CTRL),
+ MX51_PAD_CSI2_D14__CSI2_D14 = IOMUX_P(0x1d4, 0x5c4, __NA_, 0x0, 0x0, 0x0),
+ MX51_PAD_CSI2_D15__CSI2_D15 = IOMUX_P(0x1d8, 0x5c8, __NA_, 0x0, 0x0, 0x0),
+ MX51_PAD_CSI2_D16__CSI2_D16 = IOMUX_P(0x1dc, 0x5cc, __NA_, 0x0, 0x0, 0x0),
+ MX51_PAD_CSI2_D17__CSI2_D17 = IOMUX_P(0x1e0, 0x5d0, __NA_, 0x0, 0x0, 0x0),
+ MX51_PAD_CSI2_D18__CSI2_D18 = IOMUX_P(0x1e4, 0x5d4, __NA_, 0x0, 0x0, 0x0),
+ MX51_PAD_CSI2_D18__GPIO4_11 = IOMUX_P(0x1e4, 0x5d4, __NA_, 0x3, 0x0, MX51_GPIO_PAD_CTRL),
+ MX51_PAD_CSI2_D19__CSI2_D19 = IOMUX_P(0x1e8, 0x5d8, __NA_, 0x0, 0x0, 0x0),
+ MX51_PAD_CSI2_D19__GPIO4_12 = IOMUX_P(0x1e8, 0x5d8, __NA_, 0x3, 0x0, MX51_GPIO_PAD_CTRL),
+ MX51_PAD_CSI2_VSYNC__CSI2_VSYNC = IOMUX_P(0x1ec, 0x5dc, __NA_, 0x0, 0x0, 0x0),
+ MX51_PAD_CSI2_VSYNC__GPIO4_13 = IOMUX_P(0x1ec, 0x5dc, __NA_, 0x3, 0x0, 0x0),
+ MX51_PAD_CSI2_HSYNC__CSI2_HSYNC = IOMUX_P(0x1f0, 0x5e0, __NA_, 0x0, 0x0, 0x0),
+ MX51_PAD_CSI2_HSYNC__GPIO4_14 = IOMUX_P(0x1f0, 0x5e0, __NA_, 0x3, 0x0, 0x0),
+ MX51_PAD_CSI2_PIXCLK__CSI2_PIXCLK = IOMUX_P(0x1f4, 0x5e4, __NA_, 0x0, 0x0, 0x0),
+ MX51_PAD_CSI2_PIXCLK__GPIO4_15 = IOMUX_P(0x1f4, 0x5e4, __NA_, 0x3, 0x0, 0x0),
MX51_PAD_I2C1_CLK__I2C1_CLK = IOMUX_PAD(0x5e8, 0x1f8, 0x10, __NA_, 0, MX51_I2C_PAD_CTRL),
MX51_PAD_I2C1_CLK__GPIO4_16 = IOMUX_PAD(0x5e8, 0x1f8, 3, __NA_, 0, MX51_GPIO_PAD_CTRL),
MX51_PAD_I2C1_DAT__I2C1_DAT = IOMUX_PAD(0x5ec, 0x1fc, 0x10, __NA_, 0, MX51_I2C_PAD_CTRL),
MX51_PAD_I2C1_DAT__GPIO4_17 = IOMUX_PAD(0x5ec, 0x1fc, 3, __NA_, 0, MX51_GPIO_PAD_CTRL),
+ MX51_PAD_AUD3_BB_TXD__AUD3_TXD = IOMUX_P(0x200, 0x5f0, __NA_, 0x0, 0x0, MX51_AUD_PAD_CTRL),
+ MX51_PAD_AUD3_BB_TXD__GPIO4_18 = IOMUX_P(0x200, 0x5f0, __NA_, 0x3, 0x0, MX51_GPIO_PAD_CTRL),
+ MX51_PAD_AUD3_BB_RXD__AUD3_RXD = IOMUX_P(0x204, 0x5f4, __NA_, 0x0, 0x0, MX51_AUD_PAD_CTRL),
+ MX51_PAD_AUD3_BB_RXD__GPIO4_19 = IOMUX_P(0x204, 0x5f4, __NA_, 0x3, 0x0, MX51_GPIO_PAD_CTRL),
+ MX51_PAD_AUD3_BB_RXD__UART3_RXD = IOMUX_P(0x204, 0x5f4, 0x9f4, 0x1, 0x2, MX51_UART_PAD_CTRL),
+ MX51_PAD_AUD3_BB_CK__AUD3_TXC = IOMUX_P(0x208, 0x5f8, __NA_, 0x0, 0x0, MX51_AUD_PAD_CTRL),
+ MX51_PAD_AUD3_BB_CK__GPIO4_20 = IOMUX_P(0x208, 0x5f8, __NA_, 0x3, 0x0, MX51_GPIO_PAD_CTRL),
+ MX51_PAD_AUD3_BB_FS__AUD3_TXFS = IOMUX_P(0x20c, 0x5fc, __NA_, 0x0, 0x0, MX51_AUD_PAD_CTRL),
+ MX51_PAD_AUD3_BB_FS__GPIO4_21 = IOMUX_P(0x20c, 0x5fc, __NA_, 0x3, 0x0, MX51_GPIO_PAD_CTRL),
+ MX51_PAD_AUD3_BB_FS__UART3_TXD = IOMUX_P(0x20c, 0x5fc, __NA_, 0x1, 0x0, MX51_UART_PAD_CTRL),
MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI = IOMUX_PAD(0x600, 0x210, 0, __NA_, 0, MX51_ECSPI_PAD_CTRL),
MX51_PAD_CSPI1_MISO__ECSPI1_MISO = IOMUX_PAD(0x604, 0x214, 0, __NA_, 0, MX51_ECSPI_PAD_CTRL),
MX51_PAD_CSPI1_SS0__ECSPI1_SS0 = IOMUX_PAD(0x608, 0x218, 0, __NA_, 0, MX51_ECSPI_PAD_CTRL),
@@ -177,7 +229,9 @@ enum {
MX51_PAD_CSPI1_RDY__GPIO4_26 = IOMUX_PAD(0x610, 0x220, 3, __NA_, 0, MX51_GPIO_PAD_CTRL),
MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK = IOMUX_PAD(0x614, 0x224, 0, __NA_, 0, MX51_ECSPI_PAD_CTRL),
MX51_PAD_UART1_RXD__UART1_RXD = IOMUX_PAD(0x618, 0x228, 0, 0x9e4, 0, MX51_UART_PAD_CTRL),
+ MX51_PAD_UART1_RXD__GPIO4_28 = IOMUX_P(0x228, 0x618, __NA_, 0x3, 0x0, MX51_UART_PAD_CTRL),
MX51_PAD_UART1_TXD__UART1_TXD = IOMUX_PAD(0x61c, 0x22c, 0, __NA_, 0, MX51_UART_PAD_CTRL),
+ MX51_PAD_UART1_TXD__GPIO4_29 = IOMUX_P(0x22c, 0x61c, __NA_, 0x3, 0x0, MX51_GPIO_PAD_CTRL),
MX51_PAD_UART1_RTS__UART1_RTS = IOMUX_PAD(0x620, 0x230, 0, 0x9e0, 0, MX51_UART_PAD_CTRL),
MX51_PAD_UART1_RTS__GPIO4_30 = IOMUX_PAD(0x620, 0x230, 3, __NA_, 0, MX51_GPIO_PAD_CTRL),
MX51_PAD_UART1_CTS__UART1_CTS = IOMUX_PAD(0x624, 0x234, 0, __NA_, 0, MX51_UART_PAD_CTRL),
@@ -200,6 +254,7 @@ enum {
MX51_PAD_USBH1_DATA6__USBH1_DATA6 = IOMUX_PAD(0x6a0, 0x2a0, 0, __NA_, 0, MX51_USBH_PAD_CTRL),
MX51_PAD_USBH1_DATA7__USBH1_DATA7 = IOMUX_PAD(0x6a4, 0x2a4, 0, __NA_, 0, MX51_USBH_PAD_CTRL),
MX51_PAD_DI1_PIN11__ECSPI1_SS2 = IOMUX_PAD(0x6a8, 0x2a8, 7, __NA_, 0, MX51_ECSPI_PAD_CTRL),
+ MX51_PAD_DI1_PIN11__GPIO3_0 = IOMUX_P(0x2a8, 0x6a8, __NA_, 0x4, 0x0, MX51_GPIO_PAD_CTRL),
MX51_PAD_DI1_PIN12__GPIO3_1 = IOMUX_PAD(0x6ac, 0x2ac, 4, 0x978, 1, MX51_GPIO_PAD_CTRL),
MX51_PAD_DI1_PIN13__GPIO3_2 = IOMUX_PAD(0x6b0, 0x2b0, 4, 0x97c, 1, MX51_GPIO_PAD_CTRL),
MX51_PAD_DI1_D0_CS__GPIO3_3 = IOMUX_PAD(0x6b4, 0x2b4, 4, 0x980, 1, MX51_GPIO_PAD_CTRL),
@@ -289,6 +344,7 @@ enum {
MX51_PAD_GPIO1_7__SD2_WP = IOMUX_PAD(0x810, 0x3e4, 6, __NA_, 0, MX51_ESDHC_PAD_CTRL),
MX51_PAD_GPIO1_8__GPIO1_8 = IOMUX_PAD(0x814, 0x3e8, 0, __NA_, 0, MX51_GPIO_PAD_CTRL),
MX51_PAD_GPIO1_8__SD2_CD = IOMUX_PAD(0x814, 0x3e8, 6, __NA_, 0, MX51_ESDHC_PAD_CTRL),
+ MX51_PAD_GPIO1_9__GPIO1_9 = IOMUX_P(0x3ec, 0x818, __NA_, 0x0, 0x0, MX51_GPIO_PAD_CTRL),
MX51_GRP_DDRPKS = IOMUX_PAD(0x820, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
MX51_GRP_DRAM_B4 = IOMUX_PAD(0x82c, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
MX51_GRP_PKEDDR = IOMUX_PAD(0x838, __NA_, 0, __NA_, 0, NO_PAD_CTRL),