diff --git a/arch/arm/dts/uniphier-ph1-sld3.dtsi b/arch/arm/dts/uniphier-ph1-sld3.dtsi
index 2fa42a600f154834d4d988dcb0181ab456cdbecc..5e294364e6167a219117b416e82ef699f124e0de 100644
--- a/arch/arm/dts/uniphier-ph1-sld3.dtsi
+++ b/arch/arm/dts/uniphier-ph1-sld3.dtsi
@@ -129,6 +129,15 @@
status = "disabled";
};
+ i2c4: i2c@58600000 {
+ compatible = "panasonic,uniphier-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x58600000 0x40>;
+ clock-frequency = <400000>;
+ status = "okay";
+ };
+
system-bus-controller-misc@59800000 {
compatible = "socionext,uniphier-system-bus-controller-misc",
"syscon";
diff --git a/arch/arm/dts/uniphier-ref-daughter.dtsi b/arch/arm/dts/uniphier-ref-daughter.dtsi
index 84b2206ad4ad737aab18ceb6e3e525fadea65d3e..b8960fdc5884af2bfe355dc74f4d4d9563c4ea3f 100644
--- a/arch/arm/dts/uniphier-ref-daughter.dtsi
+++ b/arch/arm/dts/uniphier-ref-daughter.dtsi
@@ -8,7 +8,7 @@
&i2c0 {
eeprom {
- compatible = "i2c-eeprom";
+ compatible = "microchip,24lc128", "i2c-eeprom";
reg = <0x50>;
u-boot,i2c-offset-len = <2>;
};
diff --git a/arch/arm/mach-uniphier/Kconfig b/arch/arm/mach-uniphier/Kconfig
index feda49e0a69fad06db12cfb741a6e191dd590dfa..7b49ad3b490d10aaf2a9d2948bb7307c79e032c9 100644
--- a/arch/arm/mach-uniphier/Kconfig
+++ b/arch/arm/mach-uniphier/Kconfig
@@ -10,13 +10,17 @@ choice
prompt "UniPhier SoC select"
default MACH_PH1_PRO4
-config MACH_PH1_PRO4
- bool "PH1-Pro4"
+config MACH_PH1_SLD3
+ bool "PH1-sLD3"
select UNIPHIER_SMP
config MACH_PH1_LD4
bool "PH1-LD4"
+config MACH_PH1_PRO4
+ bool "PH1-Pro4"
+ select UNIPHIER_SMP
+
config MACH_PH1_SLD8
bool "PH1-sLD8"
@@ -64,11 +68,11 @@ choice
config DDR_FREQ_1600
bool "DDR3 1600"
- depends on MACH_PH1_PRO4 || MACH_PH1_LD4
+ depends on MACH_PH1_SLD3 || MACH_PH1_LD4 || MACH_PH1_PRO4
config DDR_FREQ_1333
bool "DDR3 1333"
- depends on MACH_PH1_LD4 || MACH_PH1_SLD8
+ depends on MACH_PH1_SLD3 || MACH_PH1_LD4 || MACH_PH1_SLD8
endchoice
diff --git a/arch/arm/mach-uniphier/Makefile b/arch/arm/mach-uniphier/Makefile
index 24591d6ee56faacce99d7de469bcc2b4f1648d88..103db6d7dc6cd34581cdea1249f1b797525c4471 100644
--- a/arch/arm/mach-uniphier/Makefile
+++ b/arch/arm/mach-uniphier/Makefile
@@ -32,6 +32,7 @@ obj-y += timer.o
obj-$(CONFIG_PFC_MICRO_SUPPORT_CARD) += support_card.o
obj-$(CONFIG_DCC_MICRO_SUPPORT_CARD) += support_card.o
-obj-$(CONFIG_MACH_PH1_LD4) += ph1-ld4/
-obj-$(CONFIG_MACH_PH1_PRO4) += ph1-pro4/
-obj-$(CONFIG_MACH_PH1_SLD8) += ph1-sld8/
+obj-$(CONFIG_MACH_PH1_SLD3) += ph1-sld3/
+obj-$(CONFIG_MACH_PH1_LD4) += ph1-ld4/
+obj-$(CONFIG_MACH_PH1_PRO4) += ph1-pro4/
+obj-$(CONFIG_MACH_PH1_SLD8) += ph1-sld8/
diff --git a/arch/arm/mach-uniphier/include/mach/sc-regs.h b/arch/arm/mach-uniphier/include/mach/sc-regs.h
index 20878e2d1c7cd246408517078afed7083bff7927..df502940779e42ad2417b9cc9618fc977ef189c0 100644
--- a/arch/arm/mach-uniphier/include/mach/sc-regs.h
+++ b/arch/arm/mach-uniphier/include/mach/sc-regs.h
@@ -1,7 +1,7 @@
/*
* UniPhier SC (System Control) block registers
*
- * Copyright (C) 2011-2015 Panasonic Corporation
+ * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
@@ -9,7 +9,11 @@
#ifndef ARCH_SC_REGS_H
#define ARCH_SC_REGS_H
+#if defined(CONFIG_MACH_PH1_SLD3)
+#define SC_BASE_ADDR 0xf1840000
+#else
#define SC_BASE_ADDR 0x61840000
+#endif
#define SC_DPLLCTRL (SC_BASE_ADDR | 0x1200)
#define SC_DPLLCTRL_SSC_EN (0x1 << 31)
diff --git a/arch/arm/mach-uniphier/include/mach/sg-regs.h b/arch/arm/mach-uniphier/include/mach/sg-regs.h
index a65f058ee2321b00a1bfcceb54b3f0587b54967e..43a6c35339ca09aafeed72ee558b3eb27db7685b 100644
--- a/arch/arm/mach-uniphier/include/mach/sg-regs.h
+++ b/arch/arm/mach-uniphier/include/mach/sg-regs.h
@@ -55,11 +55,12 @@
#if defined(CONFIG_MACH_PH1_PRO4)
# define SG_PINCTRL(n) (SG_PINCTRL_BASE + (n) * 8)
-#elif defined(CONFIG_MACH_PH1_LD4) || defined(CONFIG_MACH_PH1_SLD8)
+#elif defined(CONFIG_MACH_PH1_SLD3) || defined(CONFIG_MACH_PH1_LD4) || \
+ defined(CONFIG_MACH_PH1_SLD8)
# define SG_PINCTRL(n) (SG_PINCTRL_BASE + (n) * 4)
#endif
-#if defined(CONFIG_MACH_PH1_PRO4)
+#if defined(CONFIG_MACH_PH1_SLD3) || defined(CONFIG_MACH_PH1_PRO4)
#define SG_PINSELBITS 4
#elif defined(CONFIG_MACH_PH1_LD4) || defined(CONFIG_MACH_PH1_SLD8)
#define SG_PINSELBITS 8
diff --git a/arch/arm/mach-uniphier/ph1-sld3/Makefile b/arch/arm/mach-uniphier/ph1-sld3/Makefile
new file mode 100644
index 0000000000000000000000000000000000000000..f3f7ad4fe0ed2414bca4f57eb20910aa0324a277
--- /dev/null
+++ b/arch/arm/mach-uniphier/ph1-sld3/Makefile
@@ -0,0 +1,16 @@
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+ifdef CONFIG_SPL_BUILD
+obj-$(CONFIG_DEBUG_LL) += lowlevel_debug.o
+obj-y += bcu_init.o memconf.o sg_init.o pll_init.o early_clkrst_init.o \
+ early_pinctrl.o pll_spectrum.o umc_init.o
+obj-$(CONFIG_PFC_MICRO_SUPPORT_CARD) += sbc_init.o
+obj-$(CONFIG_DCC_MICRO_SUPPORT_CARD) += sbc_init_3cs.o
+obj-$(CONFIG_SPL_DM) += platdevice.o
+else
+obj-$(CONFIG_BOARD_EARLY_INIT_F) += pinctrl.o clkrst_init.o
+endif
+
+obj-y += boot-mode.o
diff --git a/arch/arm/mach-uniphier/ph1-sld3/bcu_init.c b/arch/arm/mach-uniphier/ph1-sld3/bcu_init.c
new file mode 100644
index 0000000000000000000000000000000000000000..ccc6897d0ad7414f2e9f5b5e1f351864fd2d46c0
--- /dev/null
+++ b/arch/arm/mach-uniphier/ph1-sld3/bcu_init.c
@@ -0,0 +1,36 @@
+/*
+ * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <linux/io.h>
+#include <mach/bcu-regs.h>
+
+#define ch(x) ((x) >= 32 ? 0 : (x) < 0 ? 0x11111111 : 0x11111111 << (x))
+
+void bcu_init(void)
+{
+ int shift;
+
+ writel(0x11111111, BCSCR2); /* 0x80000000-0x9fffffff: IPPC/IPPD-bus */
+ writel(0x11111111, BCSCR3); /* 0xa0000000-0xbfffffff: IPPC/IPPD-bus */
+ writel(0x11111111, BCSCR4); /* 0xc0000000-0xdfffffff: IPPC/IPPD-bus */
+ /*
+ * 0xe0000000-0xefffffff: Ex-bus
+ * 0xf0000000-0xfbffffff: ASM bus
+ * 0xfc000000-0xffffffff: OCM bus
+ */
+ writel(0x24440000, BCSCR5);
+
+ /* Specify DDR channel */
+ shift = (CONFIG_SDRAM1_BASE - CONFIG_SDRAM0_BASE) / 0x04000000 * 4;
+ writel(ch(shift), BCIPPCCHR2); /* 0x80000000-0x9fffffff */
+
+ shift -= 32;
+ writel(ch(shift), BCIPPCCHR3); /* 0xa0000000-0xbfffffff */
+
+ shift -= 32;
+ writel(ch(shift), BCIPPCCHR4); /* 0xc0000000-0xdfffffff */
+}
diff --git a/arch/arm/mach-uniphier/ph1-sld3/boot-mode.c b/arch/arm/mach-uniphier/ph1-sld3/boot-mode.c
new file mode 100644
index 0000000000000000000000000000000000000000..40000afe74102165b2cea1e9c357bf66716d09ec
--- /dev/null
+++ b/arch/arm/mach-uniphier/ph1-sld3/boot-mode.c
@@ -0,0 +1,97 @@
+/*
+ * Copyright (C) 2014-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <spl.h>
+#include <linux/io.h>
+#include <mach/boot-device.h>
+#include <mach/sg-regs.h>
+#include <mach/sbc-regs.h>
+
+struct boot_device_info boot_device_table[] = {
+ {BOOT_DEVICE_NONE, "Reserved"},
+ {BOOT_DEVICE_NONE, "External Master"},
+ {BOOT_DEVICE_NONE, "Reserved"},
+ {BOOT_DEVICE_NONE, "Reserved"},
+ {BOOT_DEVICE_MMC1, "eMMC (3.3V, Boot Oparation)"},
+ {BOOT_DEVICE_NONE, "Reserved"},
+ {BOOT_DEVICE_MMC1, "eMMC (1.8V, Boot Oparation)"},
+ {BOOT_DEVICE_NONE, "Reserved"},
+ {BOOT_DEVICE_MMC1, "eMMC (3.3V, Normal)"},
+ {BOOT_DEVICE_NONE, "Reserved"},
+ {BOOT_DEVICE_MMC1, "eMMC (1.8V, Normal)"},
+ {BOOT_DEVICE_NONE, "Reserved"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 128KB, Addr 5)"},
+ {BOOT_DEVICE_NONE, "Reserved"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 256KB, Addr 5)"},
+ {BOOT_DEVICE_NONE, "Reserved"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 512KB, Addr 5)"},
+ {BOOT_DEVICE_NONE, "Reserved"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 128KB, Addr 5)"},
+ {BOOT_DEVICE_NONE, "Reserved"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 256KB, Addr 5)"},
+ {BOOT_DEVICE_NONE, "Reserved"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 512KB, Addr 5)"},
+ {BOOT_DEVICE_NONE, "Reserved"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 4, ECC 24, EraseSize 1MB, Addr 5)"},
+ {BOOT_DEVICE_NONE, "Reserved"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 128KB, Addr 5)"},
+ {BOOT_DEVICE_NONE, "Reserved"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 256KB, Addr 5)"},
+ {BOOT_DEVICE_NONE, "Reserved"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 512KB, Addr 5)"},
+ {BOOT_DEVICE_NONE, "Reserved"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 128KB, Addr 5)"},
+ {BOOT_DEVICE_NONE, "Reserved"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 256KB, Addr 5)"},
+ {BOOT_DEVICE_NONE, "Reserved"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 512KB, Addr 5)"},
+ {BOOT_DEVICE_NONE, "Reserved"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 24, EraseSize 1MB, Addr 5)"},
+ {BOOT_DEVICE_NONE, "Reserved"},
+ {BOOT_DEVICE_NONE, "Reserved"},
+ {BOOT_DEVICE_NONE, "Reserved"},
+ {BOOT_DEVICE_NONE, "Reserved"},
+ {BOOT_DEVICE_NONE, "Reserved"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, ONFI, Addr 5)"},
+ {BOOT_DEVICE_NONE, "Reserved"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, ONFI, Addr 5)"},
+ {BOOT_DEVICE_NONE, "Reserved"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 4, ECC 24, ONFI, Addr 5)"},
+ {BOOT_DEVICE_NONE, "Reserved"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, ONFI, Addr 5)"},
+ {BOOT_DEVICE_NONE, "Reserved"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, ONFI, Addr 5)"},
+ {BOOT_DEVICE_NONE, "Reserved"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 24, ONFI, Addr 5)"},
+ {BOOT_DEVICE_NONE, "Reserved"},
+ {BOOT_DEVICE_NONE, "Reserved"},
+ {BOOT_DEVICE_NONE, "Reserved"},
+ {BOOT_DEVICE_NONE, "Reserved"},
+ {BOOT_DEVICE_NONE, "Reserved"},
+ {BOOT_DEVICE_NONE, "Reserved"},
+ {BOOT_DEVICE_NONE, "Reserved"},
+ {BOOT_DEVICE_NONE, "Reserved"},
+ {BOOT_DEVICE_NONE, "Reserved"},
+ { /* sentinel */ }
+};
+
+int get_boot_mode_sel(void)
+{
+ return readl(SG_PINMON0) & 0x3f;
+}
+
+u32 spl_boot_device(void)
+{
+ int boot_mode;
+
+ if (boot_is_swapped())
+ return BOOT_DEVICE_NOR;
+
+ boot_mode = get_boot_mode_sel();
+
+ return boot_device_table[boot_mode].type;
+}
diff --git a/arch/arm/mach-uniphier/ph1-sld3/clkrst_init.c b/arch/arm/mach-uniphier/ph1-sld3/clkrst_init.c
new file mode 100644
index 0000000000000000000000000000000000000000..3a3dab7a1534d25bbf4bebcd8c4c08815a8cba3d
--- /dev/null
+++ b/arch/arm/mach-uniphier/ph1-sld3/clkrst_init.c
@@ -0,0 +1 @@
+#include "../ph1-pro4/clkrst_init.c"
diff --git a/arch/arm/mach-uniphier/ph1-sld3/early_clkrst_init.c b/arch/arm/mach-uniphier/ph1-sld3/early_clkrst_init.c
new file mode 100644
index 0000000000000000000000000000000000000000..d7ef16b10a175f019334e65ec97f2f3e9b9e4518
--- /dev/null
+++ b/arch/arm/mach-uniphier/ph1-sld3/early_clkrst_init.c
@@ -0,0 +1 @@
+#include "../ph1-pro4/early_clkrst_init.c"
diff --git a/arch/arm/mach-uniphier/ph1-sld3/early_pinctrl.c b/arch/arm/mach-uniphier/ph1-sld3/early_pinctrl.c
new file mode 100644
index 0000000000000000000000000000000000000000..f113e658d8e13d213982a2767bd0adfebc5ff608
--- /dev/null
+++ b/arch/arm/mach-uniphier/ph1-sld3/early_pinctrl.c
@@ -0,0 +1,23 @@
+/*
+ * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <mach/sg-regs.h>
+
+void early_pin_init(void)
+{
+ /* Comment format: PAD Name -> Function Name */
+
+#ifdef CONFIG_UNIPHIER_SERIAL
+ sg_set_pinsel(63, 0); /* RXD0 */
+ sg_set_pinsel(64, 1); /* TXD0 */
+
+ sg_set_pinsel(65, 0); /* RXD1 */
+ sg_set_pinsel(66, 1); /* TXD1 */
+
+ sg_set_pinsel(96, 2); /* RXD2 */
+ sg_set_pinsel(102, 2); /* TXD2 */
+#endif
+}
diff --git a/arch/arm/mach-uniphier/ph1-sld3/lowlevel_debug.S b/arch/arm/mach-uniphier/ph1-sld3/lowlevel_debug.S
new file mode 100644
index 0000000000000000000000000000000000000000..9d1fd2c964826a07a9894c174f50bd98d2b57d54
--- /dev/null
+++ b/arch/arm/mach-uniphier/ph1-sld3/lowlevel_debug.S
@@ -0,0 +1,31 @@
+/*
+ * On-chip UART initializaion for low-level debugging
+ *
+ * Copyright (C) 2014-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <linux/linkage.h>
+#include <mach/bcu-regs.h>
+#include <mach/sc-regs.h>
+#include <mach/sg-regs.h>
+#include <mach/debug-uart.S>
+
+ENTRY(setup_lowlevel_debug)
+ ldr r0, =BCSCR5
+ ldr r1, =0x24440000
+ str r1, [r0]
+
+ ldr r0, =SC_CLKCTRL
+ ldr r1, [r0]
+ orr r1, r1, #SC_CLKCTRL_CEN_PERI
+ str r1, [r0]
+
+ init_debug_uart r0, r1, r2
+
+ set_pinsel 63, 0, r0, r1
+ set_pinsel 64, 1, r0, r1
+
+ mov pc, lr
+ENDPROC(setup_lowlevel_debug)
diff --git a/arch/arm/mach-uniphier/ph1-sld3/memconf.c b/arch/arm/mach-uniphier/ph1-sld3/memconf.c
new file mode 100644
index 0000000000000000000000000000000000000000..553a9e3384470d7ee828a86e59fbc3bb28a35a8c
--- /dev/null
+++ b/arch/arm/mach-uniphier/ph1-sld3/memconf.c
@@ -0,0 +1,52 @@
+/*
+ * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <linux/types.h>
+#include <linux/sizes.h>
+#include <mach/sg-regs.h>
+
+static inline u32 sg_memconf_val_ch2(unsigned long size, int num)
+{
+ int size_mb = size / num;
+ u32 ret;
+
+ switch (size_mb) {
+ case SZ_64M:
+ ret = SG_MEMCONF_CH2_SZ_64M;
+ break;
+ case SZ_128M:
+ ret = SG_MEMCONF_CH2_SZ_128M;
+ break;
+ case SZ_256M:
+ ret = SG_MEMCONF_CH2_SZ_256M;
+ break;
+ case SZ_512M:
+ ret = SG_MEMCONF_CH2_SZ_512M;
+ break;
+ default:
+ BUG();
+ break;
+ }
+
+ switch (num) {
+ case 1:
+ ret |= SG_MEMCONF_CH2_NUM_1;
+ break;
+ case 2:
+ ret |= SG_MEMCONF_CH2_NUM_2;
+ break;
+ default:
+ BUG();
+ break;
+ }
+ return ret;
+}
+
+u32 memconf_additional_val(void)
+{
+ return sg_memconf_val_ch2(CONFIG_SDRAM2_SIZE, CONFIG_DDR_NUM_CH2);
+}
diff --git a/arch/arm/mach-uniphier/ph1-sld3/pinctrl.c b/arch/arm/mach-uniphier/ph1-sld3/pinctrl.c
new file mode 100644
index 0000000000000000000000000000000000000000..5ecbe4cca3f9e77f5906d336fb701f3e1d5d6f76
--- /dev/null
+++ b/arch/arm/mach-uniphier/ph1-sld3/pinctrl.c
@@ -0,0 +1,24 @@
+/*
+ * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <mach/sg-regs.h>
+
+void pin_init(void)
+{
+#ifdef CONFIG_USB_EHCI_UNIPHIER
+ sg_set_pinsel(13, 0); /* USB0OC */
+ sg_set_pinsel(14, 1); /* USB0VBUS */
+
+ sg_set_pinsel(15, 0); /* USB1OC */
+ sg_set_pinsel(16, 1); /* USB1VBUS */
+
+ sg_set_pinsel(17, 0); /* USB2OC */
+ sg_set_pinsel(18, 1); /* USB2VBUS */
+
+ sg_set_pinsel(19, 0); /* USB3OC */
+ sg_set_pinsel(20, 1); /* USB3VBUS */
+#endif
+}
diff --git a/arch/arm/mach-uniphier/ph1-sld3/platdevice.c b/arch/arm/mach-uniphier/ph1-sld3/platdevice.c
new file mode 100644
index 0000000000000000000000000000000000000000..652106712f23872c779660eff479bad50030b561
--- /dev/null
+++ b/arch/arm/mach-uniphier/ph1-sld3/platdevice.c
@@ -0,0 +1 @@
+#include "../ph1-ld4/platdevice.c"
diff --git a/arch/arm/mach-uniphier/ph1-sld3/pll_init.c b/arch/arm/mach-uniphier/ph1-sld3/pll_init.c
new file mode 100644
index 0000000000000000000000000000000000000000..ebd1c310b7ace91b421e1ee1517ffff061264b9d
--- /dev/null
+++ b/arch/arm/mach-uniphier/ph1-sld3/pll_init.c
@@ -0,0 +1,10 @@
+/*
+ * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+void pll_init(void)
+{
+ /* add pll init code here */
+}
diff --git a/arch/arm/mach-uniphier/ph1-sld3/pll_spectrum.c b/arch/arm/mach-uniphier/ph1-sld3/pll_spectrum.c
new file mode 100644
index 0000000000000000000000000000000000000000..fcf2ad282a76f08fc90047229db1e300349847e2
--- /dev/null
+++ b/arch/arm/mach-uniphier/ph1-sld3/pll_spectrum.c
@@ -0,0 +1,18 @@
+/*
+ * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <linux/io.h>
+#include <mach/sc-regs.h>
+
+void enable_dpll_ssc(void)
+{
+ u32 tmp;
+
+ tmp = readl(SC_DPLLCTRL);
+ tmp |= SC_DPLLCTRL_SSC_EN;
+ writel(tmp, SC_DPLLCTRL);
+}
diff --git a/arch/arm/mach-uniphier/ph1-sld3/sbc_init.c b/arch/arm/mach-uniphier/ph1-sld3/sbc_init.c
new file mode 100644
index 0000000000000000000000000000000000000000..d66f89ea51fae969a4a6a5037f5cea3baf8faba6
--- /dev/null
+++ b/arch/arm/mach-uniphier/ph1-sld3/sbc_init.c
@@ -0,0 +1,45 @@
+/*
+ * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <linux/io.h>
+#include <mach/sbc-regs.h>
+#include <mach/sg-regs.h>
+
+void sbc_init(void)
+{
+ /* only address/data multiplex mode is supported */
+
+ /*
+ * Only CS1 is connected to support card.
+ * BKSZ[1:0] should be set to "01".
+ */
+ writel(SBCTRL0_ADMULTIPLX_MEM_VALUE, SBCTRL10);
+ writel(SBCTRL1_ADMULTIPLX_MEM_VALUE, SBCTRL11);
+ writel(SBCTRL2_ADMULTIPLX_MEM_VALUE, SBCTRL12);
+
+ if (boot_is_swapped()) {
+ /*
+ * Boot Swap On: boot from external NOR/SRAM
+ * 0x02000000-0x03ffffff is a mirror of 0x00000000-0x01ffffff.
+ *
+ * 0x00000000-0x01efffff, 0x02000000-0x03efffff: memory bank
+ * 0x01f00000-0x01ffffff, 0x03f00000-0x03ffffff: peripherals
+ */
+ writel(0x0000bc01, SBBASE0);
+ } else {
+ /*
+ * Boot Swap Off: boot from mask ROM
+ * 0x00000000-0x01ffffff: mask ROM
+ * 0x02000000-0x03efffff: memory bank (31MB)
+ * 0x03f00000-0x03ffffff: peripherals (1MB)
+ */
+ writel(0x0000be01, SBBASE0); /* dummy */
+ writel(0x0200be01, SBBASE1);
+ }
+
+ sg_set_pinsel(99, 1); /* GPIO26 -> EA24 */
+}
diff --git a/arch/arm/mach-uniphier/ph1-sld3/sbc_init_3cs.c b/arch/arm/mach-uniphier/ph1-sld3/sbc_init_3cs.c
new file mode 100644
index 0000000000000000000000000000000000000000..f5e24467ced00112fa1d309428c7ae5d1c3384db
--- /dev/null
+++ b/arch/arm/mach-uniphier/ph1-sld3/sbc_init_3cs.c
@@ -0,0 +1,37 @@
+/*
+ * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <linux/io.h>
+#include <mach/sbc-regs.h>
+#include <mach/sg-regs.h>
+
+void sbc_init(void)
+{
+ /* only address/data multiplex mode is supported */
+
+ /* XECS0 : boot/sub memory (boot swap = off/on) */
+ writel(SBCTRL0_ADMULTIPLX_MEM_VALUE, SBCTRL00);
+ writel(SBCTRL1_ADMULTIPLX_MEM_VALUE, SBCTRL01);
+ writel(SBCTRL2_ADMULTIPLX_MEM_VALUE, SBCTRL02);
+
+ /* XECS1 : sub/boot memory (boot swap = off/on) */
+ writel(SBCTRL0_ADMULTIPLX_MEM_VALUE, SBCTRL10);
+ writel(SBCTRL1_ADMULTIPLX_MEM_VALUE, SBCTRL11);
+ writel(SBCTRL2_ADMULTIPLX_MEM_VALUE, SBCTRL12);
+
+ /* XECS2 : peripherals */
+ writel(SBCTRL0_ADMULTIPLX_PERI_VALUE, SBCTRL20);
+ writel(SBCTRL1_ADMULTIPLX_PERI_VALUE, SBCTRL21);
+ writel(SBCTRL2_ADMULTIPLX_PERI_VALUE, SBCTRL22);
+
+ /* base address regsiters */
+ writel(0x0000bc01, SBBASE0);
+ writel(0x0400bc01, SBBASE1);
+ writel(0x0800bf01, SBBASE2);
+
+ sg_set_pinsel(99, 1); /* GPIO26 -> EA24 */
+}
diff --git a/arch/arm/mach-uniphier/ph1-sld3/sg_init.c b/arch/arm/mach-uniphier/ph1-sld3/sg_init.c
new file mode 100644
index 0000000000000000000000000000000000000000..ca3cb9c6b8e5b8e69e1467332dd5ae3ffe170dad
--- /dev/null
+++ b/arch/arm/mach-uniphier/ph1-sld3/sg_init.c
@@ -0,0 +1,9 @@
+/*
+ * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+void sg_init(void)
+{
+}
diff --git a/arch/arm/mach-uniphier/ph1-sld3/umc_init.c b/arch/arm/mach-uniphier/ph1-sld3/umc_init.c
new file mode 100644
index 0000000000000000000000000000000000000000..91ee3de2827045ba6ccd5a243eab096894c5ea8d
--- /dev/null
+++ b/arch/arm/mach-uniphier/ph1-sld3/umc_init.c
@@ -0,0 +1,15 @@
+/*
+ * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+
+int umc_init(void)
+{
+ /* add UMC init code here */
+ printf("Implement memory init code\n");
+
+ return 0;
+}
diff --git a/configs/ph1_ld4_defconfig b/configs/ph1_ld4_defconfig
index a71511c4107190cd40d1d4105ef03b211e2530cd..f84dcdf46a4af78019cec0812b871f6eaabcd5f0 100644
--- a/configs/ph1_ld4_defconfig
+++ b/configs/ph1_ld4_defconfig
@@ -4,8 +4,6 @@ CONFIG_MACH_PH1_LD4=y
CONFIG_PFC_MICRO_SUPPORT_CARD=y
CONFIG_SYS_TEXT_BASE=0x84000000
CONFIG_DEFAULT_DEVICE_TREE="uniphier-ph1-ld4-ref"
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
CONFIG_HUSH_PARSER=y
# CONFIG_CMD_XIMG is not set
# CONFIG_CMD_ENV_EXISTS is not set
diff --git a/configs/ph1_pro4_defconfig b/configs/ph1_pro4_defconfig
index d02712eb573efaa721240ec1858db8f2f18cff57..2fc844d9074695c2f39d6180dd6e5396f345de7e 100644
--- a/configs/ph1_pro4_defconfig
+++ b/configs/ph1_pro4_defconfig
@@ -3,8 +3,6 @@ CONFIG_ARCH_UNIPHIER=y
CONFIG_PFC_MICRO_SUPPORT_CARD=y
CONFIG_SYS_TEXT_BASE=0x84000000
CONFIG_DEFAULT_DEVICE_TREE="uniphier-ph1-pro4-ref"
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
CONFIG_HUSH_PARSER=y
# CONFIG_CMD_XIMG is not set
# CONFIG_CMD_ENV_EXISTS is not set
diff --git a/configs/ph1_sld3_defconfig b/configs/ph1_sld3_defconfig
new file mode 100644
index 0000000000000000000000000000000000000000..386a0d13dd933cdb0a696bcc69cf3a7241394e5e
--- /dev/null
+++ b/configs/ph1_sld3_defconfig
@@ -0,0 +1,28 @@
+CONFIG_ARM=y
+CONFIG_ARCH_UNIPHIER=y
+CONFIG_MACH_PH1_SLD3=y
+CONFIG_PFC_MICRO_SUPPORT_CARD=y
+CONFIG_SYS_TEXT_BASE=0x84000000
+CONFIG_DEFAULT_DEVICE_TREE="uniphier-ph1-sld3-ref"
+CONFIG_HUSH_PARSER=y
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_ENV_EXISTS is not set
+CONFIG_CMD_NAND=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_TFTPPUT=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_TIME=y
+# CONFIG_CMD_MISC is not set
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM=y
+CONFIG_NAND_DENALI=y
+CONFIG_SYS_NAND_DENALI_64BIT=y
+CONFIG_NAND_DENALI_SPARE_AREA_SKIP_BYTES=8
+CONFIG_SPL_NAND_DENALI=y
+CONFIG_UNIPHIER_SERIAL=y
+CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_STORAGE=y
diff --git a/configs/ph1_sld8_defconfig b/configs/ph1_sld8_defconfig
index ee4cebcef38da5dbe23885238fa9d33bc6f1e472..2af45d2a557a6974c3c39a7cb439255a8344e74f 100644
--- a/configs/ph1_sld8_defconfig
+++ b/configs/ph1_sld8_defconfig
@@ -4,8 +4,6 @@ CONFIG_MACH_PH1_SLD8=y
CONFIG_PFC_MICRO_SUPPORT_CARD=y
CONFIG_SYS_TEXT_BASE=0x84000000
CONFIG_DEFAULT_DEVICE_TREE="uniphier-ph1-sld8-ref"
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
CONFIG_HUSH_PARSER=y
# CONFIG_CMD_XIMG is not set
# CONFIG_CMD_ENV_EXISTS is not set
diff --git a/doc/README.uniphier b/doc/README.uniphier
index 4902533544ff0a02679c0b614abaaf6441122c70..52d681b57aedc69d51ab6b7b520a3b59ec764935 100644
--- a/doc/README.uniphier
+++ b/doc/README.uniphier
@@ -28,14 +28,18 @@ Tested toolchains
Compile the source
------------------
-PH1-Pro4:
- $ make ph1_pro4_defconfig
+PH1-sLD3:
+ $ make ph1_sld3_defconfig
$ make CROSS_COMPILE=arm-linux-gnueabi-
PH1-LD4:
$ make ph1_ld4_defconfig
$ make CROSS_COMPILE=arm-linux-gnueabi-
+PH1-Pro4:
+ $ make ph1_pro4_defconfig
+ $ make CROSS_COMPILE=arm-linux-gnueabi-
+
PH1-sLD8:
$ make ph1_sld8_defconfig
$ make CROSS_COMPILE=arm-linux-gnueabi-
@@ -81,6 +85,48 @@ Supported devices
- Support card (SRAM, NOR flash, some peripherals)
+Micro Support Card
+------------------
+
+The recommended bit switch settings are as follows:
+
+ SW2 OFF(1)/ON(0) Description
+ ------------------------------------------
+ bit 1 <---- BKSZ[0]
+ bit 2 ----> BKSZ[1]
+ bit 3 <---- SoC Bus Width 16/32
+ bit 4 <---- SERIAL_SEL[0]
+ bit 5 ----> SERIAL_SEL[1]
+ bit 6 ----> BOOTSWAP_EN
+ bit 7 <---- CS1/CS5
+ bit 8 <---- SOC_SERIAL_DISABLE
+
+ SW8 OFF(1)/ON(0) Description
+ ------------------------------------------
+ bit 1 ----> CS1_SPLIT
+ bit 2 <---- CASE9_ON
+ bit 3 <---- CASE10_ON
+ bit 4 Don't Care Reserve
+ bit 5 Don't Care Reserve
+ bit 6 Don't Care Reserve
+ bit 7 ----> BURST_EN
+ bit 8 ----> FLASHBUS32_16
+
+The BKSZ[1:0] specifies the address range of memory slot and peripherals
+as follows:
+
+ BKSZ Description RAM slot Peripherals
+ --------------------------------------------------------------------
+ 0b00 15MB RAM / 1MB Peri 00000000-0effffff 0f000000-0fffffff
+ 0b01 31MB RAM / 1MB Peri 00000000-1effffff 1f000000-1fffffff
+ 0b10 64MB RAM / 1MB Peri 00000000-3effffff 3f000000-3fffffff
+ 0b11 127MB RAM / 1MB Peri 00000000-7effffff 7f000000-7fffffff
+
+Set BSKZ[1:0] to 0b01 for U-Boot.
+This mode is the most handy because EA[24] is always supported by the save pin
+mode of the system bus. On the other hand, EA[25] is not supported for some
+newer SoCs. Even if it is, EA[25] is not connected on most of the boards.
+
--
-Masahiro Yamada <yamada.m@jp.panasonic.com>
-Feb. 2015
+Masahiro Yamada <yamada.masahiro@socionext.com>
+Jul. 2015
diff --git a/include/configs/uniphier.h b/include/configs/uniphier.h
index 5c7a342d73d65ee494aa267dbbc154338385c1a4..908be266f3936be6681d82fa11b4158dce37b5ac 100644
--- a/include/configs/uniphier.h
+++ b/include/configs/uniphier.h
@@ -9,15 +9,18 @@
#ifndef __CONFIG_UNIPHIER_COMMON_H__
#define __CONFIG_UNIPHIER_COMMON_H__
-#if defined(CONFIG_MACH_PH1_PRO4)
+#if defined(CONFIG_MACH_PH1_SLD3)
#define CONFIG_DDR_NUM_CH0 2
-#define CONFIG_DDR_NUM_CH1 2
+#define CONFIG_DDR_NUM_CH1 1
+#define CONFIG_DDR_NUM_CH2 1
/* Physical start address of SDRAM */
#define CONFIG_SDRAM0_BASE 0x80000000
#define CONFIG_SDRAM0_SIZE 0x20000000
-#define CONFIG_SDRAM1_BASE 0xa0000000
+#define CONFIG_SDRAM1_BASE 0xc0000000
#define CONFIG_SDRAM1_SIZE 0x20000000
+#define CONFIG_SDRAM2_BASE 0xc0000000
+#define CONFIG_SDRAM2_SIZE 0x10000000
#endif
#if defined(CONFIG_MACH_PH1_LD4)
@@ -31,6 +34,17 @@
#define CONFIG_SDRAM1_SIZE 0x10000000
#endif
+#if defined(CONFIG_MACH_PH1_PRO4)
+#define CONFIG_DDR_NUM_CH0 2
+#define CONFIG_DDR_NUM_CH1 2
+
+/* Physical start address of SDRAM */
+#define CONFIG_SDRAM0_BASE 0x80000000
+#define CONFIG_SDRAM0_SIZE 0x20000000
+#define CONFIG_SDRAM1_BASE 0xa0000000
+#define CONFIG_SDRAM1_SIZE 0x20000000
+#endif
+
#if defined(CONFIG_MACH_PH1_SLD8)
#define CONFIG_DDR_NUM_CH0 1
#define CONFIG_DDR_NUM_CH1 1
@@ -177,8 +191,13 @@
#define CONFIG_NAND_DENALI_ECC_SIZE 1024
+#ifdef CONFIG_MACH_PH1_SLD3
+#define CONFIG_SYS_NAND_REGS_BASE 0xf8100000
+#define CONFIG_SYS_NAND_DATA_BASE 0xf8000000
+#else
#define CONFIG_SYS_NAND_REGS_BASE 0x68100000
#define CONFIG_SYS_NAND_DATA_BASE 0x68000000
+#endif
#define CONFIG_SYS_NAND_BASE (CONFIG_SYS_NAND_DATA_BASE + 0x10)
@@ -209,7 +228,6 @@
#define CONFIG_LOADADDR 0x84000000
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
-#define CONFIG_BOOTFILE "fit.itb"
#define CONFIG_CMDLINE_EDITING /* add command line history */
@@ -222,25 +240,61 @@
"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off;" \
"tftpboot; bootm;"
-#define CONFIG_BOOTARGS " user_debug=0x1f init=/sbin/init"
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "netdev=eth0\0" \
- "image_offset=0x00080000\0" \
- "image_size=0x00f00000\0" \
- "verify=n\0" \
- "nandupdate=nand erase 0 0x100000 &&" \
- "tftpboot u-boot-spl.bin &&" \
- "nand write $loadaddr 0 0x10000 &&" \
- "tftpboot u-boot-dtb.img &&" \
- "nand write $loadaddr 0x10000 0xf0000\0" \
- "norboot=run add_default_bootargs &&" \
- "bootm $image_offset\0" \
- "nandboot=run add_default_bootargs &&" \
- "nand read $loadaddr $image_offset $image_size &&" \
- "bootm\0" \
- "add_default_bootargs=setenv bootargs $bootargs" \
- " console=ttyS0,$baudrate\0" \
+#define CONFIG_BOOTARGS " earlyprintk loglevel=8"
+
+#ifdef CONFIG_FIT
+#define CONFIG_BOOTFILE "fitImage"
+#define LINUXBOOT_ENV_SETTINGS \
+ "fit_addr=0x00100000\0" \
+ "fit_addr_r=0x84100000\0" \
+ "fit_size=0x00f00000\0" \
+ "norboot=run add_default_bootargs &&" \
+ "bootm $fit_addr\0" \
+ "nandboot=run add_default_bootargs &&" \
+ "nand read $fit_addr_r $fit_addr $fit_size &&" \
+ "bootm $fit_addr_r\0" \
+ "tftpboot=run add_default_bootargs &&" \
+ "tftpboot $fit_addr_r $bootfile &&" \
+ "bootm $fit_addr_r\0"
+#else
+#define CONFIG_BOOTFILE "uImage"
+#define LINUXBOOT_ENV_SETTINGS \
+ "fdt_addr=0x00100000\0" \
+ "fdt_addr_r=0x84100000\0" \
+ "fdt_size=0x00008000\0" \
+ "fdt_file=" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \
+ "kernel_addr=0x00200000\0" \
+ "kernel_addr_r=0x84200000\0" \
+ "kernel_size=0x00800000\0" \
+ "ramdisk_addr=0x00a00000\0" \
+ "ramdisk_addr_r=0x84a00000\0" \
+ "ramdisk_size=0x00600000\0" \
+ "ramdisk_file=rootfs.cpio.uboot\0" \
+ "norboot=run add_default_bootargs &&" \
+ "bootm $kernel_addr $ramdisk_addr $fdt_addr\0" \
+ "nandboot=run add_default_bootargs &&" \
+ "nand read $kernel_addr_r $kernel_addr $kernel_size &&" \
+ "nand read $ramdisk_addr_r $ramdisk_addr $ramdisk_size &&" \
+ "nand read $fdt_addr_r $fdt_addr $fdt_size &&" \
+ "bootm $kernel_addr_r $ramdisk_addr_r $fdt_addr_r\0" \
+ "tftpboot=run add_default_bootargs &&" \
+ "tftpboot $kernel_addr_r $bootfile &&" \
+ "tftpboot $ramdisk_addr_r $ramdisk_file &&" \
+ "tftpboot $fdt_addr_r $fdt_file &&" \
+ "bootm $kernel_addr_r $ramdisk_addr_r $fdt_addr_r\0"
+#endif
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "netdev=eth0\0" \
+ "verify=n\0" \
+ "nandupdate=nand erase 0 0x00100000 &&" \
+ "tftpboot u-boot-spl.bin &&" \
+ "nand write $loadaddr 0 0x00010000 &&" \
+ "tftpboot u-boot-dtb.img &&" \
+ "nand write $loadaddr 0x00010000 0x000f0000\0" \
+ "add_default_bootargs=setenv bootargs $bootargs" \
+ " console=ttyS0,$baudrate\0" \
+ LINUXBOOT_ENV_SETTINGS
/* Open Firmware flat tree */
#define CONFIG_OF_LIBFDT
@@ -259,7 +313,8 @@
#define CONFIG_SYS_SDRAM_SIZE (CONFIG_SDRAM0_SIZE)
#endif
-#if defined(CONFIG_MACH_PH1_LD4) || defined(CONFIG_MACH_PH1_SLD8)
+#if defined(CONFIG_MACH_PH1_SLD3) || defined(CONFIG_MACH_PH1_LD4) || \
+ defined(CONFIG_MACH_PH1_SLD8)
#define CONFIG_SPL_TEXT_BASE 0x00040000
#endif
#if defined(CONFIG_MACH_PH1_PRO4)