From 3291375546156a63cfabbaf4d38569377122d80b Mon Sep 17 00:00:00 2001
From: mntmn <lukas@mntmn.com>
Date: Thu, 21 May 2020 16:35:24 +0200
Subject: [PATCH] reform2: WIP some comments for lpddr4_init
---
drivers/ddr/imx/imx8m/lpddr4_init.c | 8 +++++---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/drivers/ddr/imx/imx8m/lpddr4_init.c b/drivers/ddr/imx/imx8m/lpddr4_init.c
index ef3c7839bf4..420edc36244 100644
--- a/drivers/ddr/imx/imx8m/lpddr4_init.c
+++ b/drivers/ddr/imx/imx8m/lpddr4_init.c
@@ -28,7 +28,7 @@ void ddr_init(struct dram_timing_info *dram_timing)
{
unsigned mstr2;
unsigned int tmp;
- int imx8mq = is_imx8mq();
+ int imx8mq = is_imx8mq(); // seems to make no difference
debug("DDRINFO: start lpddr4 ddr init\n");
/* step 1: reset */
@@ -49,8 +49,9 @@ void ddr_init(struct dram_timing_info *dram_timing)
* source 4 800MHz /4 = 200MHz
*/
clock_set_target_val(DRAM_APB_CLK_ROOT, CLK_ROOT_ON |
- CLK_ROOT_SOURCE_SEL(4) |
- CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV4));
+ CLK_ROOT_SOURCE_SEL(4) |
+ CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV4));
+ // seems unnecessary
/* disable iso */
reg32_write(0x303A00EC, 0x0000ffff); /* PGC_CPU_MAPPING */
@@ -58,6 +59,7 @@ void ddr_init(struct dram_timing_info *dram_timing)
debug("DDRINFO: cfg clk\n");
dram_pll_init(MHZ(imx8mq ? 800 : 750));
+ // doesn't matter
/*
* release [0]ddr1_preset_n, [1]ddr1_core_reset_n,
--
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