diff --git a/arch/x86/cpu/coreboot/sdram.c b/arch/x86/cpu/coreboot/sdram.c
index 786009c746d924255db184e22b998cc50de68c8e..b4fe6c91cfaedb6b1deecc9b5c9c17d24b3f94a0 100644
--- a/arch/x86/cpu/coreboot/sdram.c
+++ b/arch/x86/cpu/coreboot/sdram.c
@@ -113,7 +113,7 @@ int dram_init_f(void)
 	return 0;
 }
 
-int dram_init(void)
+int dram_init_banksize(void)
 {
 	int i, j;
 
@@ -132,3 +132,8 @@ int dram_init(void)
 	}
 	return 0;
 }
+
+int dram_init(void)
+{
+	return dram_init_banksize();
+}
diff --git a/common/board_f.c b/common/board_f.c
index 769889123b48216df5f5f89d6e18b5ffcf5668f5..00ca81126c7cde0c2113c389d4e9813c151dcd3d 100644
--- a/common/board_f.c
+++ b/common/board_f.c
@@ -755,7 +755,7 @@ static int mark_bootstage(void)
 static init_fnc_t init_sequence_f[] = {
 #if !defined(CONFIG_CPM2) && !defined(CONFIG_MPC512X) && \
 		!defined(CONFIG_MPC83xx) && !defined(CONFIG_MPC85xx) && \
-		!defined(CONFIG_MPC86xx)
+		!defined(CONFIG_MPC86xx) && !defined(CONFIG_X86)
 	zero_global_data,
 #endif
 	setup_fdt,
@@ -856,8 +856,7 @@ static init_fnc_t init_sequence_f[] = {
 #endif
 #ifdef CONFIG_X86
 	dram_init_f,		/* configure available RAM banks */
-	/* x86 would prefer that this happens after relocation */
-	dram_init,
+	calculate_relocation_address,
 #endif
 	announce_dram_init,
 	/* TODO: unify all these dram functions? */
diff --git a/common/board_r.c b/common/board_r.c
index 9605f80a0cbfb61523534bb9a11e0f0ef20fd428..2b17fa6cfedef6db677d1931dfe6ca7af2f5f769 100644
--- a/common/board_r.c
+++ b/common/board_r.c
@@ -721,9 +721,6 @@ init_fnc_t init_sequence_r[] = {
 	 */
 #ifdef CONFIG_CLOCKS
 	set_cpu_clk_info, /* Setup clock information */
-#endif
-#ifdef CONFIG_X86
-	init_bd_struct_r,
 #endif
 	initr_reloc_global_data,
 	initr_serial,
diff --git a/include/configs/coreboot.h b/include/configs/coreboot.h
index a4aa8f74535e4d3f1d769e8b2c4e51759c2a840a..5bacc77bb50dcf7602e4cb9b5ea0c1a08eebed87 100644
--- a/include/configs/coreboot.h
+++ b/include/configs/coreboot.h
@@ -41,6 +41,7 @@
 #define CONFIG_INTEL_CORE_ARCH	/* Sandy bridge and ivy bridge chipsets. */
 #define CONFIG_ZBOOT_32
 #define CONFIG_PHYSMEM
+#define CONFIG_SYS_EARLY_PCI_INIT
 
 #define CONFIG_LMB
 #define CONFIG_OF_LIBFDT