diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h
index 7736b6a8ac0452d110393242ec42b6a2de36ea0d..48ce0edd0625b7ed3534debab3a652f521609567 100644
--- a/arch/arm/include/asm/arch-mx6/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx6/imx-regs.h
@@ -17,7 +17,7 @@
#define GPU_2D_ARB_END_ADDR 0x02203FFF
#define OPENVG_ARB_BASE_ADDR 0x02204000
#define OPENVG_ARB_END_ADDR 0x02207FFF
-#elif (defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL))
+#elif (defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL))
#define CAAM_ARB_BASE_ADDR 0x00100000
#define CAAM_ARB_END_ADDR 0x00107FFF
#define GPU_ARB_BASE_ADDR 0x01800000
@@ -46,7 +46,8 @@
#define MXS_BCH_BASE (APBH_DMA_ARB_BASE_ADDR + 0x04000)
/* GPV - PL301 configuration ports */
-#if (defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL) || \
+#if (defined(CONFIG_MX6SX) || \
+ defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) || \
defined(CONFIG_MX6SL) || defined(CONFIG_MX6SLL))
#define GPV2_BASE_ADDR 0x00D00000
#define GPV3_BASE_ADDR 0x00E00000
@@ -88,7 +89,7 @@
#define QSPI0_AMBA_END 0x6FFFFFFF
#define QSPI1_AMBA_BASE 0x70000000
#define QSPI1_AMBA_END 0x7FFFFFFF
-#elif defined(CONFIG_MX6UL)
+#elif (defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL))
#define WEIM_ARB_BASE_ADDR 0x50000000
#define WEIM_ARB_END_ADDR 0x57FFFFFF
#define QSPI0_AMBA_BASE 0x60000000
@@ -109,7 +110,8 @@
#endif
#if (defined(CONFIG_MX6SLL) || defined(CONFIG_MX6SL) || \
- defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL))
+ defined(CONFIG_MX6SX) || \
+ defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL))
#define MMDC0_ARB_BASE_ADDR 0x80000000
#define MMDC0_ARB_END_ADDR 0xFFFFFFFF
#define MMDC1_ARB_BASE_ADDR 0xC0000000
@@ -262,7 +264,7 @@
#define MMDC_P0_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x30000)
/* i.MX6SL/SLL */
#define RNGB_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x34000)
-#ifdef CONFIG_MX6UL
+#if (defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL))
#define ENET2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x34000)
#else
/* i.MX6SX */
@@ -288,7 +290,8 @@
#define IP2APB_PERFMON3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4C000)
#endif
#define IP2APB_TZASC1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x50000)
-#ifdef CONFIG_MX6UL
+#if (defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL))
+#define SCTR_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x5C000)
#define QSPI0_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x60000)
#define UART6_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x7C000)
#elif defined(CONFIG_MX6SX)
@@ -337,7 +340,7 @@
#define PWM6_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xA8000)
#define PWM7_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xAC000)
#define PWM8_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xB0000)
-#elif defined(CONFIG_MX6ULL)
+#elif (defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL))
#define AIPS3_CONFIG_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x7C000)
#define DCP_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x80000)
#define RNGB_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x84000)
@@ -354,7 +357,8 @@
#define MX6SX_LCDIF1_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x20000)
#define MX6SX_WDOG3_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x88000)
-#if !(defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL) || \
+#if !(defined(CONFIG_MX6SX) || \
+ defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) || \
defined(CONFIG_MX6SLL) || defined(CONFIG_MX6SL))
#define IRAM_SIZE 0x00040000
#else
@@ -573,7 +577,7 @@ struct src {
#define IOMUXC_GPR12_LOS_LEVEL (0x1f << 4)
struct iomuxc {
-#if (defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL))
+#if (defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL))
u8 reserved[0x4000];
#endif
u32 gpr[14];
@@ -700,7 +704,7 @@ struct cspi_regs {
#define MXC_CSPICON_SSPOL 12 /* SS polarity */
#define MXC_CSPICON_CTL 20 /* inactive state of SCLK */
#if defined(CONFIG_MX6SLL) || defined(CONFIG_MX6SL) || \
- defined(CONFIG_MX6DL) || defined(CONFIG_MX6UL)
+ defined(CONFIG_MX6DL) || defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL)
#define MXC_SPI_BASE_ADDRESSES \
ECSPI1_BASE_ADDR, \
ECSPI2_BASE_ADDR, \
diff --git a/arch/arm/include/asm/arch-mx6/mx6-ddr.h b/arch/arm/include/asm/arch-mx6/mx6-ddr.h
index 2a8d4431eaacc2fc9c1763527df43a601aef3191..19d2f1d9c58bdc63f7becb991f36374cfd696512 100644
--- a/arch/arm/include/asm/arch-mx6/mx6-ddr.h
+++ b/arch/arm/include/asm/arch-mx6/mx6-ddr.h
@@ -16,7 +16,7 @@
#ifdef CONFIG_MX6SX
#include "mx6sx-ddr.h"
#else
-#ifdef CONFIG_MX6UL
+#if defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL)
#include "mx6ul-ddr.h"
#else
#ifdef CONFIG_MX6SL
diff --git a/arch/arm/include/asm/arch-mx6/mx6ul-ddr.h b/arch/arm/include/asm/arch-mx6/mx6ul-ddr.h
index ed11c4bb4debfceba995763e1d412253e2e47517..518b81208a3e0f05be21a11e6d4de2dbbeaaa5fb 100644
--- a/arch/arm/include/asm/arch-mx6/mx6ul-ddr.h
+++ b/arch/arm/include/asm/arch-mx6/mx6ul-ddr.h
@@ -7,7 +7,7 @@
#ifndef __ASM_ARCH_MX6UL_DDR_H__
#define __ASM_ARCH_MX6UL_DDR_H__
-#ifndef CONFIG_MX6UL
+#if !(defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL))
#error "wrong CPU"
#endif
diff --git a/arch/arm/include/asm/mach-imx/iomux-v3.h b/arch/arm/include/asm/mach-imx/iomux-v3.h
index ad35e0109e4da897d2fe9bfd69f4121a1eee139a..ed75e9cd9ad95109f47071b0e2c9253ad052e520 100644
--- a/arch/arm/include/asm/mach-imx/iomux-v3.h
+++ b/arch/arm/include/asm/mach-imx/iomux-v3.h
@@ -127,7 +127,7 @@ typedef u64 iomux_v3_cfg_t;
#define PAD_CTL_ODE (1 << 11)
-#if defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL)
+#if defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL)
#define PAD_CTL_SPEED_LOW (0 << 6)
#else
#define PAD_CTL_SPEED_LOW (1 << 6)
@@ -253,7 +253,7 @@ if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D)) { \
imx_iomux_v3_setup_pad(MX6Q_##def);
#define SETUP_IOMUX_PADS(x) \
imx_iomux_v3_setup_multiple_pads(x, ARRAY_SIZE(x))
-#elif defined(CONFIG_MX6UL)
+#elif defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL)
#define IOMUX_PADS(x) MX6_##x
#define SETUP_IOMUX_PAD(def) \
imx_iomux_v3_setup_pad(MX6_##def);
diff --git a/arch/arm/include/asm/mach-imx/regs-lcdif.h b/arch/arm/include/asm/mach-imx/regs-lcdif.h
index 4de401bd22b438fea5ec34e3da6eca307ad51e51..c6cf03bf5a48d3e86a048119b2b8913cc6db5844 100644
--- a/arch/arm/include/asm/mach-imx/regs-lcdif.h
+++ b/arch/arm/include/asm/mach-imx/regs-lcdif.h
@@ -19,8 +19,11 @@
struct mxs_lcdif_regs {
mxs_reg_32(hw_lcdif_ctrl) /* 0x00 */
mxs_reg_32(hw_lcdif_ctrl1) /* 0x10 */
-#if defined(CONFIG_MX28) || defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL) || \
- defined(CONFIG_MX7) || defined(CONFIG_MX6SL) || defined(CONFIG_MX6SLL)
+
+#if defined(CONFIG_MX28) || defined(CONFIG_MX6SX) || \
+ defined(CONFIG_MX6SL) || defined(CONFIG_MX6SLL) || \
+ defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) || \
+ defined(CONFIG_MX7)
mxs_reg_32(hw_lcdif_ctrl2) /* 0x20 */
#endif
mxs_reg_32(hw_lcdif_transfer_count) /* 0x20/0x30 */
@@ -55,8 +58,10 @@ struct mxs_lcdif_regs {
#endif
mxs_reg_32(hw_lcdif_data) /* 0x1b0/0x180 */
mxs_reg_32(hw_lcdif_bm_error_stat) /* 0x1c0/0x190 */
-#if defined(CONFIG_MX28) || defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL) || \
- defined(CONFIG_MX7) || defined(CONFIG_MX6SL) || defined(CONFIG_MX6SLL)
+#if defined(CONFIG_MX28) || defined(CONFIG_MX6SX) || \
+ defined(CONFIG_MX6SL) || defined(CONFIG_MX6SLL) || \
+ defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) || \
+ defined(CONFIG_MX7)
mxs_reg_32(hw_lcdif_crc_stat) /* 0x1a0 */
#endif
mxs_reg_32(hw_lcdif_lcdif_stat) /* 0x1d0/0x1b0 */
@@ -64,8 +69,10 @@ struct mxs_lcdif_regs {
mxs_reg_32(hw_lcdif_debug0) /* 0x1f0/0x1d0 */
mxs_reg_32(hw_lcdif_debug1) /* 0x200/0x1e0 */
mxs_reg_32(hw_lcdif_debug2) /* 0x1f0 */
-#if defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL) || defined(CONFIG_MX7) || \
- defined(CONFIG_MX6SL) || defined(CONFIG_MX6SLL)
+#if defined(CONFIG_MX6SX) || \
+ defined(CONFIG_MX6SL) || defined(CONFIG_MX6SLL) || \
+ defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) || \
+ defined(CONFIG_MX7)
mxs_reg_32(hw_lcdif_thres)
mxs_reg_32(hw_lcdif_as_ctrl)
mxs_reg_32(hw_lcdif_as_buf)
diff --git a/arch/arm/include/asm/mach-imx/sys_proto.h b/arch/arm/include/asm/mach-imx/sys_proto.h
index 5184e0097231ca842033ab315424b23fadca5975..d518e038091ade05aeb8cdac0ee7670ab1620294 100644
--- a/arch/arm/include/asm/mach-imx/sys_proto.h
+++ b/arch/arm/include/asm/mach-imx/sys_proto.h
@@ -81,7 +81,8 @@ enum imx6_bmode {
IMX6_BMODE_ESD,
IMX6_BMODE_MMC,
IMX6_BMODE_EMMC,
- IMX6_BMODE_NAND,
+ IMX6_BMODE_NAND_MIN,
+ IMX6_BMODE_NAND_MAX = 0xf,
};
static inline u8 imx6_is_bmode_from_gpr9(void)
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index e687048b3122b0cd763040423bf4b7e6463332e1..3aec89d440a013be33edd5acebc37033f7179494 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -7,6 +7,12 @@ config IMX_CONFIG
config ROM_UNIFIED_SECTIONS
bool
+config SYSCOUNTER_TIMER
+ bool
+
+config GPT_TIMER
+ bool
+
config IMX_RDC
bool "i.MX Resource domain controller driver"
depends on ARCH_MX6 || ARCH_MX7
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index d77c10e176845965f98bf18b674f6654eac10e61..d7966cfd4ad15c80f6809a89671bf426ab98d28b 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -11,7 +11,8 @@ ifeq ($(SOC),$(filter $(SOC),mx25 mx35 mx5 mx6 mx7 vf610))
obj-y = iomux-v3.o
endif
ifeq ($(SOC),$(filter $(SOC),mx5 mx6))
-obj-y += timer.o cpu.o speed.o
+obj-y += cpu.o speed.o
+obj-$(CONFIG_GPT_TIMER) += timer.o
obj-$(CONFIG_SYS_I2C_MXC) += i2c-mxv7.o
endif
ifeq ($(SOC),$(filter $(SOC),mx7 mx6 mxs))
@@ -21,7 +22,6 @@ endif
ifeq ($(SOC),$(filter $(SOC),mx7))
obj-y += cpu.o
obj-$(CONFIG_SYS_I2C_MXC) += i2c-mxv7.o
-obj-$(CONFIG_SYSCOUNTER_TIMER) += syscounter.o
endif
ifeq ($(SOC),$(filter $(SOC),mx6 mx7))
obj-y += cache.o init.o
@@ -30,6 +30,7 @@ obj-$(CONFIG_IMX_VIDEO_SKIP) += video.o
obj-$(CONFIG_IMX_RDC) += rdc-sema.o
obj-$(CONFIG_IMX_BOOTAUX) += imx_bootaux.o
obj-$(CONFIG_SECURE_BOOT) += hab.o
+obj-$(CONFIG_SYSCOUNTER_TIMER) += syscounter.o
endif
ifeq ($(SOC),$(filter $(SOC),mx7ulp))
obj-y += cache.o
diff --git a/arch/arm/mach-imx/mx5/Kconfig b/arch/arm/mach-imx/mx5/Kconfig
index 250194b6231c5f33cf852b05233695eea5de8d0c..3ce6bcfc88930225c205ce1a7015fa97de3975c2 100644
--- a/arch/arm/mach-imx/mx5/Kconfig
+++ b/arch/arm/mach-imx/mx5/Kconfig
@@ -1,6 +1,7 @@
if ARCH_MX5
config MX5
+ select GPT_TIMER
bool
default y
diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig
index 58ee20a8b603e2277b96effd7109d18e2cdfcb0a..567a6a6bf56bdd94fde6685a60d3e41224c1b282 100644
--- a/arch/arm/mach-imx/mx6/Kconfig
+++ b/arch/arm/mach-imx/mx6/Kconfig
@@ -8,7 +8,8 @@ config MX6_SMP
bool
config MX6
- select ARM_ERRATA_743622 if !MX6UL
+ select ARM_ERRATA_743622 if !MX6UL && !MX6ULL
+ select GPT_TIMER if !MX6UL && !MX6ULL
bool
default y
imply CMD_FUSE
@@ -53,6 +54,7 @@ config MX6UL
select HAS_CAAM
select SYS_L2CACHE_OFF
select ROM_UNIFIED_SECTIONS
+ select SYSCOUNTER_TIMER
bool
config MX6UL_LITESOM
@@ -75,6 +77,7 @@ config MX6UL_OPOS6UL
config MX6ULL
select SYS_L2CACHE_OFF
select ROM_UNIFIED_SECTIONS
+ select SYSCOUNTER_TIMER
bool
config MX6_DDRCAL
@@ -210,6 +213,14 @@ config TARGET_MX6LOGICPD
select DM_REGULATOR
select OF_CONTROL
+config TARGET_MX6MEMCAL
+ bool "mx6memcal"
+ select SUPPORT_SPL
+ help
+ The mx6memcal board is a virtual board that can be used to validate
+ and characterize the memory layout of a new design during the initial
+ development and pre-production stages.
+
config TARGET_MX6QARM2
bool "mx6qarm2"
@@ -452,6 +463,7 @@ source "board/embest/mx6boards/Kconfig"
source "board/engicam/imx6q/Kconfig"
source "board/engicam/imx6ul/Kconfig"
source "board/freescale/mx6qarm2/Kconfig"
+source "board/freescale/mx6memcal/Kconfig"
source "board/freescale/mx6sabreauto/Kconfig"
source "board/freescale/mx6sabresd/Kconfig"
source "board/freescale/mx6slevk/Kconfig"
diff --git a/arch/arm/mach-imx/mx6/ddr.c b/arch/arm/mach-imx/mx6/ddr.c
index 0cf391eb9ca9206eec6e85fce468951983d27e26..52a9a259040075b24aacd704197d463feef4ad0b 100644
--- a/arch/arm/mach-imx/mx6/ddr.c
+++ b/arch/arm/mach-imx/mx6/ddr.c
@@ -631,7 +631,7 @@ void mx6sx_dram_iocfg(unsigned width,
}
#endif
-#ifdef CONFIG_MX6UL
+#if defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL)
void mx6ul_dram_iocfg(unsigned width,
const struct mx6ul_iomux_ddr_regs *ddr,
const struct mx6ul_iomux_grp_regs *grp)
diff --git a/arch/arm/mach-imx/mx7/Kconfig b/arch/arm/mach-imx/mx7/Kconfig
index 4f8b4e138e3d9c99adcd97b980d79b2ecfe0c129..2a3db860bbcfeb7314a395dba61f37ee277d0c4e 100644
--- a/arch/arm/mach-imx/mx7/Kconfig
+++ b/arch/arm/mach-imx/mx7/Kconfig
@@ -3,6 +3,7 @@ if ARCH_MX7
config MX7
bool
select ROM_UNIFIED_SECTIONS
+ select SYSCOUNTER_TIMER
select CPU_V7_HAS_VIRT
select CPU_V7_HAS_NONSEC
select ARCH_SUPPORT_PSCI
diff --git a/arch/arm/mach-imx/spl.c b/arch/arm/mach-imx/spl.c
index d0d1b73aa638bd12130e380b47a086e6ccaf8d55..723f51fad3d8cd99ce019d39919fdf867888453d 100644
--- a/arch/arm/mach-imx/spl.c
+++ b/arch/arm/mach-imx/spl.c
@@ -91,7 +91,7 @@ u32 spl_boot_device(void)
case IMX6_BMODE_EMMC:
return BOOT_DEVICE_MMC1;
/* NAND Flash: 8.5.2, Table 8-10 */
- case IMX6_BMODE_NAND:
+ case IMX6_BMODE_NAND_MIN ... IMX6_BMODE_NAND_MAX:
return BOOT_DEVICE_NAND;
}
return BOOT_DEVICE_NONE;
diff --git a/board/engicam/common/board.c b/board/engicam/common/board.c
index f633c719163e726c59b07d4eeac212dc882fac9e..1bdd833196739a2cc297742bf3b9457f5454813c 100644
--- a/board/engicam/common/board.c
+++ b/board/engicam/common/board.c
@@ -69,7 +69,7 @@ int board_late_init(void)
#endif
env_set("modeboot", "mmcboot");
break;
- case IMX6_BMODE_NAND:
+ case IMX6_BMODE_NAND_MIN ... IMX6_BMODE_NAND_MAX:
env_set("modeboot", "nandboot");
break;
default:
diff --git a/board/engicam/icorem6_rqs/icorem6_rqs.c b/board/engicam/icorem6_rqs/icorem6_rqs.c
deleted file mode 100644
index a55a754bc7aa015f64bb572b277df69ddc08bcc8..0000000000000000000000000000000000000000
--- a/board/engicam/icorem6_rqs/icorem6_rqs.c
+++ /dev/null
@@ -1,48 +0,0 @@
-/*
- * Copyright (C) 2016 Amarula Solutions B.V.
- * Copyright (C) 2016 Engicam S.r.l.
- * Author: Jagan Teki <jagan@amarulasolutions.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <asm/arch/sys_proto.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#ifdef CONFIG_ENV_IS_IN_MMC
-int board_mmc_get_env_dev(int devno)
-{
- return devno - 1;
-}
-#endif
-
-#ifdef CONFIG_SPL_BUILD
-#include <spl.h>
-
-#ifdef CONFIG_ENV_IS_IN_MMC
-void board_boot_order(u32 *spl_boot_list)
-{
- u32 bmode = imx6_src_get_boot_mode();
- u8 boot_dev = BOOT_DEVICE_MMC1;
-
- switch ((bmode & IMX6_BMODE_MASK) >> IMX6_BMODE_SHIFT) {
- case IMX6_BMODE_SD:
- case IMX6_BMODE_ESD:
- /* SD/eSD - BOOT_DEVICE_MMC1 */
- break;
- case IMX6_BMODE_MMC:
- case IMX6_BMODE_EMMC:
- /* MMC/eMMC */
- boot_dev = BOOT_DEVICE_MMC2;
- break;
- default:
- /* Default - BOOT_DEVICE_MMC1 */
- printf("Wrong board boot order\n");
- break;
- }
-
- spl_boot_list[0] = boot_dev;
-}
-#endif
-#endif /* CONFIG_SPL_BUILD */
diff --git a/board/freescale/mx6memcal/Kconfig b/board/freescale/mx6memcal/Kconfig
new file mode 100644
index 0000000000000000000000000000000000000000..443804dc11ca8f25c815b2c4278c8878eed23eab
--- /dev/null
+++ b/board/freescale/mx6memcal/Kconfig
@@ -0,0 +1,235 @@
+if TARGET_MX6MEMCAL
+
+config SYS_BOARD
+ default "mx6memcal"
+
+config SYS_VENDOR
+ default "freescale"
+
+config SYS_CONFIG_NAME
+ default "mx6memcal"
+
+menu "mx6memcal specifics"
+choice
+ prompt "Serial console"
+ help
+ Either UART1 or UART2 will be used as the console for
+ displaying the calibration values or errors.
+
+config SERIAL_CONSOLE_UART1
+ bool "UART1"
+ help
+ Select this if your board uses UART1 for its' console.
+
+config SERIAL_CONSOLE_UART2
+ bool "UART2"
+ help
+ Select this if your board uses UART2 for its' console.
+
+endchoice
+
+choice
+ prompt "UART pads"
+ help
+ Select the RX and TX pads used for your serial console.
+ The choices below reflect the most commonly used options
+ for your UART.
+
+ config UART2_EIM_D26_27
+ bool "UART2 on EIM_D26/27 (SabreLite, Nitrogen6x)"
+ depends on SERIAL_CONSOLE_UART2
+ help
+ Choose this configuration if you're using pads
+ EIM_D26 and D27 for a console on UART2.
+ This is typical for designs that are based on the
+ NXP SABRELite.
+
+ config UART1_CSI0_DAT10_11
+ bool "UART1 on CSI0_DAT10/11 (Wand)"
+ depends on SERIAL_CONSOLE_UART1
+ help
+ Choose this configuration if you're using pads
+ CSI0_DAT10 and DAT11 for a console on UART1 as
+ is done on the i.MX6 Wand board.
+
+ config UART1_SD3_DAT6_7
+ bool "UART1 on SD3_DAT6/7 (SabreSD, SabreAuto)"
+ depends on SERIAL_CONSOLE_UART1
+ help
+ Choose this configuration if you're using pads
+ SD3_DAT6 and DAT7 for a console on UART1 as is
+ done on the NXP SABRESD or SABREAUTO designs.
+
+ config UART1_UART1
+ bool "UART1 on UART1 (i.MX6SL EVK, WaRP)"
+ depends on SERIAL_CONSOLE_UART1
+ help
+ Choose this configuration if you're using pads
+ UART1_TXD/RXD for a console on UART1 as is done
+ on most i.MX6SL designs.
+
+endchoice
+
+config IMXIMAGE_OUTPUT
+ bool "Include output for imximage .cfg files"
+ default y
+ help
+ Say "Y" if you want output formatted for use in non-SPL
+ (DCD-style) configuration files.
+
+config DDRWIDTH
+ int "DDR bus width"
+ default 64
+ help
+ Select either 32 or 64 to reflect the DDR bus width.
+
+config DDRCS
+ int "DDR chip selects"
+ default 2
+ range 1 2
+ help
+ Select the number of chip selects used in your board design
+
+choice
+ prompt "Memory type"
+ help
+ Select the type of DDR (DDR3 or LPDDR2) used on your design
+
+config DDR3
+ bool "DDR3"
+ help
+ Select this if your board design uses DDR3.
+
+config LPDDR2
+ bool "LPDDR2"
+ help
+ Select this if your board design uses LPDDR2.
+
+endchoice
+
+choice
+ prompt "Memory device"
+
+config MT41K512M16TNA
+ bool "Micron MT41K512M16TNA 512Mx16 (1GiB/chip)"
+ depends on DDR3
+
+config MT41K128M16JT
+ bool "Micron MT41K128M16JT 128Mx16 (256 MiB/chip)"
+ depends on DDR3
+
+config H5TQ4G63AFR
+ bool "Hynix H5TQ4G63AFR 256Mx16 (512 MiB/chip)"
+ depends on DDR3
+
+config H5TQ2G63DFR
+ bool "Hynix H5TQ2G63DFR 128Mx16 (256 MiB/chip)"
+ depends on DDR3
+
+config MT42L256M32D2LG
+ bool "Micron MT42L256M32D2LG LPDDR2 256Mx32 (1GiB/chip)"
+ depends on LPDDR2
+
+config MT29PZZZ4D4BKESK
+ bool "Micron MT29PZZZ4D4BKESK multi-chip 512MiB LPDDR2/4GiB eMMC"
+ depends on LPDDR2
+
+endchoice
+
+config DDR_ODT
+ int "DDR On-die-termination"
+ default 2
+ range 0 7
+ help
+ Enter the on-die termination value as an index defined for
+ IOMUX settings for PAD_DRAM_SDCLK0_P and others.
+ 0 == Disabled
+ 1 == 120 Ohm
+ 2 == 60 Ohm
+ 3 == 40 Ohm
+ 4 == 30 Ohm
+ 5 == 24 Ohm
+ 6 == 20 Ohm
+ 7 == 17 Ohm
+ Value will be applied to all clock and data lines
+
+
+config DRAM_DRIVE_STRENGTH
+ int "DRAM Drive strength"
+ default 6
+ range 0 7
+ help
+ Enter drive strength as an index defined for IOMUX settings
+ for GRP_B1DS and others.
+ 0 == Hi Z
+ 6 == 40 Ohm (default)
+ 7 == 34 Ohm
+ Value will be applied to all clock and data lines
+
+config RTT_NOM
+ int "RTT_NOM"
+ default 1
+ range 1 2
+ help
+ Enter the RTT_NOM selector
+ 1 == RZQ/4 (60ohm)
+ 2 == RZQ/2 (120ohm)
+
+config RTT_WR
+ int "RTT_WR"
+ default 1
+ range 0 2
+ help
+ Enter the RTT_WR selector for MR2
+ 0 == Dynamic ODT disabled
+ 1 == RZQ/4 (60ohm)
+ 2 == RZQ/2 (120ohm)
+
+config RALAT
+ int "Read additional latency"
+ default 5
+ range 0 7
+ help
+ Enter a latency in number of cycles. This will be added to
+ CAS and internal delays for which the MMDC will retrieve the
+ read data from the internal FIFO.
+ This is used to compensate for board/chip delays.
+
+config WALAT
+ int "Write additional latency"
+ default 0
+ range 0 7
+ help
+ Enter a latency in number of cycles. This will be added to
+ CAS and internal delays for which the MMDC will retrieve the
+ read data from the internal FIFO
+ This is used to compensate for board/chip delays.
+
+config REFSEL
+ int "Refresh period"
+ range 0 3
+ default 1
+ help
+ Select the DDR refresh period.
+ See the description of bitfield REF_SEL in the reference manual
+ for details.
+ 0 == disabled
+ 1 == 32 kHz
+ 2 == 64 kHz
+ 3 == fast counter
+
+config REFR
+ int "Number of refreshes"
+ range 0 7
+ default 7
+ help
+ This selects the number of refreshes (-1) during each period.
+ i.e.:
+ 0 == 1 refresh (tRFC)
+ 7 == 8 refreshes (tRFC*8)
+ See the description of MDREF[REFR] in the reference manual for
+ details.
+
+endmenu
+endif
+
diff --git a/board/freescale/mx6memcal/MAINTAINERS b/board/freescale/mx6memcal/MAINTAINERS
new file mode 100644
index 0000000000000000000000000000000000000000..5da38f7109b3c3dd5f15e3cbc04e2a19ff3f0f74
--- /dev/null
+++ b/board/freescale/mx6memcal/MAINTAINERS
@@ -0,0 +1,7 @@
+MX6MEMCAL BOARD
+M: Eric Nelson <eric@nelint.com>
+S: Maintained
+F: board/freescale/mx6memcal/
+F: include/configs/mx6memcal.h
+F: configs/mx6memcal_defconfig
+
diff --git a/board/freescale/mx6memcal/Makefile b/board/freescale/mx6memcal/Makefile
new file mode 100644
index 0000000000000000000000000000000000000000..2d7a6fa5d99bd98835b13b12a0a43cb21e77fde4
--- /dev/null
+++ b/board/freescale/mx6memcal/Makefile
@@ -0,0 +1,13 @@
+#
+# Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
+#
+# (C) Copyright 2011 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+ifdef CONFIG_SPL_BUILD
+obj-y := spl.o
+else
+obj-y := mx6memcal.o
+endif
diff --git a/board/freescale/mx6memcal/README b/board/freescale/mx6memcal/README
new file mode 100644
index 0000000000000000000000000000000000000000..9fe2fe2d0431964993ddac7cc321be4f1f073c76
--- /dev/null
+++ b/board/freescale/mx6memcal/README
@@ -0,0 +1,49 @@
+mx6memcal - a tool for calibrating DDR on i.MX6 boards.
+
+The mx6memcal board isn't a real board, but a tool for use in bring-up of
+new i.MX6 board designs.
+
+It provides a similar function to the tool from NXP([1]) with a number
+of advantages:
+
+1. It's open-source, so it's easier to change if needed.
+ Typical reasons for needing to change include the use of alternate
+ UARTs and PMIC initialization.
+2. It produces an image that's directly loadable with imx_usb [2] or
+ SB_LOADER.exe [3].
+ The NXP tool requires either a cumbersome JTAG connection that
+ makes running the DDR very slow or a working U-Boot image that
+ suffers from a chicken-and-egg problem (i.e. where do you get the
+ DDR parameters for U-Boot?).
+3. It doesn't prompt for parameters, so it's much faster to gather
+ data from multiple boards.
+4. Parameters to the calibration process can be chosen through
+ 'make menuconfig'.
+
+When booted, the mx6memcal board will run the DDR calibration
+routines and display the result in a form suitable for cut and
+paste into struct mx6_mmdc_calibration. It can also optionally
+produce output in a form usable in a DCD-style .cfg file.
+
+Selections in Kconfig allow most system design settings to be chosen:
+
+1. The UART number and pad configuration for the UART. Options
+ include support for the most frequent reference designs on
+ i.MX6DQ/SDL (SABRE Lite and SABRESD designs).
+2. The memory bus width (64 and 32-bit)
+3. The number of chip-selects in use
+4. The type of DDR (DDR3 or LPDDR2). Note that LPDDR2 support
+ is incomplete as of this writing.
+5. The type of DDR chips in use. This selection allows re-use of common
+ parts and four DDR3 and two LPDDR2 parts are currently defined
+6. The On-die termination value for the DRAM lines
+7. The DRAM drive strength
+8. The RTT_NOM and RTT_WR termination settings
+9. RALAT/WALAT latency values
+
+References:
+[1] - NXP DDR Stress Test Tool - https://community.nxp.com/docs/DOC-105652
+[2] - Boundary Devices imx_usb_loader
+ https://github.com/boundarydevices/imx_usb_loader
+[3] - Use of SB_Loader.exe
+ https://boundarydevices.com/windows-users-and-unbricking
diff --git a/board/freescale/mx6memcal/mx6memcal.c b/board/freescale/mx6memcal/mx6memcal.c
new file mode 100644
index 0000000000000000000000000000000000000000..afea0fbd9d21dfbe659268c2d22c3beee01be0a3
--- /dev/null
+++ b/board/freescale/mx6memcal/mx6memcal.c
@@ -0,0 +1,32 @@
+/*
+ * mx6memcal board support - provides a minimal, UART-only
+ * U-Boot that's capable of running a memory test.
+ *
+ * Copyright (C) 2016 Nelson Integration, LLC
+ * Author: Eric Nelson <eric@nelint.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/sys_proto.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_init(void)
+{
+ return 0;
+}
+
+int checkboard(void)
+{
+ puts("Board: mx6memcal\n");
+ return 0;
+}
+
+int dram_init(void)
+{
+ gd->ram_size = imx_ddr_size();
+ return 0;
+}
+
diff --git a/board/freescale/mx6memcal/spl.c b/board/freescale/mx6memcal/spl.c
new file mode 100644
index 0000000000000000000000000000000000000000..8ee89ff1161103a53141709d27ffaee00e62ab7d
--- /dev/null
+++ b/board/freescale/mx6memcal/spl.c
@@ -0,0 +1,456 @@
+/*
+ * Copyright (C) 2016 Nelson Integration, LLC
+ * Author: Eric Nelson <eric@nelint.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/mx6-ddr.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/arch/sys_proto.h>
+#include <spl.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
+ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
+ PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+
+static iomux_v3_cfg_t const uart_pads[] = {
+#ifdef CONFIG_UART2_EIM_D26_27
+ IOMUX_PADS(PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
+#elif defined(CONFIG_UART1_CSI0_DAT10_11)
+ IOMUX_PADS(PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
+ IOMUX_PADS(PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
+#elif defined(CONFIG_UART1_SD3_DAT6_7)
+ IOMUX_PADS(PAD_SD3_DAT6__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD3_DAT7__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
+#elif defined(CONFIG_UART1_UART1)
+ MX6_PAD_UART1_TXD__UART1_TXD | MUX_PAD_CTRL(UART_PAD_CTRL),
+ MX6_PAD_UART1_RXD__UART1_RXD | MUX_PAD_CTRL(UART_PAD_CTRL),
+#else
+#error select UART console pads
+#endif
+};
+
+#ifdef CONFIG_DDR3
+#define GRP_DDRTYPE 0x000C0000
+#else
+#define GRP_DDRTYPE 0x00080000
+#endif
+
+/* all existing designs have this disabled */
+#define DDR_PKE 0
+
+/* use Kconfig for ODT and DRIVE_STRENGTH */
+#define DDR_ODT \
+ (CONFIG_DDR_ODT << 8)
+#define DRAM_DRIVE_STRENGTH \
+ (CONFIG_DRAM_DRIVE_STRENGTH << 3)
+
+/* configure MX6Q/DUAL mmdc DDR io registers */
+static struct mx6dq_iomux_ddr_regs const mx6dq_ddr_ioregs = {
+ /* SDCLK[0:1], CAS, RAS, Reset: Differential input, 40ohm */
+ .dram_sdclk_0 = DDR_ODT + DRAM_DRIVE_STRENGTH,
+ .dram_sdclk_1 = DDR_ODT + DRAM_DRIVE_STRENGTH,
+ .dram_cas = DDR_ODT + DRAM_DRIVE_STRENGTH,
+ .dram_ras = DDR_ODT + DRAM_DRIVE_STRENGTH,
+ .dram_reset = DDR_ODT + DRAM_DRIVE_STRENGTH,
+ /* SDCKE[0:1]: 100k pull-up */
+ .dram_sdcke0 = 0x00003000,
+ .dram_sdcke1 = 0x00003000,
+ /* SDBA2: pull-up disabled */
+ .dram_sdba2 = 0x00000000,
+ /* SDODT[0:1]: 100k pull-up, 40 ohm */
+ .dram_sdodt0 = 0x00003000 + DRAM_DRIVE_STRENGTH,
+ .dram_sdodt1 = 0x00003000 + DRAM_DRIVE_STRENGTH,
+ /* SDQS[0:7]: Differential input, 40 ohm */
+ .dram_sdqs0 = DRAM_DRIVE_STRENGTH,
+ .dram_sdqs1 = DRAM_DRIVE_STRENGTH,
+ .dram_sdqs2 = DRAM_DRIVE_STRENGTH,
+ .dram_sdqs3 = DRAM_DRIVE_STRENGTH,
+ .dram_sdqs4 = DRAM_DRIVE_STRENGTH,
+ .dram_sdqs5 = DRAM_DRIVE_STRENGTH,
+ .dram_sdqs6 = DRAM_DRIVE_STRENGTH,
+ .dram_sdqs7 = DRAM_DRIVE_STRENGTH,
+
+ /* DQM[0:7]: Differential input, 40 ohm */
+ .dram_dqm0 = DDR_ODT + DRAM_DRIVE_STRENGTH,
+ .dram_dqm1 = DDR_ODT + DRAM_DRIVE_STRENGTH,
+ .dram_dqm2 = DDR_ODT + DRAM_DRIVE_STRENGTH,
+ .dram_dqm3 = DDR_ODT + DRAM_DRIVE_STRENGTH,
+ .dram_dqm4 = DDR_ODT + DRAM_DRIVE_STRENGTH,
+ .dram_dqm5 = DDR_ODT + DRAM_DRIVE_STRENGTH,
+ .dram_dqm6 = DDR_ODT + DRAM_DRIVE_STRENGTH,
+ .dram_dqm7 = DDR_ODT + DRAM_DRIVE_STRENGTH,
+};
+
+/* configure MX6Q/DUAL mmdc GRP io registers */
+static struct mx6dq_iomux_grp_regs const mx6dq_grp_ioregs = {
+ /* DDR3 */
+ .grp_ddr_type = GRP_DDRTYPE,
+ .grp_ddrmode_ctl = DDR_ODT,
+ /* disable DDR pullups */
+ .grp_ddrpke = DDR_PKE,
+ /* ADDR[00:16], SDBA[0:1]: 40 ohm */
+ .grp_addds = DRAM_DRIVE_STRENGTH,
+ /* CS0/CS1/SDBA2/CKE0/CKE1/SDWE: 40 ohm */
+ .grp_ctlds = DRAM_DRIVE_STRENGTH,
+ /* DATA[00:63]: Differential input, 40 ohm */
+ .grp_ddrmode = DDR_ODT,
+ .grp_b0ds = DRAM_DRIVE_STRENGTH,
+ .grp_b1ds = DRAM_DRIVE_STRENGTH,
+ .grp_b2ds = DRAM_DRIVE_STRENGTH,
+ .grp_b3ds = DRAM_DRIVE_STRENGTH,
+ .grp_b4ds = DRAM_DRIVE_STRENGTH,
+ .grp_b5ds = DRAM_DRIVE_STRENGTH,
+ .grp_b6ds = DRAM_DRIVE_STRENGTH,
+ .grp_b7ds = DRAM_DRIVE_STRENGTH,
+};
+
+static struct mx6sdl_iomux_ddr_regs const mx6sdl_ddr_ioregs = {
+ /* SDCLK[0:1], CAS, RAS, Reset: Differential input, 40ohm */
+ .dram_sdclk_0 = DDR_ODT + DRAM_DRIVE_STRENGTH,
+ .dram_sdclk_1 = DDR_ODT + DRAM_DRIVE_STRENGTH,
+ .dram_cas = DDR_ODT + DRAM_DRIVE_STRENGTH,
+ .dram_ras = DDR_ODT + DRAM_DRIVE_STRENGTH,
+ .dram_reset = DDR_ODT + DRAM_DRIVE_STRENGTH,
+ /* SDCKE[0:1]: 100k pull-up */
+ .dram_sdcke0 = 0x00003000,
+ .dram_sdcke1 = 0x00003000,
+ /* SDBA2: pull-up disabled */
+ .dram_sdba2 = 0x00000000,
+ /* SDODT[0:1]: 100k pull-up, 40 ohm */
+ .dram_sdodt0 = 0x00003000 + DRAM_DRIVE_STRENGTH,
+ .dram_sdodt1 = 0x00003000 + DRAM_DRIVE_STRENGTH,
+ /* SDQS[0:7]: Differential input, 40 ohm */
+ .dram_sdqs0 = DRAM_DRIVE_STRENGTH,
+ .dram_sdqs1 = DRAM_DRIVE_STRENGTH,
+ .dram_sdqs2 = DRAM_DRIVE_STRENGTH,
+ .dram_sdqs3 = DRAM_DRIVE_STRENGTH,
+ .dram_sdqs4 = DRAM_DRIVE_STRENGTH,
+ .dram_sdqs5 = DRAM_DRIVE_STRENGTH,
+ .dram_sdqs6 = DRAM_DRIVE_STRENGTH,
+ .dram_sdqs7 = DRAM_DRIVE_STRENGTH,
+
+ /* DQM[0:7]: Differential input, 40 ohm */
+ .dram_dqm0 = DDR_ODT + DRAM_DRIVE_STRENGTH,
+ .dram_dqm1 = DDR_ODT + DRAM_DRIVE_STRENGTH,
+ .dram_dqm2 = DDR_ODT + DRAM_DRIVE_STRENGTH,
+ .dram_dqm3 = DDR_ODT + DRAM_DRIVE_STRENGTH,
+ .dram_dqm4 = DDR_ODT + DRAM_DRIVE_STRENGTH,
+ .dram_dqm5 = DDR_ODT + DRAM_DRIVE_STRENGTH,
+ .dram_dqm6 = DDR_ODT + DRAM_DRIVE_STRENGTH,
+ .dram_dqm7 = DDR_ODT + DRAM_DRIVE_STRENGTH,
+};
+
+/* configure MX6SOLO/DUALLITE mmdc GRP io registers */
+static struct mx6sdl_iomux_grp_regs const mx6sdl_grp_ioregs = {
+ /* DDR3 */
+ .grp_ddr_type = GRP_DDRTYPE,
+ /* SDQS[0:7]: Differential input, 40 ohm */
+ .grp_ddrmode_ctl = DDR_ODT,
+ /* disable DDR pullups */
+ .grp_ddrpke = DDR_PKE,
+ /* ADDR[00:16], SDBA[0:1]: 40 ohm */
+ .grp_addds = DRAM_DRIVE_STRENGTH,
+ /* CS0/CS1/SDBA2/CKE0/CKE1/SDWE: 40 ohm */
+ .grp_ctlds = DRAM_DRIVE_STRENGTH,
+ /* DATA[00:63]: Differential input, 40 ohm */
+ .grp_ddrmode = DDR_ODT,
+ .grp_b0ds = DRAM_DRIVE_STRENGTH,
+ .grp_b1ds = DRAM_DRIVE_STRENGTH,
+ .grp_b2ds = DRAM_DRIVE_STRENGTH,
+ .grp_b3ds = DRAM_DRIVE_STRENGTH,
+ .grp_b4ds = DRAM_DRIVE_STRENGTH,
+ .grp_b5ds = DRAM_DRIVE_STRENGTH,
+ .grp_b6ds = DRAM_DRIVE_STRENGTH,
+ .grp_b7ds = DRAM_DRIVE_STRENGTH,
+};
+
+const struct mx6sl_iomux_ddr_regs mx6sl_ddr_ioregs = {
+ .dram_sdqs0 = DRAM_DRIVE_STRENGTH,
+ .dram_sdqs1 = DRAM_DRIVE_STRENGTH,
+ .dram_sdqs2 = DRAM_DRIVE_STRENGTH,
+ .dram_sdqs3 = DRAM_DRIVE_STRENGTH,
+ .dram_dqm0 = DRAM_DRIVE_STRENGTH,
+ .dram_dqm1 = DRAM_DRIVE_STRENGTH,
+ .dram_dqm2 = DRAM_DRIVE_STRENGTH,
+ .dram_dqm3 = DRAM_DRIVE_STRENGTH,
+ .dram_cas = DRAM_DRIVE_STRENGTH,
+ .dram_ras = DRAM_DRIVE_STRENGTH,
+ .dram_sdclk_0 = DRAM_DRIVE_STRENGTH,
+ .dram_reset = DRAM_DRIVE_STRENGTH,
+ .dram_sdba2 = 0x00020000,
+ .dram_odt0 = 0x00030000 + DRAM_DRIVE_STRENGTH,
+ .dram_odt1 = 0x00030000 + DRAM_DRIVE_STRENGTH,
+};
+
+const struct mx6sl_iomux_grp_regs mx6sl_grp_ioregs = {
+ .grp_b0ds = DRAM_DRIVE_STRENGTH,
+ .grp_b1ds = DRAM_DRIVE_STRENGTH,
+ .grp_b2ds = DRAM_DRIVE_STRENGTH,
+ .grp_b3ds = DRAM_DRIVE_STRENGTH,
+ .grp_addds = DRAM_DRIVE_STRENGTH,
+ .grp_ctlds = DRAM_DRIVE_STRENGTH,
+ .grp_ddrmode_ctl = DDR_ODT,
+ .grp_ddrpke = DDR_PKE,
+ .grp_ddrmode = DDR_ODT,
+ .grp_ddr_type = GRP_DDRTYPE,
+};
+
+static struct mx6_ddr_sysinfo const sysinfo = {
+ /* width of data bus:0=16,1=32,2=64 */
+#if CONFIG_DDRWIDTH == 32
+ .dsize = 1,
+#elif CONFIG_DDRWIDTH == 64
+ .dsize = 2,
+#else
+#error missing CONFIG_DDRWIDTH
+#endif
+ /* config for full 4GB range so that get_mem_size() works */
+ .cs_density = 32, /* 32Gb per CS */
+
+ /* # of chip selects */
+ .ncs = CONFIG_DDRCS,
+ .cs1_mirror = 0,
+ .bi_on = 1, /* Bank interleaving enabled */
+ .rtt_nom = CONFIG_RTT_NOM,
+ .rtt_wr = CONFIG_RTT_WR,
+ .ralat = CONFIG_RALAT, /* Read additional latency */
+ .walat = CONFIG_WALAT, /* Write additional latency */
+ .mif3_mode = 3, /* Command prediction working mode */
+#ifdef CONFIG_DDR3
+ .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
+ .sde_to_rst = 0x10, /* JEDEC value for LPDDR2 - 200us */
+ .pd_fast_exit = 0, /* immaterial for calibration */
+ .ddr_type = DDR_TYPE_DDR3,
+#else
+ .rst_to_cke = 0x10, /* JEDEC value for LPDDR2: 200us */
+ .sde_to_rst = 0, /* LPDDR2 does not need this field */
+ .pd_fast_exit = 0, /* immaterial for calibration */
+ .ddr_type = DDR_TYPE_LPDDR2,
+#endif
+ .refsel = CONFIG_REFSEL,
+ .refr = CONFIG_REFR,
+};
+
+#ifdef CONFIG_MT41K512M16TNA
+/* Micron MT41K512M16TNA-125 */
+static struct mx6_ddr3_cfg const ddrtype = {
+ .mem_speed = 1600,
+ .density = 8,
+ .width = 16,
+ .banks = 8,
+ .rowaddr = 15,
+ .coladdr = 10,
+ .pagesz = 1,
+ .trcd = 1375,
+ .trcmin = 5062,
+ .trasmin = 3750,
+};
+#elif defined(CONFIG_MT41K128M16JT)
+/* Micron MT41K128M16JT-125 */
+static struct mx6_ddr3_cfg const ddrtype = {
+ .mem_speed = 1600,
+ .density = 2,
+ .width = 16,
+ .banks = 8,
+ .rowaddr = 14,
+ .coladdr = 10,
+ .pagesz = 2,
+ .trcd = 1375,
+ .trcmin = 4875,
+ .trasmin = 3500,
+};
+#elif defined(CONFIG_H5TQ4G63AFR)
+/* Hynix H5TQ4G63AFR */
+static struct mx6_ddr3_cfg const ddrtype = {
+ .mem_speed = 1600,
+ .density = 4,
+ .width = 16,
+ .banks = 8,
+ .rowaddr = 15,
+ .coladdr = 10,
+ .pagesz = 2,
+ .trcd = 1375,
+ .trcmin = 4875,
+ .trasmin = 3500,
+};
+#elif defined CONFIG_H5TQ2G63DFR
+/* Hynix H5TQ2G63DFR */
+static struct mx6_ddr3_cfg const ddrtype = {
+ .mem_speed = 1333,
+ .density = 2,
+ .width = 16,
+ .banks = 8,
+ .rowaddr = 14,
+ .coladdr = 10,
+ .pagesz = 2,
+ .trcd = 1350,
+ .trcmin = 4950,
+ .trasmin = 3600,
+};
+#elif defined(CONFIG_MT42L256M32D2LG)
+/* Micron MT42L256M32D2LG */
+static struct mx6_lpddr2_cfg ddrtype = {
+ .mem_speed = 800,
+ .density = 4,
+ .width = 32,
+ .banks = 8,
+ .rowaddr = 14,
+ .coladdr = 10,
+ .trcd_lp = 2000,
+ .trppb_lp = 2000,
+ .trpab_lp = 2250,
+ .trasmin = 4200,
+};
+#elif defined(CONFIG_MT29PZZZ4D4BKESK)
+/* Micron MT29PZZZ4D4BKESK */
+static struct mx6_lpddr2_cfg ddrtype = {
+ .mem_speed = 800,
+ .density = 4,
+ .width = 32,
+ .banks = 8,
+ .rowaddr = 14,
+ .coladdr = 10,
+ .trcd_lp = 2000,
+ .trppb_lp = 2000,
+ .trpab_lp = 2250,
+ .trasmin = 4200,
+};
+#else
+#error please select DDR type using menuconfig
+#endif
+
+static void ccgr_init(void)
+{
+ struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+ /* FIXME: these should probably be checked, especially
+ * for i.MX6SL, UL, ULL
+ */
+ writel(0x00C03F3F, &ccm->CCGR0);
+ writel(0x0030FC03, &ccm->CCGR1);
+ writel(0x0FFFC000, &ccm->CCGR2);
+ writel(0x3FF00000, &ccm->CCGR3);
+ writel(0x00FFF300, &ccm->CCGR4);
+ writel(0x0F0000C3, &ccm->CCGR5);
+ writel(0x000003FF, &ccm->CCGR6);
+}
+
+static void display_calibration(struct mx6_mmdc_calibration *calib)
+{
+ printf(".p0_mpdgctrl0\t= 0x%08X\n", calib->p0_mpdgctrl0);
+ printf(".p0_mpdgctrl1\t= 0x%08X\n", calib->p0_mpdgctrl1);
+ printf(".p0_mprddlctl\t= 0x%08X\n", calib->p0_mprddlctl);
+ printf(".p0_mpwrdlctl\t= 0x%08X\n", calib->p0_mpwrdlctl);
+ printf(".p0_mpwldectrl0\t= 0x%08X\n", calib->p0_mpwldectrl0);
+ printf(".p0_mpwldectrl1\t= 0x%08X\n", calib->p0_mpwldectrl1);
+ if (sysinfo.dsize == 2) {
+ printf(".p1_mpdgctrl0\t= 0x%08X\n", calib->p1_mpdgctrl0);
+ printf(".p1_mpdgctrl1\t= 0x%08X\n", calib->p1_mpdgctrl1);
+ printf(".p1_mprddlctl\t= 0x%08X\n", calib->p1_mprddlctl);
+ printf(".p1_mpwrdlctl\t= 0x%08X\n", calib->p1_mpwrdlctl);
+ printf(".p1_mpwldectrl0\t= 0x%08X\n", calib->p1_mpwldectrl0);
+ printf(".p1_mpwldectrl1\t= 0x%08X\n", calib->p1_mpwldectrl1);
+ }
+#ifdef CONFIG_IMXIMAGE_OUTPUT
+ printf("DATA 4 MX6_MMDC_P0_MPDGCTRL0\t= 0x%08X\n", calib->p0_mpdgctrl0);
+ printf("DATA 4 MX6_MMDC_P0_MPDGCTRL1\t= 0x%08X\n", calib->p0_mpdgctrl1);
+ printf("DATA 4 MX6_MMDC_P0_MPRDDLCTL\t= 0x%08X\n", calib->p0_mprddlctl);
+ printf("DATA 4 MX6_MMDC_P0_MPWRDLCTL\t= 0x%08X\n", calib->p0_mpwrdlctl);
+ printf("DATA 4 MX6_MMDC_P0_MPWLDECTRL0\t= 0x%08X\n",
+ calib->p0_mpwldectrl0);
+ printf("DATA 4 MX6_MMDC_P0_MPWLDECTRL1\t= 0x%08X\n",
+ calib->p0_mpwldectrl1);
+ if (sysinfo.dsize == 2) {
+ printf("DATA 4 MX6_MMDC_P1_MPDGCTRL0\t= 0x%08X\n",
+ calib->p1_mpdgctrl0);
+ printf("DATA 4 MX6_MMDC_P1_MPDGCTRL1\t= 0x%08X\n",
+ calib->p1_mpdgctrl1);
+ printf("DATA 4 MX6_MMDC_P1_MPRDDLCTL\t= 0x%08X\n",
+ calib->p1_mprddlctl);
+ printf("DATA 4 MX6_MMDC_P1_MPWRDLCTL\t= 0x%08X\n",
+ calib->p1_mpwrdlctl);
+ printf("DATA 4 MX6_MMDC_P1_MPWLDECTRL0\t= 0x%08X\n",
+ calib->p1_mpwldectrl0);
+ printf("DATA 4 MX6_MMDC_P1_MPWLDECTRL1\t= 0x%08X\n",
+ calib->p1_mpwldectrl1);
+ }
+#endif
+}
+
+/*
+ * called from C runtime startup code (arch/arm/lib/crt0.S:_main)
+ * - we have a stack and a place to store GD, both in SRAM
+ * - no variable global data is available
+ */
+void board_init_f(ulong dummy)
+{
+ int errs;
+ struct mx6_mmdc_calibration calibration = {0};
+
+ memset((void *)gd, 0, sizeof(struct global_data));
+
+ /* write leveling calibration defaults */
+ calibration.p0_mpwrdlctl = 0x40404040;
+ calibration.p1_mpwrdlctl = 0x40404040;
+
+ /* setup AIPS and disable watchdog */
+ arch_cpu_init();
+
+ ccgr_init();
+
+ SETUP_IOMUX_PADS(uart_pads);
+
+ /* setup GP timer */
+ timer_init();
+
+ /* UART clocks enabled and gd valid - init serial console */
+ preloader_console_init();
+
+ if (sysinfo.dsize != 1) {
+ if (is_cpu_type(MXC_CPU_MX6SX) ||
+ is_cpu_type(MXC_CPU_MX6UL) ||
+ is_cpu_type(MXC_CPU_MX6SL)) {
+ printf("cpu type 0x%x doesn't support 64-bit bus\n",
+ get_cpu_type());
+ reset_cpu(0);
+ }
+ }
+#ifdef CONFIG_MX6SL
+ mx6sl_dram_iocfg(CONFIG_DDRWIDTH, &mx6sl_ddr_ioregs,
+ &mx6sl_grp_ioregs);
+#else
+ if (is_cpu_type(MXC_CPU_MX6Q)) {
+ mx6dq_dram_iocfg(CONFIG_DDRWIDTH, &mx6dq_ddr_ioregs,
+ &mx6dq_grp_ioregs);
+ } else {
+ mx6sdl_dram_iocfg(CONFIG_DDRWIDTH, &mx6sdl_ddr_ioregs,
+ &mx6sdl_grp_ioregs);
+ }
+#endif
+ mx6_dram_cfg(&sysinfo, &calibration, &ddrtype);
+
+ errs = mmdc_do_write_level_calibration(&sysinfo);
+ if (errs) {
+ printf("error %d from write level calibration\n", errs);
+ } else {
+ errs = mmdc_do_dqs_calibration(&sysinfo);
+ if (errs) {
+ printf("error %d from write level calibration\n", errs);
+ } else {
+ printf("completed successfully\n");
+ mmdc_read_calibration(&sysinfo, &calibration);
+ display_calibration(&calibration);
+ }
+ }
+ reset_cpu(0);
+}
diff --git a/configs/cm_fx6_defconfig b/configs/cm_fx6_defconfig
index bcf2b77190247c15f1b1901b46092d9e4bffff38..33e610ccb42d484383ebacf97a3ce71fe0a2bdfd 100644
--- a/configs/cm_fx6_defconfig
+++ b/configs/cm_fx6_defconfig
@@ -12,9 +12,11 @@ CONFIG_SPL_WATCHDOG_SUPPORT=y
# CONFIG_CMD_BMODE is not set
CONFIG_DEFAULT_DEVICE_TREE="imx6q-cm-fx6"
CONFIG_AHCI=y
+CONFIG_DISTRO_DEFAULTS=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
CONFIG_BOOTDELAY=3
+CONFIG_BOOTCOMMAND="run distro_bootcmd; run legacy_bootcmd"
CONFIG_SPL=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x80
CONFIG_SPL_I2C_SUPPORT=y
diff --git a/configs/mx6memcal_defconfig b/configs/mx6memcal_defconfig
new file mode 100644
index 0000000000000000000000000000000000000000..9a3bb833c161ec988a6890792a0213fdd108eda8
--- /dev/null
+++ b/configs/mx6memcal_defconfig
@@ -0,0 +1,33 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_MX6_DDRCAL=y
+CONFIG_TARGET_MX6MEMCAL=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_WATCHDOG_SUPPORT=y
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,SPL,MX6QDL"
+CONFIG_SPL=y
+CONFIG_HUSH_PARSER=y
+# CONFIG_MMC is not set
+# CONFIG_CMD_BOOTD is not set
+# CONFIG_CMD_BOOTM is not set
+# CONFIG_CMD_ELF is not set
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_IMPORTENV is not set
+# CONFIG_CMD_EDITENV is not set
+# CONFIG_CMD_SAVEENV is not set
+# CONFIG_CMD_ENV_EXISTS is not set
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_MEMINFO=y
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_LOADS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_NET is not set
+# CONFIG_CMD_NFS is not set
+CONFIG_CMD_CACHE=y
+CONFIG_REGEX=y
diff --git a/drivers/gpio/mxc_gpio.c b/drivers/gpio/mxc_gpio.c
index c480eba9407a40c89575b72b94e0b2c4d01140c5..cfa620bceb3fe382d9b7846d033c568d19718c7d 100644
--- a/drivers/gpio/mxc_gpio.c
+++ b/drivers/gpio/mxc_gpio.c
@@ -47,12 +47,12 @@ static unsigned long gpio_ports[] = {
#if defined(CONFIG_MX27) || defined(CONFIG_MX53) || defined(CONFIG_MX6) || \
defined(CONFIG_MX7)
[4] = GPIO5_BASE_ADDR,
-#ifndef CONFIG_MX6UL
+#if !(defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL))
[5] = GPIO6_BASE_ADDR,
#endif
#endif
#if defined(CONFIG_MX53) || defined(CONFIG_MX6) || defined(CONFIG_MX7)
-#ifndef CONFIG_MX6UL
+#if !(defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL))
[6] = GPIO7_BASE_ADDR,
#endif
#endif
diff --git a/drivers/mtd/nand/mxs_nand_spl.c b/drivers/mtd/nand/mxs_nand_spl.c
index b6c9208140fbe9dd62b5a1083d0cc6e0a957248e..910f76dd9d4b7126bf3851e33c75ceff72c35c76 100644
--- a/drivers/mtd/nand/mxs_nand_spl.c
+++ b/drivers/mtd/nand/mxs_nand_spl.c
@@ -153,7 +153,6 @@ static int mxs_nand_init(void)
nand_chip.numchips = 1;
/* identify flash device */
- puts(": ");
if (mxs_flash_ident(mtd)) {
printf("Failed to identify\n");
return -1;
@@ -167,7 +166,6 @@ static int mxs_nand_init(void)
mtd->size = nand_chip.chipsize;
nand_chip.scan_bbt(mtd);
- printf("%llu MiB\n", (mtd->size / (1024 * 1024)));
return 0;
}
diff --git a/include/configs/cm_fx6.h b/include/configs/cm_fx6.h
index 51956102335105e974821906c24b0fed8fe6cf22..ec3e6e6ca52a1d69f75b3a177ae4c5ceeb9c743b 100644
--- a/include/configs/cm_fx6.h
+++ b/include/configs/cm_fx6.h
@@ -13,6 +13,10 @@
#include "mx6_common.h"
+#ifndef CONFIG_SPL_BUILD
+#include <config_distro_defaults.h>
+#endif
+
/* Machine config */
#define CONFIG_SYS_LITTLE_ENDIAN
#define CONFIG_MACH_TYPE 4273
@@ -62,7 +66,15 @@
#define CONFIG_ENV_SIZE (8 * 1024)
#define CONFIG_ENV_OFFSET (768 * 1024)
+#ifndef CONFIG_SPL_BUILD
#define CONFIG_EXTRA_ENV_SETTINGS \
+ "fdt_high=0xffffffff\0" \
+ "initrd_high=0xffffffff\0" \
+ "fdt_addr_r=0x18000000\0" \
+ "ramdisk_addr_r=0x13000000\0" \
+ "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
+ "pxefile_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
+ "scriptaddr=" __stringify(CONFIG_LOADADDR) "\0" \
"stdin=serial,usbkbd\0" \
"stdout=serial,vga\0" \
"stderr=serial,vga\0" \
@@ -71,24 +83,20 @@
"uImage=uImage-cm-fx6\0" \
"zImage=zImage-cm-fx6\0" \
"kernel=uImage-cm-fx6\0" \
- "script=boot.scr\0" \
"dtb=cm-fx6.dtb\0" \
- "bootm_low=18000000\0" \
- "loadaddr=0x10800000\0" \
- "fdtaddr=0x11000000\0" \
"console=ttymxc3,115200\0" \
"ethprime=FEC0\0" \
"video_hdmi=mxcfb0:dev=hdmi,1920x1080M-32@50,if=RGB32\0" \
"video_dvi=mxcfb0:dev=dvi,1280x800M-32@50,if=RGB32\0" \
- "doboot=bootm ${loadaddr}\0" \
+ "doboot=bootm ${kernel_addr_r}\0" \
"doloadfdt=false\0" \
"mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \
"mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
"setboottypez=setenv kernel ${zImage};" \
- "setenv doboot bootz ${loadaddr} - ${fdtaddr};" \
+ "setenv doboot bootz ${kernel_addr_r} - ${fdt_addr_r};" \
"setenv doloadfdt true;\0" \
"setboottypem=setenv kernel ${uImage};" \
- "setenv doboot bootm ${loadaddr};" \
+ "setenv doboot bootm ${kernel_addr_r};" \
"setenv doloadfdt false;\0"\
"mmcroot=/dev/mmcblk0p2 rw rootwait\0" \
"sataroot=/dev/sda2 rw rootwait\0" \
@@ -112,17 +120,13 @@
"run_eboot=echo Starting EBOOT ...; "\
"mmc dev 2 && " \
"mmc rescan && mmc read 10042000 a 400 && go 10042000\0" \
- "loadscript=load ${storagetype} ${storagedev} ${loadaddr} ${script};\0"\
- "loadkernel=load ${storagetype} ${storagedev} ${loadaddr} ${kernel};\0"\
- "loadfdt=load ${storagetype} ${storagedev} ${fdtaddr} ${dtb};\0" \
- "bootscript=echo Running bootscript from ${storagetype} ...;" \
- "source ${loadaddr};\0" \
- "nandloadkernel=nand read ${loadaddr} 0 780000;\0" \
- "nandloadfdt=nand read ${fdtaddr} 780000 80000;\0" \
+ "loadkernel=load ${storagetype} ${storagedev} ${kernel_addr_r} ${kernel};\0"\
+ "loadfdt=load ${storagetype} ${storagedev} ${fdt_addr_r} ${dtb};\0" \
+ "nandloadkernel=nand read ${kernel_addr_r} 0 780000;\0" \
+ "nandloadfdt=nand read ${fdt_addr_r} 780000 80000;\0" \
"setupmmcboot=setenv storagetype mmc; setenv storagedev 2;\0" \
"setupsataboot=setenv storagetype sata; setenv storagedev 0;\0" \
"setupnandboot=setenv storagetype nand;\0" \
- "setupusbboot=setenv storagetype usb; setenv storagedev 0;\0" \
"storagebootcmd=echo Booting from ${storagetype} ...;" \
"run ${storagetype}args; run doboot;\0" \
"trybootk=if run loadkernel; then " \
@@ -131,35 +135,37 @@
"fi;" \
"run storagebootcmd;" \
"fi;\0" \
- "trybootsmz=if run loadscript; then " \
- "run bootscript;" \
- "fi;" \
+ "trybootsmz=" \
"run setboottypem;" \
"run trybootk;" \
"run setboottypez;" \
- "run trybootk;\0"
-
-#define CONFIG_BOOTCOMMAND \
- "run setupmmcboot;" \
- "mmc dev ${storagedev};" \
- "if mmc rescan; then " \
- "run trybootsmz;" \
- "fi;" \
- "run setupusbboot;" \
- "if usb start; then "\
- "if run loadscript; then " \
- "run bootscript;" \
+ "run trybootk;\0" \
+ "legacy_bootcmd=" \
+ "run setupmmcboot;" \
+ "mmc dev ${storagedev};" \
+ "if mmc rescan; then " \
+ "run trybootsmz;" \
"fi;" \
- "fi;" \
- "run setupsataboot;" \
- "if sata init; then " \
- "run trybootsmz;" \
- "fi;" \
- "run setupnandboot;" \
- "run nandboot;"
+ "run setupsataboot;" \
+ "if sata init; then " \
+ "run trybootsmz;" \
+ "fi;" \
+ "run setupnandboot;" \
+ "run nandboot;\0" \
+ BOOTENV
#define CONFIG_PREBOOT "usb start;sf probe"
+#define BOOT_TARGET_DEVICES(func) \
+ func(USB, usb, 0) \
+ func(MMC, mmc, 2) \
+ func(SATA, sata, 0)
+
+#include <config_distro_bootcmd.h>
+#else
+#define CONFIG_EXTRA_ENV_SETTINGS
+#endif
+
/* SPI */
#define CONFIG_SPI
#define CONFIG_MXC_SPI
diff --git a/include/configs/imx6_spl.h b/include/configs/imx6_spl.h
index cdb3a374bc049b197804194df58396c1ad0c1176..dd481205f36097ed6aa7bec2508ee2c1fb1b3599 100644
--- a/include/configs/imx6_spl.h
+++ b/include/configs/imx6_spl.h
@@ -55,7 +55,8 @@
# endif
#endif
-#if defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL) || defined(CONFIG_MX6SL)
+#if defined(CONFIG_MX6SX) || defined(CONFIG_MX6SL) || \
+ defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL)
#define CONFIG_SPL_BSS_START_ADDR 0x88200000
#define CONFIG_SPL_BSS_MAX_SIZE 0x100000 /* 1 MB */
#define CONFIG_SYS_SPL_MALLOC_START 0x88300000
diff --git a/include/configs/mx6_common.h b/include/configs/mx6_common.h
index 5fb85a1127788cbb50958c8e1d0a6b4485be1d81..ddc645c136500650abab7b7695f0928a60e0d282 100644
--- a/include/configs/mx6_common.h
+++ b/include/configs/mx6_common.h
@@ -7,7 +7,10 @@
#ifndef __MX6_COMMON_H
#define __MX6_COMMON_H
-#ifndef CONFIG_MX6UL
+#if (defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL))
+#define CONFIG_SC_TIMER_CLK 8000000 /* 8Mhz */
+#define COUNTER_FREQUENCY CONFIG_SC_TIMER_CLK
+#else
#ifndef CONFIG_SYS_L2CACHE_OFF
#define CONFIG_SYS_L2_PL310
#define CONFIG_SYS_PL310_BASE L2_PL310_BASE
@@ -37,8 +40,9 @@
#define CONFIG_REVISION_TAG
/* Boot options */
-#if (defined(CONFIG_MX6SX) || defined(CONFIG_MX6SL) || \
- defined(CONFIG_MX6UL) || defined(CONFIG_MX6SLL))
+#if defined(CONFIG_MX6SL) || defined(CONFIG_MX6SLL) || \
+ defined(CONFIG_MX6SX) || \
+ defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL)
#define CONFIG_LOADADDR 0x82000000
#ifndef CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_TEXT_BASE 0x87800000
diff --git a/include/configs/mx6memcal.h b/include/configs/mx6memcal.h
new file mode 100644
index 0000000000000000000000000000000000000000..f5238a52f50fb9fe42a63d0b0fbf9cfe5e14a28f
--- /dev/null
+++ b/include/configs/mx6memcal.h
@@ -0,0 +1,59 @@
+/*
+ * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
+ *
+ * Configuration settings for the Boundary Devices Nitrogen6X
+ * and Freescale i.MX6Q Sabre Lite boards.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* SPL */
+
+#include "mx6_common.h"
+#include "imx6_spl.h"
+
+#undef CONFIG_FSL_ESDHC
+#undef CONFIG_MMC
+#undef CONFIG_SPL_MMC_SUPPORT
+#undef CONFIG_GENERIC_MMC
+#undef CONFIG_CMD_FUSE
+
+#define CONFIG_SYS_MEMTEST_START 0x10000000
+#define CONFIG_SYS_MEMTEST_END 0x20000000
+#define CONFIG_SYS_MALLOC_LEN (64 * 1024 * 1024)
+
+#define CONFIG_MXC_UART
+#ifdef CONFIG_SERIAL_CONSOLE_UART1
+#if defined(CONFIG_MX6SL)
+#define CONFIG_MXC_UART_BASE UART1_IPS_BASE_ADDR
+#else
+#define CONFIG_MXC_UART_BASE UART1_BASE
+#endif
+#elif defined(CONFIG_SERIAL_CONSOLE_UART2)
+#define CONFIG_MXC_UART_BASE UART2_BASE
+#else
+#error please define serial console (CONFIG_SERIAL_CONSOLE_UARTx)
+#endif
+#define CONFIG_BAUDRATE 115200
+
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + 16)
+
+/* Physical Memory Map */
+#define CONFIG_NR_DRAM_BANKS 1
+#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
+
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
+#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+ (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+#define CONFIG_ENV_SIZE (8 * 1024)
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/mx7_common.h b/include/configs/mx7_common.h
index 16e4d95ff47de948e41cebb582df88b4c22cc352..17850400c1fd6384eaf2f4ec8d9db55bab1a814d 100644
--- a/include/configs/mx7_common.h
+++ b/include/configs/mx7_common.h
@@ -19,7 +19,6 @@
/* Timer settings */
#define CONFIG_MXC_GPT_HCLK
-#define CONFIG_SYSCOUNTER_TIMER
#define CONFIG_SC_TIMER_CLK 8000000 /* 8Mhz */
#define COUNTER_FREQUENCY CONFIG_SC_TIMER_CLK
#define CONFIG_SYS_FSL_CLK
diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt
index 43a4ff08928db2dafc12d391718ab1a337685a76..a27dc4fc3822f1d8f406b8229bab39832a76cdca 100644
--- a/scripts/config_whitelist.txt
+++ b/scripts/config_whitelist.txt
@@ -362,6 +362,7 @@ CONFIG_DB_784MP_GP
CONFIG_DCACHE
CONFIG_DCACHE_OFF
CONFIG_DCFG_ADDR
+CONFIG_DDR3
CONFIG_DDR_
CONFIG_DDR_2HCLK
CONFIG_DDR_2T_TIMING
@@ -2219,7 +2220,6 @@ CONFIG_SUPPORT_RAW_INITRD
CONFIG_SUPPORT_VFAT
CONFIG_SUVD3
CONFIG_SXNI855T
-CONFIG_SYSCOUNTER_TIMER
CONFIG_SYSFLAGS_ADDR
CONFIG_SYSFS
CONFIG_SYSMGR_ISWGRP_HANDOFF