From 2ad77bc207766568526d8a766dabd523090129c6 Mon Sep 17 00:00:00 2001
From: Troy Kisky <troy.kisky@boundarydevices.com>
Date: Fri, 16 May 2014 12:20:09 -0700
Subject: [PATCH] bt: initial addition, Boundary Devices board
Two configurations bt2g and bt4g for two different memory layouts
bt.h: CONFIG_IPUV3_CLK 264000000
bt: rename J6/J7 to J12V/J5V
bt: use nitrogen6x clock.cfg/ddr-setup.cfg
bt: add CONFIG_CMD_GPIO
bt: explicit fbp_detect_i2c
bt: use boundary.h
bt: add CONFIG_SPI_FLASH_SPANSION
bt.h: use BD_CMA to specify cma= on cmd_line
bt: bt2g_defconfig add CONFIG_BLOCK_CACHE
bt4g: bt4g_defconfig add CONFIG_BLOCK_CACHE
bt: use common code for eth init
bt: eth.c now in common directory
bt: move misc_init_r/do_kbd to common
bt: move mmc_init/ dram_init/ overwrite_console/ common_board_init/ splash_screen_prepare/ board_cfb_skip to common
bt: use common 1066mhz_4x256mx16.cfg
bt: add CONFIG_SPI_FLASH_GIGADEVICE: to defconfigs
bt: use common ddr scripts
bt: port to v2018.07
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
bt: update to v2017.01
bt: update to v2017.03
Signed-off-by: Gary Bisson <gary.bisson@boundarydevices.com>
---
arch/arm/mach-imx/mx6/Kconfig | 4 +
board/boundary/bt/6x_bootscript.txt | 9 +
board/boundary/bt/Kconfig | 20 +
board/boundary/bt/MAINTAINERS | 8 +
board/boundary/bt/Makefile | 10 +
board/boundary/bt/bt.c | 573 ++++++++++++++++++++++++++++
board/boundary/bt/bt2g.cfg | 47 +++
board/boundary/bt/bt4g.cfg | 47 +++
board/boundary/bt/spl.c | 112 ++++++
configs/bt2g_defconfig | 72 ++++
configs/bt4g_defconfig | 72 ++++
include/configs/bt.h | 27 ++
12 files changed, 1001 insertions(+)
create mode 100644 board/boundary/bt/6x_bootscript.txt
create mode 100644 board/boundary/bt/Kconfig
create mode 100644 board/boundary/bt/MAINTAINERS
create mode 100644 board/boundary/bt/Makefile
create mode 100644 board/boundary/bt/bt.c
create mode 100644 board/boundary/bt/bt2g.cfg
create mode 100644 board/boundary/bt/bt4g.cfg
create mode 100644 board/boundary/bt/spl.c
create mode 100644 configs/bt2g_defconfig
create mode 100644 configs/bt4g_defconfig
create mode 100644 include/configs/bt.h
diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig
index 0e235435e81..5ea9a56e652 100644
--- a/arch/arm/mach-imx/mx6/Kconfig
+++ b/arch/arm/mach-imx/mx6/Kconfig
@@ -371,6 +371,9 @@ config TARGET_ASH
config TARGET_ASH2
bool "ash2"
+config TARGET_BT
+ bool "bt"
+
config TARGET_NITROGEN6X
bool "nitrogen6x"
imply USB_HOST_ETHER
@@ -517,6 +520,7 @@ source "board/boundary/acl/Kconfig"
source "board/boundary/ap/Kconfig"
source "board/boundary/ash/Kconfig"
source "board/boundary/ash2/Kconfig"
+source "board/boundary/bt/Kconfig"
source "board/boundary/nitrogen6x/Kconfig"
source "board/boundary/ys/Kconfig"
source "board/bticino/mamoj/Kconfig"
diff --git a/board/boundary/bt/6x_bootscript.txt b/board/boundary/bt/6x_bootscript.txt
new file mode 100644
index 00000000000..de208d56e02
--- /dev/null
+++ b/board/boundary/bt/6x_bootscript.txt
@@ -0,0 +1,9 @@
+setenv bootargs enable_wait_mode=off video=mxcfb0:dev=hdmi,1280x720M@60,if=RGB24
+setenv bootargs $bootargs video=mxcfb1:off video=mxcfb2:off video=mxcfb3:off
+setenv bootargs $bootargs fbmem=28M console=ttymxc1,115200 vmalloc=400M
+setenv bootargs $bootargs consoleblank=0 mxc_hdmi.only_cea=1
+setenv bootargs $bootargs rootwait root=/dev/mmcblk${disk}p1
+ext2load mmc ${disk}:1 0x10800000 /boot/uImage &&
+ ext2load mmc ${disk}:1 0x12800000 /boot/uramdisk.img &&
+ bootm 10800000 12800000
+echo "Error launching kernel /boot/uImage"
diff --git a/board/boundary/bt/Kconfig b/board/boundary/bt/Kconfig
new file mode 100644
index 00000000000..e89c50d0545
--- /dev/null
+++ b/board/boundary/bt/Kconfig
@@ -0,0 +1,20 @@
+if TARGET_BT
+
+config SYS_CPU
+ default "armv7"
+
+config SYS_BOARD
+ default "bt"
+
+config SYS_VENDOR
+ default "boundary"
+
+config SYS_SOC
+ default "mx6"
+
+config SYS_CONFIG_NAME
+ default "bt"
+
+source "board/boundary/common/Kconfig"
+
+endif
diff --git a/board/boundary/bt/MAINTAINERS b/board/boundary/bt/MAINTAINERS
new file mode 100644
index 00000000000..22825d2258c
--- /dev/null
+++ b/board/boundary/bt/MAINTAINERS
@@ -0,0 +1,8 @@
+BT BOARD
+M: Troy Kisky <troy.kisky@boundarydevices.com>
+S: Maintained
+F: board/boundary/bt/
+F: include/configs/bt.h
+F: configs/bt2g_defconfig
+F: configs/bt4g_defconfig
+
diff --git a/board/boundary/bt/Makefile b/board/boundary/bt/Makefile
new file mode 100644
index 00000000000..9ae9738a264
--- /dev/null
+++ b/board/boundary/bt/Makefile
@@ -0,0 +1,10 @@
+#
+# Copyright (C) 2012-2013, Guennadi Liakhovetski <lg@denx.de>
+# (C) Copyright 2012-2013 Freescale Semiconductor, Inc.
+# Copyright (C) 2013, Boundary Devices <info@boundarydevices.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := bt.o
+obj-$(CONFIG_SPL_BUILD) += spl.o
diff --git a/board/boundary/bt/bt.c b/board/boundary/bt/bt.c
new file mode 100644
index 00000000000..95606563919
--- /dev/null
+++ b/board/boundary/bt/bt.c
@@ -0,0 +1,573 @@
+/*
+ * Copyright (C) 2010-2013 Freescale Semiconductor, Inc.
+ * Copyright (C) 2013, Boundary Devices <info@boundarydevices.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/sys_proto.h>
+#include <malloc.h>
+#include <asm/arch/mx6-pins.h>
+#include <linux/errno.h>
+#include <asm/gpio.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/mach-imx/fbpanel.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#include <asm/mach-imx/sata.h>
+#include <asm/mach-imx/spi.h>
+#include <mmc.h>
+#include <fsl_esdhc.h>
+#include <linux/fb.h>
+#include <ipu_pixfmt.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/mxc_hdmi.h>
+#include <i2c.h>
+#include <input.h>
+#include <splash.h>
+#include <usb/ehci-ci.h>
+#include "../common/bd_common.h"
+#include "../common/padctrl.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define AUD_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
+ PAD_CTL_SPEED_LOW | PAD_CTL_DSE_40ohm | \
+ PAD_CTL_HYS | PAD_CTL_SRE_FAST)
+
+#define BUTTON_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
+ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
+
+#define CSI_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
+ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
+ PAD_CTL_HYS | PAD_CTL_SRE_FAST)
+
+#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
+ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
+ PAD_CTL_ODE | PAD_CTL_SRE_FAST)
+
+#define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
+ PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
+
+#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
+ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
+ PAD_CTL_HYS | PAD_CTL_SRE_FAST)
+
+#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
+ PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
+ PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+
+/*
+ *
+ */
+static const iomux_v3_cfg_t init_pads[] = {
+ /* ECSPI1 */
+ IOMUX_PAD_CTRL(EIM_D17__ECSPI1_MISO, SPI_PAD_CTRL),
+ IOMUX_PAD_CTRL(EIM_D18__ECSPI1_MOSI, SPI_PAD_CTRL),
+ IOMUX_PAD_CTRL(EIM_D16__ECSPI1_SCLK, SPI_PAD_CTRL),
+#define GP_ECSPI1_NOR_CS IMX_GPIO_NR(3, 19)
+ IOMUX_PAD_CTRL(EIM_D19__GPIO3_IO19, WEAK_PULLUP), /* SS1 */
+
+ /* ECSPI3 - GS2971 */
+ IOMUX_PAD_CTRL(DISP0_DAT2__ECSPI3_MISO, SPI_PAD_CTRL), /* pin E7 - SDOUT */
+ IOMUX_PAD_CTRL(DISP0_DAT1__ECSPI3_MOSI, SPI_PAD_CTRL), /* pin E8 - SDIN */
+ IOMUX_PAD_CTRL(DISP0_DAT0__ECSPI3_SCLK, SPI_PAD_CTRL), /* pin F8 - SCLK */
+#define GP_ECSPI3_GS2971_CS IMX_GPIO_NR(4, 24)
+ IOMUX_PAD_CTRL(DISP0_DAT3__GPIO4_IO24, WEAK_PULLUP), /* 0 - pin F7 - CS0 */
+
+ /* ENET pads that don't change for PHY reset */
+ IOMUX_PAD_CTRL(ENET_MDIO__ENET_MDIO, PAD_CTRL_ENET_MDIO),
+ IOMUX_PAD_CTRL(ENET_MDC__ENET_MDC, PAD_CTRL_ENET_MDC),
+ IOMUX_PAD_CTRL(RGMII_TXC__RGMII_TXC, PAD_CTRL_ENET_TX),
+ IOMUX_PAD_CTRL(RGMII_TD0__RGMII_TD0, PAD_CTRL_ENET_TX),
+ IOMUX_PAD_CTRL(RGMII_TD1__RGMII_TD1, PAD_CTRL_ENET_TX),
+ IOMUX_PAD_CTRL(RGMII_TD2__RGMII_TD2, PAD_CTRL_ENET_TX),
+ IOMUX_PAD_CTRL(RGMII_TD3__RGMII_TD3, PAD_CTRL_ENET_TX),
+ IOMUX_PAD_CTRL(RGMII_TX_CTL__RGMII_TX_CTL, PAD_CTRL_ENET_TX),
+ IOMUX_PAD_CTRL(ENET_REF_CLK__ENET_TX_CLK, PAD_CTRL_ENET_TX),
+ /* pin 42 PHY nRST */
+#define GP_RGMII_PHY_RESET IMX_GPIO_NR(1, 27)
+ IOMUX_PAD_CTRL(ENET_RXD0__GPIO1_IO27, OUTPUT_40OHM),
+#define GPIRQ_ENET_PHY IMX_GPIO_NR(1, 28)
+ IOMUX_PAD_CTRL(ENET_TX_EN__GPIO1_IO28, WEAK_PULLUP), /* Micrel RGMII Phy Interrupt */
+
+ /* gpios J91 */
+ /* grounds, 1,2,11,12,29,46,47,48,49,50 */
+#define GP_BT_GPIO1 IMX_GPIO_NR(2, 15)
+ IOMUX_PAD_CTRL(SD4_DAT7__GPIO2_IO15, WEAK_PULLUP), /* bt_gpio1, pin 3 */
+#define GP_BT_GPIO2 IMX_GPIO_NR(2, 14)
+ IOMUX_PAD_CTRL(SD4_DAT6__GPIO2_IO14, WEAK_PULLUP), /* bt_gpio2, pin 4 */
+#define GP_BT_GPIO3 IMX_GPIO_NR(2, 13)
+ IOMUX_PAD_CTRL(SD4_DAT5__GPIO2_IO13, WEAK_PULLUP), /* bt_gpio3, pin 5 */
+#define GP_BT_GPIO4 IMX_GPIO_NR(2, 12)
+ IOMUX_PAD_CTRL(SD4_DAT4__GPIO2_IO12, WEAK_PULLUP), /* bt_gpio4, pin 6 */
+#define GP_BT_GPIO5 IMX_GPIO_NR(2, 11)
+ IOMUX_PAD_CTRL(SD4_DAT3__GPIO2_IO11, WEAK_PULLUP), /* bt_gpio5, pin 7 */
+#define GP_BT_GPIO6 IMX_GPIO_NR(2, 10)
+ IOMUX_PAD_CTRL(SD4_DAT2__GPIO2_IO10, WEAK_PULLUP), /* bt_gpio6, pin 8 */
+#define GP_BT_GPIO7 IMX_GPIO_NR(2, 9)
+ IOMUX_PAD_CTRL(SD4_DAT1__GPIO2_IO09, WEAK_PULLUP), /* bt_gpio7, pin 9 */
+#define GP_BT_GPIO8 IMX_GPIO_NR(2, 8)
+ IOMUX_PAD_CTRL(SD4_DAT0__GPIO2_IO08, WEAK_PULLUP), /* bt_gpio8, pin 10 */
+#define GP_BT_GPIO9 IMX_GPIO_NR(7, 9)
+ IOMUX_PAD_CTRL(SD4_CMD__GPIO7_IO09, WEAK_PULLUP), /* bt_gpio9, pin 13 */
+#define GP_BT_GPIO10 IMX_GPIO_NR(7, 10)
+ IOMUX_PAD_CTRL(SD4_CLK__GPIO7_IO10, WEAK_PULLUP), /* bt_gpio10, pin 14 */
+#define GP_BT_GPIO11 IMX_GPIO_NR(2, 7)
+ IOMUX_PAD_CTRL(NANDF_D7__GPIO2_IO07, WEAK_PULLUP), /* bt_gpio11, pin 15 */
+#define GP_BT_GPIO12 IMX_GPIO_NR(2, 6)
+ IOMUX_PAD_CTRL(NANDF_D6__GPIO2_IO06, WEAK_PULLUP), /* bt_gpio12, pin 16 */
+#define GP_BT_GPIO13 IMX_GPIO_NR(2, 5)
+ IOMUX_PAD_CTRL(NANDF_D5__GPIO2_IO05, WEAK_PULLUP), /* bt_gpio13, pin 17 */
+#define GP_BT_GPIO14 IMX_GPIO_NR(2, 4)
+ IOMUX_PAD_CTRL(NANDF_D4__GPIO2_IO04, WEAK_PULLUP), /* bt_gpio14, pin 18 */
+#define GP_BT_GPIO15 IMX_GPIO_NR(2, 3)
+ IOMUX_PAD_CTRL(NANDF_D3__GPIO2_IO03, WEAK_PULLUP), /* bt_gpio15, pin 19 */
+#define GP_BT_GPIO16 IMX_GPIO_NR(2, 2)
+ IOMUX_PAD_CTRL(NANDF_D2__GPIO2_IO02, WEAK_PULLUP), /* bt_gpio16, pin 20 */
+#define GP_BT_GPIO17 IMX_GPIO_NR(2, 1)
+ IOMUX_PAD_CTRL(NANDF_D1__GPIO2_IO01, WEAK_PULLUP), /* bt_gpio17, pin 21 */
+#define GP_BT_GPIO18 IMX_GPIO_NR(2, 0)
+ IOMUX_PAD_CTRL(NANDF_D0__GPIO2_IO00, WEAK_PULLUP), /* bt_gpio18, pin 22 */
+#define GP_BT_GPIO19 IMX_GPIO_NR(6, 10)
+ IOMUX_PAD_CTRL(NANDF_RB0__GPIO6_IO10, WEAK_PULLUP), /* bt_gpio19, pin 23 */
+#define GP_BT_GPIO20 IMX_GPIO_NR(6, 9)
+ IOMUX_PAD_CTRL(NANDF_WP_B__GPIO6_IO09, WEAK_PULLUP), /* bt_gpio20, pin 24 */
+#define GP_BT_GPIO21 IMX_GPIO_NR(6, 7)
+ IOMUX_PAD_CTRL(NANDF_CLE__GPIO6_IO07, WEAK_PULLUP), /* bt_gpio21, pin 25 */
+#define GP_BT_GPIO22 IMX_GPIO_NR(6, 8)
+ IOMUX_PAD_CTRL(NANDF_ALE__GPIO6_IO08, WEAK_PULLUP), /* bt_gpio22, pin 26 */
+#define GP_BT_GPIO23 IMX_GPIO_NR(6, 16)
+ IOMUX_PAD_CTRL(NANDF_CS3__GPIO6_IO16, WEAK_PULLUP), /* bt_gpio23, pin 27 */
+#define GP_BT_GPIO24 IMX_GPIO_NR(6, 15)
+ IOMUX_PAD_CTRL(NANDF_CS2__GPIO6_IO15, WEAK_PULLUP), /* bt_gpio24, pin 28 */
+#define GP_BT_GPIO25 IMX_GPIO_NR(6, 14)
+ IOMUX_PAD_CTRL(NANDF_CS1__GPIO6_IO14, WEAK_PULLUP), /* bt_gpio25, pin 30 */
+#define GP_BT_GPIO26 IMX_GPIO_NR(6, 11)
+ IOMUX_PAD_CTRL(NANDF_CS0__GPIO6_IO11, WEAK_PULLUP), /* bt_gpio26, pin 31 */
+#define GP_BT_GPIO27 IMX_GPIO_NR(5, 30)
+ IOMUX_PAD_CTRL(CSI0_DAT12__GPIO5_IO30, WEAK_PULLUP), /* bt_gpio27, pin 32 */
+#define GP_BT_GPIO28 IMX_GPIO_NR(5, 31)
+ IOMUX_PAD_CTRL(CSI0_DAT13__GPIO5_IO31, WEAK_PULLUP), /* bt_gpio28, pin 33 */
+#define GP_BT_GPIO29 IMX_GPIO_NR(5, 24)
+ IOMUX_PAD_CTRL(CSI0_DAT6__GPIO5_IO24, WEAK_PULLUP), /* bt_gpio29, pin 34 */
+#define GP_BT_GPIO30 IMX_GPIO_NR(5, 25)
+ IOMUX_PAD_CTRL(CSI0_DAT7__GPIO5_IO25, WEAK_PULLUP), /* bt_gpio30, pin 35 */
+#define GP_BT_GPIO31 IMX_GPIO_NR(6, 2)
+ IOMUX_PAD_CTRL(CSI0_DAT16__GPIO6_IO02, WEAK_PULLUP), /* bt_gpio31, pin 36 */
+#define GP_BT_GPIO32 IMX_GPIO_NR(6, 3)
+ IOMUX_PAD_CTRL(CSI0_DAT17__GPIO6_IO03, WEAK_PULLUP), /* bt_gpio32, pin 37 */
+#define GP_BT_GPIO33 IMX_GPIO_NR(6, 4)
+ IOMUX_PAD_CTRL(CSI0_DAT18__GPIO6_IO04, WEAK_PULLUP), /* bt_gpio33, pin 38 */
+#define GP_BT_GPIO34 IMX_GPIO_NR(6, 5)
+ IOMUX_PAD_CTRL(CSI0_DAT19__GPIO6_IO05, WEAK_PULLUP), /* bt_gpio34, pin 39 */
+#define GP_BT_GPIO35 IMX_GPIO_NR(5, 2)
+ IOMUX_PAD_CTRL(EIM_A25__GPIO5_IO02, WEAK_PULLUP), /* bt_gpio35, pin 40 */
+#define GP_BT_GPIO36 IMX_GPIO_NR(3, 29)
+ IOMUX_PAD_CTRL(EIM_D29__GPIO3_IO29, WEAK_PULLUP), /* bt_gpio36, pin 41 */
+#define GP_BT_GPIO37 IMX_GPIO_NR(2, 30)
+ IOMUX_PAD_CTRL(EIM_EB2__GPIO2_IO30, WEAK_PULLUP), /* bt_gpio37, pin 42 */
+#define GP_BT_GPIO38 IMX_GPIO_NR(2, 31)
+ IOMUX_PAD_CTRL(EIM_EB3__GPIO2_IO31, WEAK_PULLUP), /* bt_gpio38, pin 43 */
+#define GP_BT_GPIO39 IMX_GPIO_NR(5, 26)
+ IOMUX_PAD_CTRL(CSI0_DAT8__GPIO5_IO26, WEAK_PULLUP), /* bt_gpio39, pin 44 */
+#define GP_BT_GPIO40 IMX_GPIO_NR(5, 27)
+ IOMUX_PAD_CTRL(CSI0_DAT9__GPIO5_IO27, WEAK_PULLUP), /* bt_gpio40, pin 45 */
+
+ /* Power control, high is off */
+ /* Pull-up so that reset will leave high */
+#define GP_PWR_J1 IMX_GPIO_NR(5, 9)
+ IOMUX_PAD_CTRL(DISP0_DAT15__GPIO5_IO09, WEAK_PULLUP), /* J1 Power enable */
+#define GP_PWR_J2 IMX_GPIO_NR(4, 25)
+ IOMUX_PAD_CTRL(DISP0_DAT4__GPIO4_IO25, WEAK_PULLUP), /* J2 */
+#define GP_PWR_J3 IMX_GPIO_NR(2, 23)
+ IOMUX_PAD_CTRL(EIM_CS0__GPIO2_IO23, WEAK_PULLUP), /* J3 */
+#define GP_PWR_J4 IMX_GPIO_NR(2, 25)
+ IOMUX_PAD_CTRL(EIM_OE__GPIO2_IO25, WEAK_PULLUP), /* J4 */
+#define GP_PWR_J5V IMX_GPIO_NR(2, 27)
+ IOMUX_PAD_CTRL(EIM_LBA__GPIO2_IO27, WEAK_PULLUP), /* J7 */
+#define GP_PWR_J12V IMX_GPIO_NR(2, 26)
+ IOMUX_PAD_CTRL(EIM_RW__GPIO2_IO26, WEAK_PULLUP), /* J6 */
+
+ /* Dry Contact */
+ /* J92 pins */
+#define GP_J92_PIN7 IMX_GPIO_NR(3, 31)
+ IOMUX_PAD_CTRL(EIM_D31__GPIO3_IO31, WEAK_PULLUP), /* OUT_1 - Dry contact to J92 pin 7 */
+#define GP_J92_PIN9 IMX_GPIO_NR(1, 8)
+ IOMUX_PAD_CTRL(GPIO_8__GPIO1_IO08, WEAK_PULLDN), /* OUT_2 - Dry contact to J92 pin 9 */
+#define GP_J92_PIN10 IMX_GPIO_NR(5, 22)
+ IOMUX_PAD_CTRL(CSI0_DAT4__GPIO5_IO22, WEAK_PULLUP), /* GPI_1 - J92 - pin 10 */
+#define GP_J92_PIN12 IMX_GPIO_NR(5, 23)
+ IOMUX_PAD_CTRL(CSI0_DAT5__GPIO5_IO23, WEAK_PULLUP), /* GPI_2 - J92 - pin 12 */
+
+ /* Test points */
+#define GP_TP81 IMX_GPIO_NR(1, 3)
+ IOMUX_PAD_CTRL(GPIO_3__GPIO1_IO03, WEAK_PULLUP),
+
+ /*
+ * PCIe - tw6869 dedicated,
+ * VIN1-4 used,
+ * AIN1-2 amplified, AIN3-4 not amplified
+ */
+#define GP_PCIE_RESET IMX_GPIO_NR(4, 8)
+ IOMUX_PAD_CTRL(KEY_COL1__GPIO4_IO08, OUTPUT_40OHM),
+
+ /* i2c1 rtc rv4162 */
+#define GPIRQ_RTC_RV4162 IMX_GPIO_NR(4, 11)
+ IOMUX_PAD_CTRL(KEY_ROW2__GPIO4_IO11, WEAK_PULLUP),
+
+ /* I2C3_Adv7391 */
+#define GP_ADV7391_RESET IMX_GPIO_NR(4, 20)
+ IOMUX_PAD_CTRL(DI0_PIN4__GPIO4_IO20, WEAK_PULLUP), /* Adv7391 reset */
+
+ /* SDI - gs2971 on CSI1 */
+#if defined(CONFIG_MX6S) || defined(CONFIG_MX6DL)
+ /* Dualite/Solo doesn't have IPU2 */
+ IOMUX_PAD_CTRL(EIM_A24__IPU1_CSI1_DATA19, CSI_PAD_CTRL), /* GPIO2[30] */
+ IOMUX_PAD_CTRL(EIM_A23__IPU1_CSI1_DATA18, CSI_PAD_CTRL), /* GPIO6[6] */
+ IOMUX_PAD_CTRL(EIM_A22__IPU1_CSI1_DATA17, CSI_PAD_CTRL), /* GPIO2[16] */
+ IOMUX_PAD_CTRL(EIM_A21__IPU1_CSI1_DATA16, CSI_PAD_CTRL), /* GPIO2[17] */
+ IOMUX_PAD_CTRL(EIM_A20__IPU1_CSI1_DATA15, CSI_PAD_CTRL), /* GPIO2[18] */
+ IOMUX_PAD_CTRL(EIM_A19__IPU1_CSI1_DATA14, CSI_PAD_CTRL), /* GPIO2[19] */
+ IOMUX_PAD_CTRL(EIM_A18__IPU1_CSI1_DATA13, CSI_PAD_CTRL), /* GPIO2[20] */
+ IOMUX_PAD_CTRL(EIM_A17__IPU1_CSI1_DATA12, CSI_PAD_CTRL), /* GPIO2[21] */
+ IOMUX_PAD_CTRL(EIM_EB0__IPU1_CSI1_DATA11, CSI_PAD_CTRL), /* GPIO2[28] */
+ IOMUX_PAD_CTRL(EIM_EB1__IPU1_CSI1_DATA10, CSI_PAD_CTRL), /* GPIO2[29] */
+ IOMUX_PAD_CTRL(EIM_DA0__IPU1_CSI1_DATA09, CSI_PAD_CTRL), /* GPIO3[0] */
+ IOMUX_PAD_CTRL(EIM_DA1__IPU1_CSI1_DATA08, CSI_PAD_CTRL), /* GPIO3[1] */
+ IOMUX_PAD_CTRL(EIM_DA2__IPU1_CSI1_DATA07, CSI_PAD_CTRL), /* GPIO3[2] */
+ IOMUX_PAD_CTRL(EIM_DA3__IPU1_CSI1_DATA06, CSI_PAD_CTRL), /* GPIO3[3] */
+ IOMUX_PAD_CTRL(EIM_DA4__IPU1_CSI1_DATA05, CSI_PAD_CTRL), /* GPIO3[4] */
+ IOMUX_PAD_CTRL(EIM_DA5__IPU1_CSI1_DATA04, CSI_PAD_CTRL), /* GPIO3[5] */
+ IOMUX_PAD_CTRL(EIM_DA6__IPU1_CSI1_DATA03, CSI_PAD_CTRL), /* GPIO3[6] */
+ IOMUX_PAD_CTRL(EIM_DA7__IPU1_CSI1_DATA02, CSI_PAD_CTRL), /* GPIO3[7] */
+ IOMUX_PAD_CTRL(EIM_DA8__IPU1_CSI1_DATA01, CSI_PAD_CTRL), /* GPIO3[8] */
+ IOMUX_PAD_CTRL(EIM_DA9__IPU1_CSI1_DATA00, CSI_PAD_CTRL), /* GPIO3[9] */
+ IOMUX_PAD_CTRL(EIM_A16__IPU1_CSI1_PIXCLK, CSI_PAD_CTRL), /* GPIO2[22] */
+#else
+ IOMUX_PAD_CTRL(EIM_A24__IPU2_CSI1_DATA19, CSI_PAD_CTRL), /* GPIO2[30] */
+ IOMUX_PAD_CTRL(EIM_A23__IPU2_CSI1_DATA18, CSI_PAD_CTRL), /* GPIO6[6] */
+ IOMUX_PAD_CTRL(EIM_A22__IPU2_CSI1_DATA17, CSI_PAD_CTRL), /* GPIO2[16] */
+ IOMUX_PAD_CTRL(EIM_A21__IPU2_CSI1_DATA16, CSI_PAD_CTRL), /* GPIO2[17] */
+ IOMUX_PAD_CTRL(EIM_A20__IPU2_CSI1_DATA15, CSI_PAD_CTRL), /* GPIO2[18] */
+ IOMUX_PAD_CTRL(EIM_A19__IPU2_CSI1_DATA14, CSI_PAD_CTRL), /* GPIO2[19] */
+ IOMUX_PAD_CTRL(EIM_A18__IPU2_CSI1_DATA13, CSI_PAD_CTRL), /* GPIO2[20] */
+ IOMUX_PAD_CTRL(EIM_A17__IPU2_CSI1_DATA12, CSI_PAD_CTRL), /* GPIO2[21] */
+ IOMUX_PAD_CTRL(EIM_EB0__IPU2_CSI1_DATA11, CSI_PAD_CTRL), /* GPIO2[28] */
+ IOMUX_PAD_CTRL(EIM_EB1__IPU2_CSI1_DATA10, CSI_PAD_CTRL), /* GPIO2[29] */
+ IOMUX_PAD_CTRL(EIM_DA0__IPU2_CSI1_DATA09, CSI_PAD_CTRL), /* GPIO3[0] */
+ IOMUX_PAD_CTRL(EIM_DA1__IPU2_CSI1_DATA08, CSI_PAD_CTRL), /* GPIO3[1] */
+ IOMUX_PAD_CTRL(EIM_DA2__IPU2_CSI1_DATA07, CSI_PAD_CTRL), /* GPIO3[2] */
+ IOMUX_PAD_CTRL(EIM_DA3__IPU2_CSI1_DATA06, CSI_PAD_CTRL), /* GPIO3[3] */
+ IOMUX_PAD_CTRL(EIM_DA4__IPU2_CSI1_DATA05, CSI_PAD_CTRL), /* GPIO3[4] */
+ IOMUX_PAD_CTRL(EIM_DA5__IPU2_CSI1_DATA04, CSI_PAD_CTRL), /* GPIO3[5] */
+ IOMUX_PAD_CTRL(EIM_DA6__IPU2_CSI1_DATA03, CSI_PAD_CTRL), /* GPIO3[6] */
+ IOMUX_PAD_CTRL(EIM_DA7__IPU2_CSI1_DATA02, CSI_PAD_CTRL), /* GPIO3[7] */
+ IOMUX_PAD_CTRL(EIM_DA8__IPU2_CSI1_DATA01, CSI_PAD_CTRL), /* GPIO3[8] */
+ IOMUX_PAD_CTRL(EIM_DA9__IPU2_CSI1_DATA00, CSI_PAD_CTRL), /* GPIO3[9] */
+ IOMUX_PAD_CTRL(EIM_A16__IPU2_CSI1_PIXCLK, CSI_PAD_CTRL), /* GPIO2[22] - pin A8 */
+#endif
+
+ /* Not used, but MUST be in GPIO mode */
+ IOMUX_PAD_CTRL(EIM_DA10__GPIO3_IO10, WEAK_PULLUP), /* IPU2_CSI1_DATA_EN not used (pin B5 stat2) */
+ IOMUX_PAD_CTRL(EIM_DA11__GPIO3_IO11, WEAK_PULLUP), /* HSYNC - pin A5 stat0 */
+ IOMUX_PAD_CTRL(EIM_DA12__GPIO3_IO12, WEAK_PULLUP), /* VSYNC - pin A6 stat1 */
+
+#define GP_GS2971_SMPTE_BYPASS IMX_GPIO_NR(2, 24)
+ IOMUX_PAD_CTRL(EIM_CS1__GPIO2_IO24, WEAK_PULLUP), /* pin G7 - i/o SMPTE bypass */
+#define GP_GS2971_RESET IMX_GPIO_NR(3, 13)
+ IOMUX_PAD_CTRL(EIM_DA13__GPIO3_IO13, OUTPUT_40OHM), /* 0 - pin C7 - reset */
+#define GP_GS2971_DVI_LOCK IMX_GPIO_NR(3, 14)
+ IOMUX_PAD_CTRL(EIM_DA14__GPIO3_IO14, WEAK_PULLUP), /* pin B6 - stat3 - DVI_LOCK */
+#define GP_GS2971_DATA_ERR IMX_GPIO_NR(3, 15)
+ IOMUX_PAD_CTRL(EIM_DA15__GPIO3_IO15, WEAK_PULLUP), /* pin C6 - stat5 - DATA error */
+#define GP_GS2971_LB_CONT IMX_GPIO_NR(3, 20)
+ IOMUX_PAD_CTRL(EIM_D20__GPIO3_IO20, WEAK_PULLUP), /* pin A3 - LB control - float, analog input */
+#define GP_GS2971_Y_1ANC IMX_GPIO_NR(4, 26)
+ IOMUX_PAD_CTRL(DISP0_DAT5__GPIO4_IO26, WEAK_PULLUP), /* pin C5 - stat4 - 1ANC - Y signal detect */
+#define GP_GS2971_RC_BYPASS IMX_GPIO_NR(4, 27)
+ IOMUX_PAD_CTRL(DISP0_DAT6__GPIO4_IO27, OUTPUT_40OHM), /* 0 - pin G3 - RC bypass - output is buffered(low) */
+#define GP_GS2971_IOPROC_EN IMX_GPIO_NR(4, 28)
+ IOMUX_PAD_CTRL(DISP0_DAT7__GPIO4_IO28, OUTPUT_40OHM), /* 0 - pin H8 - io(A/V) processor enable */
+#define GP_GS2971_AUDIO_EN IMX_GPIO_NR(4, 29)
+ IOMUX_PAD_CTRL(DISP0_DAT8__GPIO4_IO29, OUTPUT_40OHM), /* 0 - pin H3 - Audio Enable */
+#define GP_GS2971_TIM_861 IMX_GPIO_NR(4, 30)
+ IOMUX_PAD_CTRL(DISP0_DAT9__GPIO4_IO30, OUTPUT_40OHM), /* 0 - pin H5 - TIM861 timing format, 0-use HSYNC/VSYNC */
+#define GP_GS2971_SW_EN IMX_GPIO_NR(4, 31)
+ IOMUX_PAD_CTRL(DISP0_DAT10__GPIO4_IO31, OUTPUT_40OHM), /* 0 - pin D7 - SW_EN - line lock enable */
+#define GP_GS2971_STANDBY IMX_GPIO_NR(5, 0)
+ IOMUX_PAD_CTRL(EIM_WAIT__GPIO5_IO00, OUTPUT_40OHM), /* 1 - pin K2 - Standby */
+#define GP_GS2971_DVB_ASI IMX_GPIO_NR(5, 5)
+ IOMUX_PAD_CTRL(DISP0_DAT11__GPIO5_IO05, WEAK_PULLUP), /* pin G8 i/o DVB_ASI */
+
+ IOMUX_PAD_CTRL(KEY_ROW1__AUD5_RXD, AUD_PAD_CTRL), /* pin J3 - AOUT1/2 */
+ IOMUX_PAD_CTRL(DISP0_DAT14__AUD5_RXC, AUD_PAD_CTRL), /* pin J4 - ACLK*/
+ IOMUX_PAD_CTRL(DISP0_DAT13__AUD5_RXFS, AUD_PAD_CTRL), /* pin H4 - WCLK*/
+
+ /* UART1 */
+ IOMUX_PAD_CTRL(CSI0_DAT10__UART1_TX_DATA, UART_PAD_CTRL),
+ IOMUX_PAD_CTRL(CSI0_DAT11__UART1_RX_DATA, UART_PAD_CTRL),
+
+ /* UART2 for debug */
+ IOMUX_PAD_CTRL(EIM_D26__UART2_TX_DATA, UART_PAD_CTRL),
+ IOMUX_PAD_CTRL(EIM_D27__UART2_RX_DATA, UART_PAD_CTRL),
+
+ /* UART3 */
+ IOMUX_PAD_CTRL(EIM_D24__UART3_TX_DATA, UART_PAD_CTRL),
+ IOMUX_PAD_CTRL(EIM_D25__UART3_RX_DATA, UART_PAD_CTRL),
+
+ /* UART4 */
+ IOMUX_PAD_CTRL(KEY_COL0__UART4_TX_DATA, UART_PAD_CTRL),
+ IOMUX_PAD_CTRL(KEY_ROW0__UART4_RX_DATA, UART_PAD_CTRL),
+
+ /* UART5 */
+ IOMUX_PAD_CTRL(CSI0_DAT14__UART5_TX_DATA, UART_PAD_CTRL),
+ IOMUX_PAD_CTRL(CSI0_DAT15__UART5_RX_DATA, UART_PAD_CTRL),
+
+ /* UART6/7 on sc16is752 on i2c2 */
+#define GP_SC16IS752_IRQ IMX_GPIO_NR(4, 10)
+ IOMUX_PAD_CTRL(KEY_COL2__GPIO4_IO10, WEAK_PULLUP), /* irq */
+
+ /* USBH1 */
+ IOMUX_PAD_CTRL(EIM_D30__USB_H1_OC, WEAK_PULLUP),
+#define GP_USB_HUB_RESET IMX_GPIO_NR(7, 12)
+ IOMUX_PAD_CTRL(GPIO_17__GPIO7_IO12, OUTPUT_40OHM), /* USB Hub Reset for USB2512 4 port hub */
+ /*
+ * port1 - 10/100 ethernet using AX88772A on J90
+ * port2 - usb connector on J26
+ * port3 - usb connector on J25
+ * port4 - usb connector on J96
+ */
+#define GP_AX88772A_RESET IMX_GPIO_NR(5, 20)
+ IOMUX_PAD_CTRL(CSI0_DATA_EN__GPIO5_IO20, OUTPUT_40OHM),
+
+ /* USBOTG - J80 */
+ IOMUX_PAD_CTRL(GPIO_1__USB_OTG_ID, WEAK_PULLUP),
+ IOMUX_PAD_CTRL(KEY_COL4__USB_OTG_OC, WEAK_PULLUP),
+#define GP_USB_OTG_PWR IMX_GPIO_NR(3, 22)
+ IOMUX_PAD_CTRL(EIM_D22__GPIO3_IO22, OUTPUT_40OHM),
+
+ /* USDHC1: Full size SD card holder - J88 */
+ IOMUX_PAD_CTRL(SD1_CLK__SD1_CLK, USDHC_PAD_CTRL),
+ IOMUX_PAD_CTRL(SD1_CMD__SD1_CMD, USDHC_PAD_CTRL),
+ IOMUX_PAD_CTRL(SD1_DAT0__SD1_DATA0, USDHC_PAD_CTRL),
+ IOMUX_PAD_CTRL(SD1_DAT1__SD1_DATA1, USDHC_PAD_CTRL),
+ IOMUX_PAD_CTRL(SD1_DAT2__SD1_DATA2, USDHC_PAD_CTRL),
+ IOMUX_PAD_CTRL(SD1_DAT3__SD1_DATA3, USDHC_PAD_CTRL),
+#define GP_USDHC1_CD IMX_GPIO_NR(1, 4)
+ IOMUX_PAD_CTRL(GPIO_4__GPIO1_IO04, WEAK_PULLUP),
+#define GP_USDHC1_WP IMX_GPIO_NR(1, 2)
+ IOMUX_PAD_CTRL(GPIO_2__GPIO1_IO02, WEAK_PULLUP),
+ /* Needs to invert and use key_col1 */
+#define GP_USDHC1_POWER_SEL IMX_GPIO_NR(7, 13) /* low 1.8V, high 3.3V */
+ IOMUX_PAD_CTRL(GPIO_18__GPIO7_IO13, OUTPUT_40OHM),
+
+ /* USDHC2: micro sd - J87 */
+ IOMUX_PAD_CTRL(SD2_CLK__SD2_CLK, USDHC_PAD_CTRL),
+ IOMUX_PAD_CTRL(SD2_CMD__SD2_CMD, USDHC_PAD_CTRL),
+ IOMUX_PAD_CTRL(SD2_DAT0__SD2_DATA0, USDHC_PAD_CTRL),
+ IOMUX_PAD_CTRL(SD2_DAT1__SD2_DATA1, USDHC_PAD_CTRL),
+ IOMUX_PAD_CTRL(SD2_DAT2__SD2_DATA2, USDHC_PAD_CTRL),
+ IOMUX_PAD_CTRL(SD2_DAT3__SD2_DATA3, USDHC_PAD_CTRL),
+#define GP_USDHC2_CD IMX_GPIO_NR(3, 23)
+ IOMUX_PAD_CTRL(EIM_D23__GPIO3_IO23, WEAK_PULLUP),
+
+ /* USDHC3 - eMMC */
+ IOMUX_PAD_CTRL(SD3_CLK__SD3_CLK, USDHC_PAD_CTRL),
+ IOMUX_PAD_CTRL(SD3_CMD__SD3_CMD, USDHC_PAD_CTRL),
+ IOMUX_PAD_CTRL(SD3_DAT0__SD3_DATA0, USDHC_PAD_CTRL),
+ IOMUX_PAD_CTRL(SD3_DAT1__SD3_DATA1, USDHC_PAD_CTRL),
+ IOMUX_PAD_CTRL(SD3_DAT2__SD3_DATA2, USDHC_PAD_CTRL),
+ IOMUX_PAD_CTRL(SD3_DAT3__SD3_DATA3, USDHC_PAD_CTRL),
+ IOMUX_PAD_CTRL(SD3_DAT4__SD3_DATA4, USDHC_PAD_CTRL),
+ IOMUX_PAD_CTRL(SD3_DAT5__SD3_DATA5, USDHC_PAD_CTRL),
+ IOMUX_PAD_CTRL(SD3_DAT6__SD3_DATA6, USDHC_PAD_CTRL),
+ IOMUX_PAD_CTRL(SD3_DAT7__SD3_DATA7, USDHC_PAD_CTRL),
+#define GP_EMMC_RESET IMX_GPIO_NR(7, 8)
+ IOMUX_PAD_CTRL(SD3_RST__GPIO7_IO08, OUTPUT_40OHM), /* eMMC reset */
+};
+
+static const struct i2c_pads_info i2c_pads[] = {
+ /* I2C1, SGTL5000 */
+ I2C_PADS_INFO_ENTRY(I2C1, EIM_D21, 3, 21, EIM_D28, 3, 28, I2C_PAD_CTRL),
+ /* I2C2 Camera, MIPI */
+ I2C_PADS_INFO_ENTRY(I2C2, KEY_COL3, 4, 12, KEY_ROW3, 4, 13, I2C_PAD_CTRL),
+ /* I2C3, J15 - RGB connector */
+ I2C_PADS_INFO_ENTRY(I2C3, GPIO_5, 1, 05, GPIO_16, 7, 11, I2C_PAD_CTRL),
+};
+#define I2C_BUS_CNT 3
+
+#ifdef CONFIG_USB_EHCI_MX6
+int board_ehci_hcd_init(int port)
+{
+ /* Reset USB hub */
+ if (port) {
+ gpio_set_value(GP_USB_HUB_RESET, 0);
+ gpio_set_value(GP_AX88772A_RESET, 0);
+ mdelay(2);
+ gpio_set_value(GP_USB_HUB_RESET, 1);
+ gpio_set_value(GP_AX88772A_RESET, 1);
+ }
+ return 0;
+}
+
+int board_ehci_power(int port, int on)
+{
+ if (port)
+ return 0;
+ gpio_set_value(GP_USB_OTG_PWR, on);
+ return 0;
+}
+
+#endif
+
+#ifdef CONFIG_FSL_ESDHC
+struct fsl_esdhc_cfg board_usdhc_cfg[] = {
+ {.esdhc_base = USDHC1_BASE_ADDR, .bus_width = 4,
+ .gp_cd = GP_USDHC1_CD},
+ {.esdhc_base = USDHC2_BASE_ADDR, .bus_width = 4,
+ .gp_cd = GP_USDHC2_CD},
+ {.esdhc_base = USDHC3_BASE_ADDR, .bus_width = 8,
+ .gp_reset = GP_EMMC_RESET},
+};
+#endif
+
+int board_spi_cs_gpio(unsigned bus, unsigned cs)
+{
+ return (bus == 0 && cs == 0) ? GP_ECSPI1_NOR_CS : -1;
+}
+
+#if defined(CONFIG_VIDEO_IPUV3)
+
+static const struct display_info_t displays[] = {
+ /* hdmi */
+ VD_1280_720M_60(HDMI, fbp_detect_i2c, 1, 0x50),
+ VD_1920_1080M_60(HDMI, NULL, 1, 0x50),
+ VD_1024_768M_60(HDMI, NULL, 1, 0x50),
+};
+#define display_cnt ARRAY_SIZE(displays)
+#else
+#define displays NULL
+#define display_cnt 0
+#endif
+
+
+static const unsigned short gpios_out_low[] = {
+ GP_EMMC_RESET, /* hold in reset */
+ GP_USB_OTG_PWR, /* disable USB otg power */
+ GP_USB_HUB_RESET, /* disable hub */
+ GP_AX88772A_RESET,
+ GP_RGMII_PHY_RESET,
+ GP_PCIE_RESET,
+ GP_GS2971_RESET,
+ GP_GS2971_RC_BYPASS,
+ GP_GS2971_IOPROC_EN,
+ GP_GS2971_AUDIO_EN,
+ GP_GS2971_TIM_861,
+ GP_GS2971_SW_EN,
+ GP_GS2971_DVB_ASI,
+ GP_ADV7391_RESET,
+ GP_J92_PIN9,
+};
+
+static const unsigned short gpios_out_high[] = {
+ GP_PWR_J1,
+ GP_PWR_J2,
+ GP_PWR_J3,
+ GP_PWR_J4,
+ GP_PWR_J5V,
+ GP_PWR_J12V,
+ GP_ECSPI1_NOR_CS, /* SS1 of spi nor */
+ GP_ECSPI3_GS2971_CS,
+ GP_USDHC1_POWER_SEL, /* high=3.3v */
+ GP_GS2971_STANDBY,
+ GP_J92_PIN7,
+};
+
+static const unsigned short gpios_in[] = {
+ GP_USDHC1_CD,
+ GP_USDHC2_CD,
+ GP_GS2971_SMPTE_BYPASS,
+ GP_GS2971_DVI_LOCK,
+ GP_GS2971_DATA_ERR,
+ GP_GS2971_LB_CONT,
+ GP_GS2971_Y_1ANC,
+ GP_J92_PIN10,
+ GP_J92_PIN12,
+ GP_BT_GPIO1,
+ GP_BT_GPIO2,
+ GP_BT_GPIO3,
+ GP_BT_GPIO4,
+ GP_BT_GPIO5,
+ GP_BT_GPIO6,
+ GP_BT_GPIO7,
+ GP_BT_GPIO8,
+ GP_BT_GPIO9,
+ GP_BT_GPIO10,
+ GP_BT_GPIO11,
+ GP_BT_GPIO12,
+ GP_BT_GPIO13,
+ GP_BT_GPIO14,
+ GP_BT_GPIO15,
+ GP_BT_GPIO16,
+ GP_BT_GPIO17,
+ GP_BT_GPIO18,
+ GP_BT_GPIO19,
+ GP_BT_GPIO20,
+ GP_BT_GPIO21,
+ GP_BT_GPIO22,
+ GP_BT_GPIO23,
+ GP_BT_GPIO24,
+ GP_BT_GPIO25,
+ GP_BT_GPIO26,
+ GP_BT_GPIO27,
+ GP_BT_GPIO28,
+ GP_BT_GPIO29,
+ GP_BT_GPIO30,
+ GP_BT_GPIO31,
+ GP_BT_GPIO32,
+ GP_BT_GPIO33,
+ GP_BT_GPIO34,
+ GP_BT_GPIO35,
+ GP_BT_GPIO36,
+ GP_BT_GPIO37,
+ GP_BT_GPIO38,
+ GP_BT_GPIO39,
+ GP_BT_GPIO40,
+ GP_TP81,
+};
+
+int board_early_init_f(void)
+{
+ set_gpios_in(gpios_in, ARRAY_SIZE(gpios_in));
+ set_gpios(gpios_out_high, ARRAY_SIZE(gpios_out_high), 1);
+ set_gpios(gpios_out_low, ARRAY_SIZE(gpios_out_low), 0);
+ SETUP_IOMUX_PADS(init_pads);
+ return 0;
+}
+
+int board_init(void)
+{
+ common_board_init(i2c_pads, I2C_BUS_CNT, IOMUXC_GPR1_OTG_ID_GPIO1,
+ displays, display_cnt, 0);
+ return 0;
+}
+
+const struct button_key board_buttons[] = {
+ {"tp81", GP_TP81, 't', 1},
+ {NULL, 0, 0, 0},
+};
+
+#ifdef CONFIG_CMD_BMODE
+const struct boot_mode board_boot_modes[] = {
+ /* 4 bit bus width */
+ {"mmc0", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
+ {"mmc1", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)},
+ {NULL, 0},
+};
+#endif
diff --git a/board/boundary/bt/bt2g.cfg b/board/boundary/bt/bt2g.cfg
new file mode 100644
index 00000000000..8fee595914a
--- /dev/null
+++ b/board/boundary/bt/bt2g.cfg
@@ -0,0 +1,47 @@
+/*
+ * Copyright (C) 2013 Boundary Devices
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * Refer doc/README.imximage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+
+/* image version */
+IMAGE_VERSION 2
+
+/*
+ * Boot Device : one of
+ * spi, sd (the board has no nand neither onenand)
+ */
+BOOT_FROM spi
+
+#define __ASSEMBLY__
+#include <config.h>
+#include "asm/arch/mx6-ddr.h"
+#include "asm/arch/iomux.h"
+#include "asm/arch/crm_regs.h"
+
+/* NC YET */
+#define MX6_MMDC_P0_MPDGCTRL0_VAL 0x42740304
+#define MX6_MMDC_P0_MPDGCTRL1_VAL 0x026e0265
+#define MX6_MMDC_P1_MPDGCTRL0_VAL 0x02750306
+#define MX6_MMDC_P1_MPDGCTRL1_VAL 0x02720244
+#define MX6_MMDC_P0_MPRDDLCTL_VAL 0x463d4041
+#define MX6_MMDC_P1_MPRDDLCTL_VAL 0x42413c47
+#define MX6_MMDC_P0_MPWRDLCTL_VAL 0x37414441
+#define MX6_MMDC_P1_MPWRDLCTL_VAL 0x4633473b
+#define MX6_MMDC_P0_MPWLDECTRL0_VAL 0x0025001f
+#define MX6_MMDC_P0_MPWLDECTRL1_VAL 0x00290027
+#define MX6_MMDC_P1_MPWLDECTRL0_VAL 0x001f002b
+#define MX6_MMDC_P1_MPWLDECTRL1_VAL 0x000f0029
+#define WALAT 1
+
+#include "../common/mx6/ddr-setup.cfg"
+#define RANK 0
+#define BUS_WIDTH 64
+/* MT41K256M16HA-125 IT:E */
+#include "../common/mx6/1066mhz_256mx16.cfg"
+#include "../common/mx6/clocks.cfg"
diff --git a/board/boundary/bt/bt4g.cfg b/board/boundary/bt/bt4g.cfg
new file mode 100644
index 00000000000..39813ac9d7d
--- /dev/null
+++ b/board/boundary/bt/bt4g.cfg
@@ -0,0 +1,47 @@
+/*
+ * Copyright (C) 2013 Boundary Devices
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * Refer doc/README.imximage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+
+/* image version */
+IMAGE_VERSION 2
+
+/*
+ * Boot Device : one of
+ * spi, sd (the board has no nand neither onenand)
+ */
+BOOT_FROM spi
+
+#define __ASSEMBLY__
+#include <config.h>
+#include "asm/arch/mx6-ddr.h"
+#include "asm/arch/iomux.h"
+#include "asm/arch/crm_regs.h"
+
+/* NC YET */
+#define MX6_MMDC_P0_MPDGCTRL0_VAL 0x433C0350
+#define MX6_MMDC_P0_MPDGCTRL1_VAL 0x03400338
+#define MX6_MMDC_P1_MPDGCTRL0_VAL 0x433C0350
+#define MX6_MMDC_P1_MPDGCTRL1_VAL 0x03400304
+#define MX6_MMDC_P0_MPRDDLCTL_VAL 0x423A3E4A
+#define MX6_MMDC_P1_MPRDDLCTL_VAL 0x443A3648
+#define MX6_MMDC_P0_MPWRDLCTL_VAL 0x383E4238
+#define MX6_MMDC_P1_MPWRDLCTL_VAL 0x42364A3E
+#define MX6_MMDC_P0_MPWLDECTRL0_VAL 0x001f0024
+#define MX6_MMDC_P0_MPWLDECTRL1_VAL 0x00240021
+#define MX6_MMDC_P1_MPWLDECTRL0_VAL 0x00150028
+#define MX6_MMDC_P1_MPWLDECTRL1_VAL 0x0009001c
+#define WALAT 1
+
+#include "../common/mx6/ddr-setup.cfg"
+#define RANK 1
+#define BUS_WIDTH 64
+/* MT41K512M16TNA-125 IT:E */
+#include "../common/mx6/1066mhz_256mx16-hynix.cfg"
+#include "../common/mx6/clocks.cfg"
diff --git a/board/boundary/bt/spl.c b/board/boundary/bt/spl.c
new file mode 100644
index 00000000000..f95099671be
--- /dev/null
+++ b/board/boundary/bt/spl.c
@@ -0,0 +1,112 @@
+/*
+ * Copyright (C) 2010-2013 Freescale Semiconductor, Inc.
+ * Copyright (C) 2013, Boundary Devices <info@boundarydevices.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/sys_proto.h>
+#include <malloc.h>
+#include <asm/arch/mx6-pins.h>
+#include <linux/errno.h>
+#include <asm/gpio.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <mmc.h>
+#include <fsl_esdhc.h>
+#include <linux/fb.h>
+#include <ipu_pixfmt.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/mxc_hdmi.h>
+#include <asm/arch/mx6-ddr.h>
+#include <asm/mach-imx/boot_mode.h>
+
+#include <i2c.h>
+#include <spl.h>
+
+#if 0
+void board_init_f(ulong dummy)
+{
+#if 0
+ arch_cpu_init();
+ board_early_init_f();
+ timer_init();
+ preloader_console_init();
+
+ print_cpuinfo();
+ board_init_r(NULL, 0);
+#endif
+}
+#endif
+
+void spl_board_init(void)
+{
+#if 0
+ int i;
+ u32 const *regs ;
+ int num_regs;
+ unsigned char mac_address[6];
+ imx_get_mac_from_fuse(0,mac_address);
+ printf("ethaddr: %pM\n", mac_address);
+
+ if (is_cpu_type(MXC_CPU_MX6Q)) {
+#if 1
+ regs = mx6q_1g;
+ num_regs = ARRAY_SIZE(mx6q_1g);
+#else
+ regs = mx6q_2g;
+ num_regs = ARRAY_SIZE(mx6q_2g);
+#endif
+ } else {
+#if CONFIG_DDR_MB == 512
+ regs = mx6dl_512m;
+ num_regs = ARRAY_SIZE(mx6dl_512m);
+printf("Configuring for 512MiB narrow memory bus\n");
+#elif CONFIG_DDR_MB == 1024
+ regs = mx6dl_1gn;
+ num_regs = ARRAY_SIZE(mx6dl_1gn);
+printf("Configuring for 1GiB narrow memory bus\n");
+#elif CONFIG_DDR_MB == 2048
+ regs = mx6dl_2g;
+ num_regs = ARRAY_SIZE(mx6dl_2g);
+printf("Configuring for 2GiB wide memory bus\n");
+#endif
+ }
+ for (i=0; i < num_regs; i+=2) {
+ writel(regs[i+1],regs[i]);
+ }
+ dram_init();
+#endif
+ printf("%s\n", __func__);
+}
+
+u32 spl_boot_device(void)
+{
+ printf("%s\n", __func__);
+#if 0
+ unsigned reg;
+ struct src *psrc = (struct src *)SRC_BASE_ADDR;
+ printf("%s: sbmr1 == 0x%08x\n", __func__, psrc->sbmr1);
+ printf("%s: gpr9 == 0x%08x\n", __func__, psrc->gpr9);
+ printf("%s: gpr10 == 0x%08x\n", __func__, psrc->gpr10);
+ return BOOT_DEVICE_USB;
+#endif
+#if 1
+ return BOOT_DEVICE_SPI;
+#endif
+}
+
+#if 0
+void spl_usb_load_image(void)
+{
+ boot_mode_apply(MAKE_CFGVAL(0x01, 0x00, 0x00, 0x00));
+ reset_cpu(0);
+}
+
+#endif
diff --git a/configs/bt2g_defconfig b/configs/bt2g_defconfig
new file mode 100644
index 00000000000..121aaff23a6
--- /dev/null
+++ b/configs/bt2g_defconfig
@@ -0,0 +1,72 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_SYS_TEXT_BASE=0x17800000
+CONFIG_TARGET_BT=y
+CONFIG_ENV_VARS_UBOOT_CONFIG=y
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/bt/bt2g.cfg,MX6Q,DDR_MB=2048,DEFCONFIG=\"bt2g\""
+CONFIG_BOOTDELAY=3
+CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
+CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_SYS_ALT_MEMTEST=y
+CONFIG_CMD_DFU=y
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+# CONFIG_RANDOM_UUID is not set
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PART=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_PARTITION_TYPE_GUID=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x12000000
+CONFIG_FASTBOOT_BUF_SIZE=0x26000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=2
+CONFIG_FSL_ESDHC=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_SST=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_MICREL=y
+CONFIG_PHY_MICREL_KSZ90X1=y
+CONFIG_NETDEVICES=y
+CONFIG_FEC_MXC=y
+CONFIG_SPI=y
+CONFIG_MXC_SPI=y
+CONFIG_USB=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_KEYBOARD=y
+CONFIG_SYS_USB_EVENT_POLL_VIA_CONTROL_EP=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="Boundary"
+CONFIG_USB_GADGET_VENDOR_NUM=0x0525
+CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
+CONFIG_CI_UDC=y
+CONFIG_USB_ETHER=y
+CONFIG_USB_ETH_CDC=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_USB_ETHER_MCS7830=y
+CONFIG_USB_ETHER_SMSC95XX=y
+CONFIG_VIDEO=y
+# CONFIG_VIDEO_SW_CURSOR is not set
+CONFIG_OF_LIBFDT=y
diff --git a/configs/bt4g_defconfig b/configs/bt4g_defconfig
new file mode 100644
index 00000000000..b74fdaf447f
--- /dev/null
+++ b/configs/bt4g_defconfig
@@ -0,0 +1,72 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_SYS_TEXT_BASE=0x17800000
+CONFIG_TARGET_BT=y
+CONFIG_ENV_VARS_UBOOT_CONFIG=y
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/bt/bt4g.cfg,MX6Q,DDR_MB=3840,DEFCONFIG=\"bt4g\""
+CONFIG_BOOTDELAY=3
+CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
+CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_SYS_ALT_MEMTEST=y
+CONFIG_CMD_DFU=y
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+# CONFIG_RANDOM_UUID is not set
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PART=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_PARTITION_TYPE_GUID=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x12000000
+CONFIG_FASTBOOT_BUF_SIZE=0x26000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=2
+CONFIG_FSL_ESDHC=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_SST=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_MICREL=y
+CONFIG_PHY_MICREL_KSZ90X1=y
+CONFIG_NETDEVICES=y
+CONFIG_FEC_MXC=y
+CONFIG_SPI=y
+CONFIG_MXC_SPI=y
+CONFIG_USB=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_KEYBOARD=y
+CONFIG_SYS_USB_EVENT_POLL_VIA_CONTROL_EP=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="Boundary"
+CONFIG_USB_GADGET_VENDOR_NUM=0x0525
+CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
+CONFIG_CI_UDC=y
+CONFIG_USB_ETHER=y
+CONFIG_USB_ETH_CDC=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_USB_ETHER_MCS7830=y
+CONFIG_USB_ETHER_SMSC95XX=y
+CONFIG_VIDEO=y
+# CONFIG_VIDEO_SW_CURSOR is not set
+CONFIG_OF_LIBFDT=y
diff --git a/include/configs/bt.h b/include/configs/bt.h
new file mode 100644
index 00000000000..03279c9c02e
--- /dev/null
+++ b/include/configs/bt.h
@@ -0,0 +1,27 @@
+/*
+ * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
+ *
+ * Configuration settings for the Boundary Devices bt
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include "mx6_common.h"
+
+#define CONFIG_MACH_TYPE 3780
+
+#define CONFIG_IMX_HDMI
+#define CONFIG_SYS_FSL_USDHC_NUM 3
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
+#define BD_I2C_MASK 7
+#define BD_CMA "384M"
+
+#include "boundary.h"
+#define CONFIG_EXTRA_ENV_SETTINGS BD_BOUNDARY_ENV_SETTINGS \
+ "cmd_custom=setenv bootargs $bootargs pci=nomsi pcie.force_gen=1 coherent_pool=32M\0" \
+
+
+#endif /* __CONFIG_H */
--
GitLab