From 2740e5de4f3cd0aa36efcfe1a995fb6e3858cc97 Mon Sep 17 00:00:00 2001 From: Fabio Estevam <fabio.estevam@freescale.com> Date: Tue, 29 Oct 2013 15:46:21 -0200 Subject: [PATCH] video: ipu_disp: Fix clock polarity logic Currently the HDMI splash screen image quality on mx6solo does not show a very stable image. By comparing the IPU driver from U-boot with the one from FSL 4.1.0 BSP, we can see that there is an inverted logic for setting the DI_GEN_POL_CLK bit. >From FSL BSP [1] we have: if (!sig.clk_pol) di_gen |= DI_GEN_POLARITY_DISP_CLK; Applying the same logic into U-boot fixes the HDMI image stability. [1] git.freescale.com/git/cgit.cgi/imx/linux-2.6-imx.git/tree/drivers/mxc/ipu3/ipu_disp.c?h=imx_3.0.35_4.1.0 Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Tested-by: Eric Nelson <eric.nelson@boundarydevices.com> Acked-by: Eric Nelson <eric.nelson@boundarydevices.com> Acked-by: Stefano Babic <sbabic@denx.de> --- drivers/video/ipu_disp.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/video/ipu_disp.c b/drivers/video/ipu_disp.c index 2e913561d08..22ac1429ba4 100644 --- a/drivers/video/ipu_disp.c +++ b/drivers/video/ipu_disp.c @@ -1178,7 +1178,7 @@ int32_t ipu_init_sync_panel(int disp, uint32_t pixel_clk, if (sig.Vsync_pol) di_gen |= DI_GEN_POLARITY_3; - if (sig.clk_pol) + if (!sig.clk_pol) di_gen |= DI_GEN_POL_CLK; } -- GitLab