From 273a28ad9ef59dcfcd4c056ec1f61f1e0896cfaa Mon Sep 17 00:00:00 2001 From: Poonam Aggrwal <poonam.aggrwal@freescale.com> Date: Tue, 27 Oct 2009 09:36:38 +0530 Subject: [PATCH] 85xx/p1_p2_rdb: Fixing DDR configuration for 800MHz data rate Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> --- board/freescale/p1_p2_rdb/ddr.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/board/freescale/p1_p2_rdb/ddr.c b/board/freescale/p1_p2_rdb/ddr.c index 5cb4a13e085..fccc4f8f589 100644 --- a/board/freescale/p1_p2_rdb/ddr.c +++ b/board/freescale/p1_p2_rdb/ddr.c @@ -85,8 +85,8 @@ extern void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, #define CONFIG_SYS_DDR_TIMING_0_800 0x55770802 #define CONFIG_SYS_DDR_TIMING_1_800 0x6f6b6543 #define CONFIG_SYS_DDR_TIMING_2_800 0x0fa074d1 -#define CONFIG_SYS_DDR_CLK_CTRL_800 0x02000000 -#define CONFIG_SYS_DDR_MODE_1_800 0x00440862 +#define CONFIG_SYS_DDR_CLK_CTRL_800 0x02800000 +#define CONFIG_SYS_DDR_MODE_1_800 0x00040852 #define CONFIG_SYS_DDR_MODE_2_800 0x00000000 #define CONFIG_SYS_DDR_INTERVAL_800 0x0a280100 -- GitLab