diff --git a/arch/arm/cpu/armv7/mx7/Kconfig b/arch/arm/cpu/armv7/mx7/Kconfig
index 892ffae30951e160b1088da10da8397de7eee70c..ea19e5c411fe60c4307c4ab3b2a0aee8905b8595 100644
--- a/arch/arm/cpu/armv7/mx7/Kconfig
+++ b/arch/arm/cpu/armv7/mx7/Kconfig
@@ -13,7 +13,6 @@ choice
config TARGET_MX7DSABRESD
bool "mx7dsabresd"
- select CPU_V7
select DM
select DM_THERMAL
diff --git a/arch/arm/cpu/armv7/mx7/soc.c b/arch/arm/cpu/armv7/mx7/soc.c
index 8d50149582faf54ddfe71c9a64df64588c083601..2ed05ea4f941ad446bf3fa237984f46fc45a94a4 100644
--- a/arch/arm/cpu/armv7/mx7/soc.c
+++ b/arch/arm/cpu/armv7/mx7/soc.c
@@ -15,8 +15,6 @@
#include <dm.h>
#include <imx_thermal.h>
-struct src *src_reg = (struct src *)SRC_BASE_ADDR;
-
#if defined(CONFIG_IMX_THERMAL)
static const struct imx_thermal_plat imx7_thermal_plat = {
.regs = (void *)ANATOP_BASE_ADDR,
@@ -81,7 +79,7 @@ u32 get_cpu_temp_grade(int *minc, int *maxc)
val &= 0x3;
if (minc && maxc) {
- if ( val == TEMP_AUTOMOTIVE) {
+ if (val == TEMP_AUTOMOTIVE) {
*minc = -40;
*maxc = 125;
} else if (val == TEMP_INDUSTRIAL) {
diff --git a/arch/arm/imx-common/init.c b/arch/arm/imx-common/init.c
index 56d501044991626fc7eb9a04cac0dab1f0d37a92..15dab1d904239accc3676956ec5a8acbf3d8e444 100644
--- a/arch/arm/imx-common/init.c
+++ b/arch/arm/imx-common/init.c
@@ -44,8 +44,7 @@ void init_aips(void)
writel(0x00000000, &aips2->opacr3);
writel(0x00000000, &aips2->opacr4);
- if (is_cpu_type(MXC_CPU_MX6SX) || is_soc_type(MXC_SOC_MX7))
- {
+ if (is_cpu_type(MXC_CPU_MX6SX) || is_soc_type(MXC_SOC_MX7)) {
/*
* Set all MPROTx to be non-bufferable, trusted for R/W,
* not forced to user-mode.
@@ -103,6 +102,7 @@ void init_src(void)
writel(val, &src_regs->scr);
}
+#ifdef CONFIG_CMD_BMODE
void boot_mode_apply(unsigned cfg_val)
{
unsigned reg;
@@ -115,3 +115,4 @@ void boot_mode_apply(unsigned cfg_val)
reg &= ~(1 << 28);
writel(reg, &psrc->gpr10);
}
+#endif
diff --git a/arch/arm/imx-common/iomux-v3.c b/arch/arm/imx-common/iomux-v3.c
index b4f481fa53b2376387b692bae10bc2dac8eca221..228d5f8f1cb75c88a39c79794607072da8942bb9 100644
--- a/arch/arm/imx-common/iomux-v3.c
+++ b/arch/arm/imx-common/iomux-v3.c
@@ -11,10 +11,8 @@
#include <common.h>
#include <asm/io.h>
#include <asm/arch/imx-regs.h>
-#if !defined(CONFIG_MX25) && !defined(CONFIG_VF610)
-#include <asm/arch/sys_proto.h>
-#endif
#include <asm/imx-common/iomux-v3.h>
+#include <asm/imx-common/sys_proto.h>
static void *base = (void *)IOMUXC_BASE_ADDR;
@@ -53,7 +51,7 @@ void imx_iomux_v3_setup_pad(iomux_v3_cfg_t pad)
}
#endif
- if (mux_ctrl_ofs)
+ if (is_soc_type(MXC_SOC_MX7) || mux_ctrl_ofs)
__raw_writel(mux_mode, base + mux_ctrl_ofs);
if (sel_input_ofs)
diff --git a/board/aristainetos/MAINTAINERS b/board/aristainetos/MAINTAINERS
index 78c9b693e1c5ec14a36b16dfde5a510686b5c4bd..b463f7b1763adb945fb0477441cb3cc3c6ed4e20 100644
--- a/board/aristainetos/MAINTAINERS
+++ b/board/aristainetos/MAINTAINERS
@@ -6,3 +6,4 @@ F: include/configs/aristainetos.h
F: configs/aristainetos_defconfig
F: include/configs/aristainetos2.h
F: configs/aristainetos2_defconfig
+F: configs/aristainetos2b_defconfig
diff --git a/board/congatec/cgtqmx6eval/MAINTAINERS b/board/congatec/cgtqmx6eval/MAINTAINERS
index 35f4a2a21a981aca22f1d79e0934c1a62b4fd950..c41ebf5f9e5c5fae73d8c6258e45a7fc7af016f7 100644
--- a/board/congatec/cgtqmx6eval/MAINTAINERS
+++ b/board/congatec/cgtqmx6eval/MAINTAINERS
@@ -1,6 +1,6 @@
CGTQMX6EVAL BOARD
-#M: Leo Sartre <lsartre@adeneo-embedded.com>
-S: Orphan (since 2014-06)
+M: Otavio Salvador <otavio@ossystems.com.br>
+S: Maintained
F: board/congatec/cgtqmx6eval/
F: include/configs/cgtqmx6eval.h
F: configs/cgtqmx6qeval_defconfig
diff --git a/board/congatec/cgtqmx6eval/cgtqmx6eval.c b/board/congatec/cgtqmx6eval/cgtqmx6eval.c
index 574891e5ec6df3965c57f1890f46e214f10eb177..cf5607b2c808c3ac09491c86a498e3cca1aa1c4f 100644
--- a/board/congatec/cgtqmx6eval/cgtqmx6eval.c
+++ b/board/congatec/cgtqmx6eval/cgtqmx6eval.c
@@ -212,8 +212,7 @@ int power_init_board(void)
for (i = 0; i < ARRAY_SIZE(mipi_levels); i++) {
if (!strcmp(mipi_levels[i].name, lv_mipi)) {
- printf("set MIPI level %s\n",
- mipi_levels[i].name);
+ printf("set MIPI level %s\n", mipi_levels[i].name);
ret = pmic_reg_write(p, PFUZE100_VGEN4VOL,
mipi_levels[i].value);
if (ret)
diff --git a/board/freescale/mx6qsabreauto/MAINTAINERS b/board/freescale/mx6qsabreauto/MAINTAINERS
index fb65ce41232a1b9dbdd2c685d7a9e3ee259c2098..75a8862ef69647220c6c8e019c9ea497bf117dda 100644
--- a/board/freescale/mx6qsabreauto/MAINTAINERS
+++ b/board/freescale/mx6qsabreauto/MAINTAINERS
@@ -1,7 +1,9 @@
MX6QSABREAUTO BOARD
M: Fabio Estevam <fabio.estevam@freescale.com>
+M: Peng Fan <Peng.Fan@freescale.com>
S: Maintained
F: board/freescale/mx6qsabreauto/
F: include/configs/mx6qsabreauto.h
F: configs/mx6dlsabreauto_defconfig
F: configs/mx6qsabreauto_defconfig
+F: configs/mx6qpsabreauto_defconfig
diff --git a/board/freescale/mx6slevk/MAINTAINERS b/board/freescale/mx6slevk/MAINTAINERS
index 18d31a8d8b964c066bb5fd85135c7e0b60dfa64e..f4e74ba725c04ceb8e7c68c1b0c8f16ac971cbd1 100644
--- a/board/freescale/mx6slevk/MAINTAINERS
+++ b/board/freescale/mx6slevk/MAINTAINERS
@@ -1,7 +1,9 @@
MX6SLEVK BOARD
M: Fabio Estevam <fabio.estevam@freescale.com>
+M: Peng Fan <Peng.Fan@freescale.com>
S: Maintained
F: board/freescale/mx6slevk/
F: include/configs/mx6slevk.h
F: configs/mx6slevk_defconfig
+F: configs/mx6slevk_spl_defconfig
F: configs/mx6slevk_spinor_defconfig
diff --git a/board/freescale/mx6ul_14x14_evk/MAINTAINERS b/board/freescale/mx6ul_14x14_evk/MAINTAINERS
index 611feca106d10be9ae4685cb2f8083363a7e8869..d5f74b7ff41f7a62563e0d3b4514e7358caec196 100644
--- a/board/freescale/mx6ul_14x14_evk/MAINTAINERS
+++ b/board/freescale/mx6ul_14x14_evk/MAINTAINERS
@@ -4,3 +4,4 @@ S: Maintained
F: board/freescale/mx6ul_14x14_evk/
F: include/configs/mx6ul_14x14_evk.h
F: configs/mx6ul_14x14_evk_defconfig
+F: configs/mx6ul_9x9_evk_defconfig
diff --git a/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c b/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c
index 612fb788340e9a3967da562a15d73d3f774aeb5e..8650f350f3eb894e9c05f08ca9bc67881e5f1965 100644
--- a/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c
+++ b/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c
@@ -155,53 +155,10 @@ static void iox74lv_init(void)
gpio_direction_output(IOX_OE, 1);
};
-void iox74lv_set(int index)
-{
- int i;
-
- gpio_direction_output(IOX_OE, 0);
-
- for (i = 7; i >= 0; i--) {
- gpio_direction_output(IOX_SHCP, 0);
-
- if (i == index)
- gpio_direction_output(IOX_SDI, seq[qn_output[i]][0]);
- else
- gpio_direction_output(IOX_SDI, seq[qn_output[i]][1]);
- udelay(500);
- gpio_direction_output(IOX_SHCP, 1);
- udelay(500);
- }
-
- gpio_direction_output(IOX_STCP, 0);
- udelay(500);
- /*
- * shift register will be output to pins
- */
- gpio_direction_output(IOX_STCP, 1);
-
- for (i = 7; i >= 0; i--) {
- gpio_direction_output(IOX_SHCP, 0);
- gpio_direction_output(IOX_SDI, seq[qn_output[i]][1]);
- udelay(500);
- gpio_direction_output(IOX_SHCP, 1);
- udelay(500);
- }
-
- gpio_direction_output(IOX_STCP, 0);
- udelay(500);
- /*
- * shift register will be output to pins
- */
- gpio_direction_output(IOX_STCP, 1);
-
- gpio_direction_output(IOX_OE, 1);
-};
-
#ifdef CONFIG_SYS_I2C_MXC
#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
/* I2C1 for PMIC and EEPROM */
-struct i2c_pads_info i2c_pad_info1 = {
+static struct i2c_pads_info i2c_pad_info1 = {
.scl = {
.i2c_mode = MX6_PAD_UART4_TX_DATA__I2C1_SCL | PC,
.gpio_mode = MX6_PAD_UART4_TX_DATA__GPIO1_IO28 | PC,
@@ -356,7 +313,7 @@ static iomux_v3_cfg_t const quadspi_pads[] = {
MX6_PAD_NAND_DQS__QSPI_A_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
};
-int board_qspi_init(void)
+static int board_qspi_init(void)
{
/* Set the iomux */
imx_iomux_v3_setup_multiple_pads(quadspi_pads,
@@ -674,11 +631,6 @@ int board_late_init(void)
return 0;
}
-u32 get_board_rev(void)
-{
- return get_cpu_rev();
-}
-
int checkboard(void)
{
if (is_mx6ul_9x9_evk())
diff --git a/board/freescale/mx7dsabresd/Kconfig b/board/freescale/mx7dsabresd/Kconfig
index d7c6ae41fd0bb9197500cbab150a8773c5be5c5f..c6a969ca67ffaa7a171e2f359e592d2b354162af 100644
--- a/board/freescale/mx7dsabresd/Kconfig
+++ b/board/freescale/mx7dsabresd/Kconfig
@@ -6,9 +6,6 @@ config SYS_BOARD
config SYS_VENDOR
default "freescale"
-config SYS_SOC
- default "mx7"
-
config SYS_CONFIG_NAME
default "mx7dsabresd"
diff --git a/board/freescale/mx7dsabresd/mx7dsabresd.c b/board/freescale/mx7dsabresd/mx7dsabresd.c
index d163bee20f714db0f3705bb761549e8392396ed9..ee9890b599050e6add5c756c2b653a889b64522f 100644
--- a/board/freescale/mx7dsabresd/mx7dsabresd.c
+++ b/board/freescale/mx7dsabresd/mx7dsabresd.c
@@ -10,7 +10,6 @@
#include <asm/arch/sys_proto.h>
#include <asm/gpio.h>
#include <asm/imx-common/iomux-v3.h>
-#include <asm/imx-common/boot_mode.h>
#include <asm/io.h>
#include <linux/sizes.h>
#include <common.h>
@@ -24,6 +23,7 @@
#include <i2c.h>
#include <asm/imx-common/mxc_i2c.h>
#include <asm/arch/crm_regs.h>
+#include <usb/ehci-fsl.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -44,7 +44,7 @@ DECLARE_GLOBAL_DATA_PTR;
#ifdef CONFIG_SYS_I2C_MXC
#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
/* I2C1 for PMIC */
-struct i2c_pads_info i2c_pad_info1 = {
+static struct i2c_pads_info i2c_pad_info1 = {
.scl = {
.i2c_mode = MX7D_PAD_I2C1_SCL__I2C1_SCL | PC,
.gpio_mode = MX7D_PAD_I2C1_SCL__GPIO4_IO8 | PC,
@@ -156,7 +156,7 @@ static enum qn_func qn_output[8] = {
qn_enable
};
-void iox74lv_init(void)
+static void iox74lv_init(void)
{
int i;
@@ -190,44 +190,6 @@ void iox74lv_init(void)
gpio_direction_output(IOX_STCP, 1);
};
-void iox74lv_set(int index)
-{
- int i;
- for (i = 7; i >= 0; i--) {
- gpio_direction_output(IOX_SHCP, 0);
-
- if (i == index)
- gpio_direction_output(IOX_SDI, seq[qn_output[i]][0]);
- else
- gpio_direction_output(IOX_SDI, seq[qn_output[i]][1]);
- udelay(500);
- gpio_direction_output(IOX_SHCP, 1);
- udelay(500);
- }
-
- gpio_direction_output(IOX_STCP, 0);
- udelay(500);
- /*
- * shift register will be output to pins
- */
- gpio_direction_output(IOX_STCP, 1);
-
- for (i = 7; i >= 0; i--) {
- gpio_direction_output(IOX_SHCP, 0);
- gpio_direction_output(IOX_SDI, seq[qn_output[i]][1]);
- udelay(500);
- gpio_direction_output(IOX_SHCP, 1);
- udelay(500);
- }
-
- gpio_direction_output(IOX_STCP, 0);
- udelay(500);
- /*
- * shift register will be output to pins
- */
- gpio_direction_output(IOX_STCP, 1);
-};
-
#ifdef CONFIG_FEC_MXC
static iomux_v3_cfg_t const fec1_pads[] = {
MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
@@ -458,15 +420,6 @@ int board_init(void)
return 0;
}
-#ifdef CONFIG_CMD_BMODE
-static const struct boot_mode board_boot_modes[] = {
- /* 4 bit bus width */
- {"sd1", MAKE_CFGVAL(0x10, 0x10, 0x00, 0x00)},
- {"emmc", MAKE_CFGVAL(0x10, 0x2a, 0x00, 0x00)},
- {NULL, 0},
-};
-#endif
-
#ifdef CONFIG_POWER
#define I2C_PMIC 0
int power_init_board(void)
@@ -499,9 +452,7 @@ int power_init_board(void)
int board_late_init(void)
{
-#ifdef CONFIG_CMD_BMODE
- add_board_boot_modes(board_boot_modes);
-#endif
+ struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
#ifdef CONFIG_ENV_IS_IN_MMC
mmc_late_init();
@@ -509,14 +460,15 @@ int board_late_init(void)
imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
- set_wdog_reset((struct wdog_regs *)WDOG1_BASE_ADDR);
+ set_wdog_reset(wdog);
- return 0;
-}
+ /*
+ * Do not assert internal WDOG_RESET_B_DEB(controlled by bit 4),
+ * since we use PMIC_PWRON to reset the board.
+ */
+ clrsetbits_le16(&wdog->wcr, 0, 0x10);
-u32 get_board_rev(void)
-{
- return get_cpu_rev();
+ return 0;
}
int checkboard(void)
@@ -527,11 +479,11 @@ int checkboard(void)
}
#ifdef CONFIG_USB_EHCI_MX7
-iomux_v3_cfg_t const usb_otg1_pads[] = {
+static iomux_v3_cfg_t const usb_otg1_pads[] = {
MX7D_PAD_GPIO1_IO05__USB_OTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
};
-iomux_v3_cfg_t const usb_otg2_pads[] = {
+static iomux_v3_cfg_t const usb_otg2_pads[] = {
MX7D_PAD_UART3_CTS_B__USB_OTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
};
diff --git a/drivers/mtd/nand/mxs_nand.c b/drivers/mtd/nand/mxs_nand.c
index 1d689015a5a2294a1b7aa8bc3fe87575e0f5cc7d..f15cf36c88e713f1fd38de5648e38410f0611441 100644
--- a/drivers/mtd/nand/mxs_nand.c
+++ b/drivers/mtd/nand/mxs_nand.c
@@ -149,6 +149,13 @@ static inline uint32_t mxs_nand_get_ecc_strength(uint32_t page_data_size,
uint32_t page_oob_size)
{
int ecc_strength;
+ int max_ecc_strength_supported;
+
+ /* Refer to Chapter 17 for i.MX6DQ, Chapter 18 for i.MX6SX */
+ if (is_cpu_type(MXC_CPU_MX6SX))
+ max_ecc_strength_supported = 62;
+ else
+ max_ecc_strength_supported = 40;
/*
* Determine the ECC layout with the formula:
@@ -162,7 +169,7 @@ static inline uint32_t mxs_nand_get_ecc_strength(uint32_t page_data_size,
/ (galois_field *
mxs_nand_ecc_chunk_cnt(page_data_size));
- return round_down(ecc_strength, 2);
+ return min(round_down(ecc_strength, 2), max_ecc_strength_supported);
}
static inline uint32_t mxs_nand_get_mark_offset(uint32_t page_data_size,
diff --git a/drivers/watchdog/imx_watchdog.c b/drivers/watchdog/imx_watchdog.c
index 1d18d4b269f8af94e4f8cae77bdc9a39b5524f8e..9a77a54192be10211da9ebb716f89019290263fc 100644
--- a/drivers/watchdog/imx_watchdog.c
+++ b/drivers/watchdog/imx_watchdog.c
@@ -55,7 +55,8 @@ void reset_cpu(ulong addr)
{
struct watchdog_regs *wdog = (struct watchdog_regs *)WDOG1_BASE_ADDR;
- writew(WCR_WDE, &wdog->wcr);
+ clrsetbits_le16(&wdog->wcr, 0, WCR_WDE);
+
writew(0x5555, &wdog->wsr);
writew(0xaaaa, &wdog->wsr); /* load minimum 1/2 second timeout */
while (1) {
diff --git a/include/configs/cgtqmx6eval.h b/include/configs/cgtqmx6eval.h
index c7d54ee2492155af4d327ed133e213dcd9774d05..7158ab0f2b8307f93bdfd423cfa460699e58f5e8 100644
--- a/include/configs/cgtqmx6eval.h
+++ b/include/configs/cgtqmx6eval.h
@@ -63,6 +63,20 @@
#define CONFIG_USB_KEYBOARD
#define CONFIG_SYS_USB_EVENT_POLL_VIA_CONTROL_EP
+#define CONFIG_CI_UDC
+#define CONFIG_USBD_HS
+#define CONFIG_USB_GADGET_DUALSPEED
+
+#define CONFIG_USB_GADGET
+#define CONFIG_CMD_USB_MASS_STORAGE
+#define CONFIG_USB_FUNCTION_MASS_STORAGE
+#define CONFIG_USB_GADGET_DOWNLOAD
+#define CONFIG_USB_GADGET_VBUS_DRAW 2
+
+#define CONFIG_G_DNL_VENDOR_NUM 0x0525
+#define CONFIG_G_DNL_PRODUCT_NUM 0xa4a5
+#define CONFIG_G_DNL_MANUFACTURER "Congatec"
+
/* Framebuffer */
#define CONFIG_VIDEO
#define CONFIG_VIDEO_IPUV3
diff --git a/include/configs/mx6sabre_common.h b/include/configs/mx6sabre_common.h
index 98eb0427aa5c5e3ebcfb86c2a6814c58f72893ce..2970b831098967d19d41dba5230659f1d1a8795f 100644
--- a/include/configs/mx6sabre_common.h
+++ b/include/configs/mx6sabre_common.h
@@ -238,6 +238,12 @@
#define CONFIG_G_DNL_VENDOR_NUM 0x0525
#define CONFIG_G_DNL_PRODUCT_NUM 0xa4a5
#define CONFIG_G_DNL_MANUFACTURER "FSL"
+
+#define CONFIG_USB_FUNCTION_FASTBOOT
+#define CONFIG_CMD_FASTBOOT
+#define CONFIG_ANDROID_BOOT_IMAGE
+#define CONFIG_FASTBOOT_BUF_ADDR CONFIG_SYS_LOAD_ADDR
+#define CONFIG_FASTBOOT_BUF_SIZE 0x07000000
#endif
#endif /* __MX6QSABRE_COMMON_CONFIG_H */
diff --git a/include/configs/mx7dsabresd.h b/include/configs/mx7dsabresd.h
index ec6e0a6d6bf3f66b1239ee3f68543987ff3e1b0a..ada5de8acaade131743cf70fa7460db4345dde84 100644
--- a/include/configs/mx7dsabresd.h
+++ b/include/configs/mx7dsabresd.h
@@ -24,7 +24,6 @@
#define CONFIG_PHYLIB
#define CONFIG_PHY_BROADCOM
-#define CONFIG_FEC_DMA_MINALIGN 64
/* ENET1 */
#define IMX_FEC_BASE ENET_IPS_BASE_ADDR
@@ -175,8 +174,6 @@
#define CONFIG_SYS_MMC_ENV_PART 0 /* user area */
#define CONFIG_MMCROOT "/dev/mmcblk0p2" /* USDHC1 */
-#define CONFIG_CMD_BMODE
-
/* USB Configs */
#define CONFIG_CMD_USB
#define CONFIG_USB_EHCI