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reform-boundary-uboot

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    Valentin Longchamp authored
    If the DDR3 module supports industrial temperature range and requires
    the x2 refresh rate for that temp range, the refresh period must be
    3.9us instead of 7.8 us.
    
    This was successfuly tested on kmp204x board with some MT41K128M16 DDR3
    RAM chips (no module used, chips directly soldered on board with an SPD
    EEPROM).
    
    Signed-off-by: default avatarValentin Longchamp <valentin.longchamp@keymile.com>
    [York Sun: fix minor conflicts in fsl_ddr_dimm_params.h,
    	   lc_common_dimm_params.c, common_timing_params.h]
    Acked-by: default avatarYork Sun <yorksun@freescale.com>
    7e157b0a
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