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Reform / reform-boundary-uboot
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Shengzhou Liu
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DDR erratum A008336 only applies to DDR controller v5.2.0. DDR controller v5.2.1 already has default 0x43b30002 in EDDRTQCR1 register for optimal performance. Signed-off-by:Shengzhou Liu <Shengzhou.Liu@nxp.com> Reviewed-by:
York Sun <york.sun@nxp.com>
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