Unverified Commit 24123b1b authored by mntmn's avatar mntmn
Browse files

Revert "[WIP] Attempt to get rid of Xil_DCacheFlush"

This reverts commit 6550556d.
parent 35c23456
......@@ -127,7 +127,7 @@ void handle_blitter_dma_op(uint16_t zdata)
printf("M:%.2X R: %d D: %d\n", data->mask, data->user[0], data->u8_user[GFXDATA_U8_DRAWMODE]);
}
pattern_fill_rect2(data->u8_user[GFXDATA_U8_COLORMODE],
pattern_fill_rect(data->u8_user[GFXDATA_U8_COLORMODE],
data->x[0], data->y[0], data->x[1], data->y[1],
data->u8_user[GFXDATA_U8_DRAWMODE], data->mask,
data->rgb[0], data->rgb[1], data->x[2], data->y[2],
......
......@@ -28,12 +28,12 @@ int ethernet_get_backlog();
// FIXME allocate this memory properly
#define TX_BD_LIST_START_ADDRESS 0x3FD00000
#define RX_BD_LIST_START_ADDRESS 0x3FD08000
#define TX_FRAME_ADDRESS 0x3FD10000
#define RX_FRAME_ADDRESS 0x3FD20000
#define RX_BACKLOG_ADDRESS 0x3FE00000 // 32 * 2048 space (64 kB)
#define USB_BLOCK_STORAGE_ADDRESS 0x3FE10000 // FIXME move all of these to a memory table header file
#define TX_BD_LIST_START_ADDRESS 0x0FD00000
#define RX_BD_LIST_START_ADDRESS 0x0FD08000
#define TX_FRAME_ADDRESS 0x0FD10000
#define RX_FRAME_ADDRESS 0x0FD20000
#define RX_BACKLOG_ADDRESS 0x0FE00000 // 32 * 2048 space (64 kB)
#define USB_BLOCK_STORAGE_ADDRESS 0x0FE10000 // FIXME move all of these to a memory table header file
#define RX_FRAME_PAD 4
#define FRAME_SIZE 2048
......
......@@ -813,173 +813,6 @@ engage_cheat_codes:;
}
}
#define PATTERN_FILLRECT_LOOPY2 \
tmpl_data += 2 ; \
if ((y_line + y_offset + 1) % loop_rows == 0) \
tmpl_data = tmpl_base; \
tmpl_x = tmpl_x_base; \
cur_bit = base_bit; \
dp2 += fb_pitch / 4;
void pattern_fill_rect2(uint32_t color_format, uint16_t rect_x1, uint16_t rect_y1, uint16_t w, uint16_t h,
uint8_t draw_mode, uint8_t mask, uint32_t fg_color, uint32_t bg_color,
uint16_t x_offset, uint16_t y_offset,
uint8_t *tmpl_data, uint16_t tmpl_pitch, uint16_t loop_rows)
{
uint32_t rect_x2 = rect_x1 + w;
uint32_t *dp = (uint32_t *)((uint32_t)1024);
uint32_t *dp2 = fb + (rect_y1 * (fb_pitch / 4));
uint8_t* tmpl_base = tmpl_data;
uint16_t tmpl_x, tmpl_x_base;
uint16_t bpp = (color_format) ? 1 : color_format * 2;
uint8_t cur_bit, base_bit, inversion = 0;
uint8_t u8_fg = fg_color >> 24;
uint8_t u8_bg = bg_color >> 24;
uint8_t cur_byte = 0;
uint8_t cur_line = 0;
uint16_t cheat_y = 0;
tmpl_x = (x_offset / 8) % 2;
tmpl_data += (y_offset % loop_rows) * 2;
tmpl_x_base = tmpl_x;
cur_bit = base_bit = (0x80 >> (x_offset % 8));
if (draw_mode & INVERSVID) inversion = 1;
draw_mode &= 0x03;
if (draw_mode == JAM1) {
for (uint16_t y_line = 0; y_line < h; y_line++) {
uint16_t x = rect_x1;
cur_byte = (inversion) ? tmpl_data[tmpl_x] ^ 0xFF : tmpl_data[tmpl_x];
while (x < rect_x2) {
if (w >= 8 && cur_bit == 0x80 && x < rect_x2 - 8) {
if (mask == 0xFF) {
SET_FG_PIXELS;
}
else {
SET_FG_PIXELS_MASK2;
}
x += 8;
}
else {
while (cur_bit > 0 && x < rect_x2) {
if (cur_byte & cur_bit) {
SET_FG_PIXEL_MASK2;
}
x++;
cur_bit >>= 1;
}
cur_bit = 0x80;
}
PATTERN_FILLRECT_LOOPX;
}
memcpy(dp2, dp, w * bpp);
PATTERN_FILLRECT_LOOPY2;
}
return;
}
else if (draw_mode == JAM2) {
for (uint16_t y_line = 0; y_line < h; y_line++) {
uint16_t x = rect_x1;
cur_byte = (inversion) ? tmpl_data[tmpl_x] ^ 0xFF : tmpl_data[tmpl_x];
while (x < rect_x2) {
if (w >= 8 && cur_bit == 0x80 && x < rect_x2 - 8) {
if (mask == 0xFF) {
SET_FG_OR_BG_PIXELS;
}
else {
SET_FG_OR_BG_PIXELS_MASK2;
}
x += 8;
}
else {
while (cur_bit > 0 && x < rect_x2) {
if (cur_byte & cur_bit) {
SET_FG_PIXEL_MASK2;
}
else {
SET_BG_PIXEL_MASK2;
}
x++;
cur_bit >>= 1;
}
cur_bit = 0x80;
}
PATTERN_FILLRECT_LOOPX;
}
memcpy(dp2, dp, w * bpp);
if (mask == 0xFF && loop_rows <= 64) {
cur_line++;
if (cur_line == loop_rows) {
cheat_y = y_line + 1;
goto engage_cheat_codes;
}
}
PATTERN_FILLRECT_LOOPY2;
}
return;
engage_cheat_codes:;
dp = dp2;
dp += (fb_pitch / 4);
uint32_t *sp = dp - (cur_line * (fb_pitch / 4));
for (uint16_t y_line = cheat_y; y_line < h; y_line++) {
switch (color_format) {
case MNTVA_COLOR_8BIT:
memcpy(&((uint8_t *)dp)[rect_x1], &((uint8_t *)sp)[rect_x1], w);
break;
case MNTVA_COLOR_16BIT565:
memcpy(&((uint16_t *)dp)[rect_x1], &((uint16_t *)sp)[rect_x1], w * 2);
break;
case MNTVA_COLOR_32BIT:
memcpy(&dp[rect_x1], &sp[rect_x1], w * 4);
break;
}
dp += fb_pitch / 4;
sp += fb_pitch / 4;
}
return;
}
else { // COMPLEMENT
dp = dp2;
for (uint16_t y_line = 0; y_line < h; y_line++) {
uint16_t x = rect_x1;
cur_byte = (inversion) ? tmpl_data[tmpl_x] ^ 0xFF : tmpl_data[tmpl_x];
while (x < rect_x2) {
if (w >= 8 && cur_bit == 0x80 && x < rect_x2 - 8) {
INVERT_PIXELS;
x += 8;
}
else {
while (cur_bit > 0 && x < rect_x2) {
if (cur_byte & cur_bit) {
INVERT_PIXEL;
}
x++;
cur_bit >>= 1;
}
cur_bit = 0x80;
}
PATTERN_FILLRECT_LOOPX;
}
PATTERN_FILLRECT_LOOPY;
}
}
}
#define TEMPLATE_FILLRECT_LOOPX \
tmpl_x++; \
cur_byte = (inversion) ? tmpl_data[tmpl_x] ^ 0xFF : tmpl_data[tmpl_x];
......
......@@ -72,10 +72,6 @@ void pattern_fill_rect(uint32_t color_format, uint16_t rect_x1, uint16_t rect_y1
uint8_t draw_mode, uint8_t mask, uint32_t fg_color, uint32_t bg_color,
uint16_t x_offset, uint16_t y_offset,
uint8_t *tmpl_data, uint16_t tmpl_pitch, uint16_t loop_rows);
void pattern_fill_rect2(uint32_t color_format, uint16_t rect_x1, uint16_t rect_y1, uint16_t w, uint16_t h,
uint8_t draw_mode, uint8_t mask, uint32_t fg_color, uint32_t bg_color,
uint16_t x_offset, uint16_t y_offset,
uint8_t *tmpl_data, uint16_t tmpl_pitch, uint16_t loop_rows);
void draw_line(int16_t rect_x1, int16_t rect_y1, int16_t rect_x2, int16_t rect_y2, uint16_t len, uint16_t pattern, uint16_t pattern_offset, uint32_t fg_color, uint32_t bg_color, uint32_t color_format, uint8_t mask, uint8_t draw_mode);
void draw_line_solid(int16_t rect_x1, int16_t rect_y1, int16_t rect_x2, int16_t rect_y2, uint16_t len, uint32_t fg_color, uint32_t color_format);
......@@ -160,15 +156,6 @@ enum gfx_minterm_modes {
#define SET_FG_PIXEL32_MASK(a) \
dp[x + a] = fg_color ^ (dp[x + a] & (color_mask ^ 0xFFFFFFFF));
#define SET_FG_PIXEL8_MASK2(a) \
((uint8_t *)dp)[x + a] = u8_fg ^ (((uint8_t *)dp2)[x + a] & (mask ^ 0xFF));
#define SET_BG_PIXEL8_MASK2(a) \
((uint8_t *)dp)[x + a] = u8_bg ^ (((uint8_t *)dp2)[x + a] & (mask ^ 0xFF));
#define SET_FG_PIXEL16_MASK2(a) \
((uint16_t *)dp)[x + a] = fg_color ^ (((uint16_t *)dp2)[x + a] & (color_mask ^ 0xFFFF));
#define SET_FG_PIXEL32_MASK2(a) \
dp[x + a] = fg_color ^ (dp2[x + a] & (color_mask ^ 0xFFFFFFFF));
#define SET_FG_PIXEL \
switch (color_format) { \
case MNTVA_COLOR_8BIT: \
......@@ -189,26 +176,6 @@ enum gfx_minterm_modes {
SET_FG_PIXEL32(0); break; \
}
#define SET_FG_PIXEL_MASK2 \
switch (color_format) { \
case MNTVA_COLOR_8BIT: \
SET_FG_PIXEL8_MASK2(0); break; \
case MNTVA_COLOR_16BIT565: \
SET_FG_PIXEL16(0); break; \
case MNTVA_COLOR_32BIT: \
SET_FG_PIXEL32(0); break; \
}
#define SET_BG_PIXEL_MASK2 \
switch (color_format) { \
case MNTVA_COLOR_8BIT: \
SET_BG_PIXEL8_MASK2(0); break; \
case MNTVA_COLOR_16BIT565: \
SET_BG_PIXEL16(0); break; \
case MNTVA_COLOR_32BIT: \
SET_BG_PIXEL32(0); break; \
}
#define SET_BG_PIXEL \
switch (color_format) { \
case MNTVA_COLOR_8BIT: \
......@@ -229,74 +196,6 @@ enum gfx_minterm_modes {
SET_BG_PIXEL32(0); break; \
}
#define SET_FG_PIXELS_MASK2 \
switch (color_format) { \
case MNTVA_COLOR_8BIT: \
if (cur_byte & 0x80) SET_FG_PIXEL8_MASK2(0); \
if (cur_byte & 0x40) SET_FG_PIXEL8_MASK2(1); \
if (cur_byte & 0x20) SET_FG_PIXEL8_MASK2(2); \
if (cur_byte & 0x10) SET_FG_PIXEL8_MASK2(3); \
if (cur_byte & 0x08) SET_FG_PIXEL8_MASK2(4); \
if (cur_byte & 0x04) SET_FG_PIXEL8_MASK2(5); \
if (cur_byte & 0x02) SET_FG_PIXEL8_MASK2(6); \
if (cur_byte & 0x01) SET_FG_PIXEL8_MASK2(7); \
break; \
case MNTVA_COLOR_16BIT565: \
if (cur_byte & 0x80) SET_FG_PIXEL16(0); \
if (cur_byte & 0x40) SET_FG_PIXEL16(1); \
if (cur_byte & 0x20) SET_FG_PIXEL16(2); \
if (cur_byte & 0x10) SET_FG_PIXEL16(3); \
if (cur_byte & 0x08) SET_FG_PIXEL16(4); \
if (cur_byte & 0x04) SET_FG_PIXEL16(5); \
if (cur_byte & 0x02) SET_FG_PIXEL16(6); \
if (cur_byte & 0x01) SET_FG_PIXEL16(7); \
break; \
case MNTVA_COLOR_32BIT: \
if (cur_byte & 0x80) SET_FG_PIXEL32(0); \
if (cur_byte & 0x40) SET_FG_PIXEL32(1); \
if (cur_byte & 0x20) SET_FG_PIXEL32(2); \
if (cur_byte & 0x10) SET_FG_PIXEL32(3); \
if (cur_byte & 0x08) SET_FG_PIXEL32(4); \
if (cur_byte & 0x04) SET_FG_PIXEL32(5); \
if (cur_byte & 0x02) SET_FG_PIXEL32(6); \
if (cur_byte & 0x01) SET_FG_PIXEL32(7); \
break; \
}
#define SET_FG_OR_BG_PIXELS_MASK2 \
switch (color_format) { \
case MNTVA_COLOR_8BIT: \
if (cur_byte & 0x80) SET_FG_PIXEL8_MASK2(0) else SET_BG_PIXEL8_MASK2(0) \
if (cur_byte & 0x40) SET_FG_PIXEL8_MASK2(1) else SET_BG_PIXEL8_MASK2(1) \
if (cur_byte & 0x20) SET_FG_PIXEL8_MASK2(2) else SET_BG_PIXEL8_MASK2(2) \
if (cur_byte & 0x10) SET_FG_PIXEL8_MASK2(3) else SET_BG_PIXEL8_MASK2(3) \
if (cur_byte & 0x08) SET_FG_PIXEL8_MASK2(4) else SET_BG_PIXEL8_MASK2(4) \
if (cur_byte & 0x04) SET_FG_PIXEL8_MASK2(5) else SET_BG_PIXEL8_MASK2(5) \
if (cur_byte & 0x02) SET_FG_PIXEL8_MASK2(6) else SET_BG_PIXEL8_MASK2(6) \
if (cur_byte & 0x01) SET_FG_PIXEL8_MASK2(7) else SET_BG_PIXEL8_MASK2(7) \
break; \
case MNTVA_COLOR_16BIT565: \
if (cur_byte & 0x80) SET_FG_PIXEL16(0) else SET_BG_PIXEL16(0) \
if (cur_byte & 0x40) SET_FG_PIXEL16(1) else SET_BG_PIXEL16(1) \
if (cur_byte & 0x20) SET_FG_PIXEL16(2) else SET_BG_PIXEL16(2) \
if (cur_byte & 0x10) SET_FG_PIXEL16(3) else SET_BG_PIXEL16(3) \
if (cur_byte & 0x08) SET_FG_PIXEL16(4) else SET_BG_PIXEL16(4) \
if (cur_byte & 0x04) SET_FG_PIXEL16(5) else SET_BG_PIXEL16(5) \
if (cur_byte & 0x02) SET_FG_PIXEL16(6) else SET_BG_PIXEL16(6) \
if (cur_byte & 0x01) SET_FG_PIXEL16(7) else SET_BG_PIXEL16(7) \
break; \
case MNTVA_COLOR_32BIT: \
if (cur_byte & 0x80) SET_FG_PIXEL32(0) else SET_BG_PIXEL32(0) \
if (cur_byte & 0x40) SET_FG_PIXEL32(1) else SET_BG_PIXEL32(1) \
if (cur_byte & 0x20) SET_FG_PIXEL32(2) else SET_BG_PIXEL32(2) \
if (cur_byte & 0x10) SET_FG_PIXEL32(3) else SET_BG_PIXEL32(3) \
if (cur_byte & 0x08) SET_FG_PIXEL32(4) else SET_BG_PIXEL32(4) \
if (cur_byte & 0x04) SET_FG_PIXEL32(5) else SET_BG_PIXEL32(5) \
if (cur_byte & 0x02) SET_FG_PIXEL32(6) else SET_BG_PIXEL32(6) \
if (cur_byte & 0x01) SET_FG_PIXEL32(7) else SET_BG_PIXEL32(7) \
break; \
}
#define SET_FG_PIXELS \
switch (color_format) { \
case MNTVA_COLOR_8BIT: \
......
......@@ -58,9 +58,6 @@ typedef u8 uint8_t;
#define IIC_SCLK_RATE 400000
#define GPIO_DEVICE_ID XPAR_XGPIOPS_0_DEVICE_ID
#define CACHE_TRICK_ADDR_LOWER 0x7800000
#define CACHE_TRICK_ADDR_UPPER 0x7F00000
#define I2C_PAUSE 10
// I2C controller instance
......@@ -98,8 +95,6 @@ float xadc_get_int_voltage() {
// which can be replaced by the DMA acceleration functionality entirely, but some
// software still relies on this legacy register.
unsigned int cur_mem_offset = 0x3500000;
// Memory offset for tricking the ARM CPU into doing a cache commit to memory.
unsigned int cur_cache_trick_offset = CACHE_TRICK_ADDR_LOWER;
int hdmi_ctrl_write_byte(u8 addr, u8 value) {
u8 buffer[2];
......@@ -491,13 +486,13 @@ void pixelclock_init(int mhz) {
//XClk_Wiz_WriteReg(XPAR_CLK_WIZ_0_BASEADDR, 0x25C, 0x00000001);
phase = XClk_Wiz_ReadReg(XPAR_CLK_WIZ_0_BASEADDR, 0x20C);
printf("CLK phase: %lu\n", phase);
//printf("CLK phase: %lu\n", phase);
duty = XClk_Wiz_ReadReg(XPAR_CLK_WIZ_0_BASEADDR, 0x210);
printf("CLK duty: %lu\n", duty);
//printf("CLK duty: %lu\n", duty);
divide = XClk_Wiz_ReadReg(XPAR_CLK_WIZ_0_BASEADDR, 0x208);
printf("CLK divide: %lu\n", divide);
//printf("CLK divide: %lu\n", divide);
muldiv = XClk_Wiz_ReadReg(XPAR_CLK_WIZ_0_BASEADDR, 0x200);
printf("CLK muldiv: %lu\n", muldiv);
//printf("CLK muldiv: %lu\n", muldiv);
}
void pixelclock_init_2(struct zz_video_mode *mode) {
......@@ -521,13 +516,13 @@ void pixelclock_init_2(struct zz_video_mode *mode) {
//XClk_Wiz_WriteReg(XPAR_CLK_WIZ_0_BASEADDR, 0x25C, 0x00000001);
phase = XClk_Wiz_ReadReg(XPAR_CLK_WIZ_0_BASEADDR, 0x20C);
printf("CLK phase: %lu\n", phase);
//printf("CLK phase: %lu\n", phase);
duty = XClk_Wiz_ReadReg(XPAR_CLK_WIZ_0_BASEADDR, 0x210);
printf("CLK duty: %lu\n", duty);
//printf("CLK duty: %lu\n", duty);
divide = XClk_Wiz_ReadReg(XPAR_CLK_WIZ_0_BASEADDR, 0x208);
printf("CLK divide: %lu\n", divide);
//printf("CLK divide: %lu\n", divide);
muldiv = XClk_Wiz_ReadReg(XPAR_CLK_WIZ_0_BASEADDR, 0x200);
printf("CLK muldiv: %lu\n", muldiv);
//printf("CLK muldiv: %lu\n", muldiv);
}
// FIXME!
......@@ -614,24 +609,24 @@ void video_system_init(int hres, int vres, int htotal, int vtotal, int mhz,
void video_system_init_2(struct zz_video_mode *mode, int hdiv, int vdiv) {
printf("VSI: %d x %d [%d x %d] %d MHz %d Hz, hdiv: %d vdiv: %d\n", mode->hres,
mode->vres, mode->hmax, mode->vmax, mode->mhz, mode->vhz, hdiv, vdiv);
/*printf("VSI: %d x %d [%d x %d] %d MHz %d Hz, hdiv: %d vdiv: %d\n", mode->hres,
mode->vres, mode->hmax, mode->vmax, mode->mhz, mode->vhz, hdiv, vdiv);*/
printf("pixelclock_init()...\n");
//printf("pixelclock_init()...\n");
pixelclock_init_2(mode);
printf("...done.\n");
//printf("...done.\n");
printf("hdmi_set_video_mode()...\n");
hdmi_set_video_mode(mode->hres, mode->vres, mode->mhz, mode->vhz, mode->hdmi);
//printf("hdmi_set_video_mode()...\n");
//hdmi_set_video_mode(hres, vres, mhz, vhz, hdmi);
printf("hdmi_ctrl_init()...\n");
//printf("hdmi_ctrl_init()...\n");
hdmi_ctrl_init();
printf("init_vdma()...\n");
//printf("init_vdma()...\n");
init_vdma(mode->hres, mode->vres, hdiv, vdiv, (u32)framebuffer + framebuffer_pan_offset);
printf("...done.\n");
//printf("...done.\n");
dump_vdma_status(&vdma);
//dump_vdma_status(&vdma);
}
// Our address space is relative to the autoconfig base address (for example, it could be 0x600000)
......@@ -1922,11 +1917,7 @@ int main() {
// we flush the cache at regular intervals to avoid too much visible cache activity on the screen
// FIXME make this adjustable for user
if (cache_counter > 25000) {
//Xil_DCacheFlush();
memcpy((uint32_t*) ((u32)cur_cache_trick_offset - 0x100000), (uint32_t*) ((u32)cur_cache_trick_offset), 0x10000);
cur_cache_trick_offset += 0x10000;
if (cur_cache_trick_offset > CACHE_TRICK_ADDR_UPPER)
cur_cache_trick_offset = CACHE_TRICK_ADDR_LOWER;
Xil_DCacheFlush();
cache_counter = 0;
}
cache_counter++;
......
......@@ -43,11 +43,11 @@
`define Z3_SIZE_256MB 32'h10000000 // 256MB for Zorro 3
`define ARM_MEMORY_START 32'h001f0000
`define VIDEOCAP_ADDR 32'h01000000 // ARM_MEMORY_START+0xe0_0000
`define TX_FRAME_ADDRESS 32'h3fd10000
`define RX_FRAME_ADDRESS 32'h3fd20000
`define RX_BACKLOG_ADDRESS 32'h3fe00000
`define TX_FRAME_ADDRESS 32'h0fd10000
`define RX_FRAME_ADDRESS 32'h0fd20000
`define RX_BACKLOG_ADDRESS 32'h0fe00000
`define FRAME_SIZE 24'h2048
`define USB_BLOCK_STORAGE_ADDRESS 32'h3fe10000
`define USB_BLOCK_STORAGE_ADDRESS 32'h0fe10000
`define C_M00_AXI_TARGET_SLAVE_BASE_ADDR 32'h10000000
`define C_M00_AXI_ID_WIDTH 1
......@@ -1474,7 +1474,7 @@ module MNTZorro_v0_1_S00_AXI
end
'h0100: begin
if (!z3_curpic) begin
data_z3_hi16 <= 'b1100_1111_1111_1111; // next board related (1), 256MB 1024MB fixme
data_z3_hi16 <= 'b1011_1111_1111_1111; // next board related (1), 256MB 1024MB fixme
end else begin
data_z3_hi16 <= 'b0100_1111_1111_1111; // next board unrelated (0), 256MB 1024MB fixme
end
......@@ -1588,7 +1588,7 @@ module MNTZorro_v0_1_S00_AXI
reg_low <= ram_low + 'h1000;
reg_high <= ram_low + 'h2000;
z3_ram_high <= z3_ram_low + `Z3_SIZE_256MB;
z3_ram_high <= z3_ram_low + `Z3_SIZE_128MB;
z3_fast_high <= z3_fast_low + `Z3_SIZE_256MB;
z3_reg_low <= z3_ram_low + 'h1000;
z3_reg_high <= z3_ram_low + 'h2000;
......
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